2022-12-05 06:06:44

by Bin Meng

Subject: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V

Per RISC-V semihosting spec [1], adapt the existing Arm semihosting
earlycon driver to RISC-V.

[1] https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Bin Meng <[email protected]>
---

drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/earlycon-arm-semihost.c | 17 ++++++++++++++++-
2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 434f83168546..e94d1265151c 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE

config SERIAL_EARLYCON_ARM_SEMIHOST
bool "Early console using ARM semihosting"
- depends on ARM64 || ARM
+ depends on ARM64 || ARM || RISCV
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
index fcdec5f42376..25a0f91926a3 100644
--- a/drivers/tty/serial/earlycon-arm-semihost.c
+++ b/drivers/tty/serial/earlycon-arm-semihost.c
@@ -6,6 +6,10 @@
* Adapted for ARM and earlycon:
* Copyright (C) 2014 Linaro Ltd.
* Author: Rob Herring <[email protected]>
+ *
+ * Adapted for RISC-V and earlycon:
+ * Copyright (C) 2022 tinylab.org
+ * Author: Bin Meng <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/console.h>
@@ -23,7 +27,18 @@
*/
static void smh_putc(struct uart_port *port, unsigned char c)
{
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_RISCV)
+ asm volatile("addi a1, %0, 0\n"
+ "addi a0, zero, 3\n"
+ ".balign 16\n"
+ ".option push\n"
+ ".option norvc\n"
+ "slli zero, zero, 0x1f\n"
+ "ebreak\n"
+ "srai zero, zero, 0x7\n"
+ ".option pop\n"
+ : : "r" (&c) : "a0", "a1", "memory");
+#elif defined(CONFIG_ARM64)
asm volatile("mov x1, %0\n"
"mov x0, #3\n"
"hlt 0xf000\n"
--
2.34.1

2022-12-06 06:47:22

by Jiri Slaby

Subject: Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V

On 05. 12. 22, 6:00, Bin Meng wrote:
...
> --- a/drivers/tty/serial/earlycon-arm-semihost.c
> +++ b/drivers/tty/serial/earlycon-arm-semihost.c
...
> @@ -23,7 +27,18 @@
> */
> static void smh_putc(struct uart_port *port, unsigned char c)
> {
> -#ifdef CONFIG_ARM64
> +#if defined(CONFIG_RISCV)
> + asm volatile("addi a1, %0, 0\n"
> + "addi a0, zero, 3\n"
> + ".balign 16\n"
> + ".option push\n"
> + ".option norvc\n"
> + "slli zero, zero, 0x1f\n"
> + "ebreak\n"
> + "srai zero, zero, 0x7\n"
> + ".option pop\n"
> + : : "r" (&c) : "a0", "a1", "memory");
> +#elif defined(CONFIG_ARM64)
> asm volatile("mov x1, %0\n"
> "mov x0, #3\n"
> "hlt 0xf000\n"

Hmm, can we implement all those smh_putc() variants in respective
arch/*/include/semihost.h instead?

thanks,
--
js
suse labs

2022-12-06 14:47:06

by Bin Meng

Subject: Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V

On Tue, Dec 6, 2022 at 2:47 PM Jiri Slaby <[email protected]> wrote:
>
> On 05. 12. 22, 6:00, Bin Meng wrote:
> ...
> > --- a/drivers/tty/serial/earlycon-arm-semihost.c
> > +++ b/drivers/tty/serial/earlycon-arm-semihost.c
> ...
> > @@ -23,7 +27,18 @@
> > */
> > static void smh_putc(struct uart_port *port, unsigned char c)
> > {
> > -#ifdef CONFIG_ARM64
> > +#if defined(CONFIG_RISCV)
> > + asm volatile("addi a1, %0, 0\n"
> > + "addi a0, zero, 3\n"
> > + ".balign 16\n"
> > + ".option push\n"
> > + ".option norvc\n"
> > + "slli zero, zero, 0x1f\n"
> > + "ebreak\n"
> > + "srai zero, zero, 0x7\n"
> > + ".option pop\n"
> > + : : "r" (&c) : "a0", "a1", "memory");
> > +#elif defined(CONFIG_ARM64)
> > asm volatile("mov x1, %0\n"
> > "mov x0, #3\n"
> > "hlt 0xf000\n"
>
> Hmm, can we implement all those smh_putc() variants in respective
> arch/*/include/semihost.h instead?
>

I think so. Will do in v2.

Regards,
Bin