Add following peripherals :
- AO Clock + Reset Controller
- AO Secure Node, used for chipid
- Pinctrl
- UARTs
- SAR-ADC
- USB
- Mali GPU
USB depends on the PCIE clock and missing Reset bindings.
SARADC, USB & Mali GPU bindings are yet to be merged but are
in review.
Jerome Brunet (3):
arm64: dts: meson: g12a: add pinctrl support controllers
arm64: dts: meson: g12a: add uart_ao_a pinctrl
arm64: dts: meson: g12a: add reset controller
Neil Armstrong (6):
arm64: dts: meson: g12a: Add AO Clock + Reset Controller support
arm64: dts: meson: g12a: Add AO Secure node
arm64: dts: meson: g12a: Add UART A, B & C nodes and pins
arm64: dts: meson: g12a: Add SAR ADC node
arm64: dts: meson: g12a: Add G12A USB nodes
arm64: dts: meson: g12a: Add mali-g31 gpu node
.../boot/dts/amlogic/meson-g12a-u200.dts | 2 +
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 290 ++++++++++++++++++
2 files changed, 292 insertions(+)
--
2.20.1
Add nodes and properties for the AO Clocks and Resets.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 191d31db9853..0eb5220da82c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -122,6 +122,23 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+ rti: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x0 0x0 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x1000>;
+
+ clkc_AO: clock-controller {
+ compatible = "amlogic,meson-g12a-aoclkc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "mpeg-clk";
+ };
+ };
+
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
2.20.1
This patch adds the SAR ADC controller node.
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 50e2cd36e08b..3bcddd412aa1 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -278,6 +278,20 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ saradc: adc@9000 {
+ compatible = "amlogic,meson-g12a-saradc",
+ "amlogic,meson-saradc";
+ reg = <0x0 0x9000 0x0 0x48>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&clkc_AO CLKID_AO_SAR_ADC>,
+ <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+ <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "adc_clk", "adc_sel";
+ status = "disabled";
+ };
};
gic: interrupt-controller@ffc01000 {
--
2.20.1
This patch adds the 2 UART nodes in the EE power domain with the corresponding
pinctrl nodes.
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 2a700bb45d04..50e2cd36e08b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -113,6 +113,61 @@
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 0 86>;
};
+
+ uart_a_pins: uart_a {
+ mux {
+ groups = "uart_a_tx",
+ "uart_a_rx";
+ function = "uart_a";
+ bias-disable;
+ };
+ };
+
+ uart_a_cts_rts_pins: uart_a_cts_rts {
+ mux {
+ groups = "uart_a_cts",
+ "uart_a_rts";
+ function = "uart_a";
+ bias-disable;
+ };
+ };
+
+ uart_ao_a_c_pins: uart_ao_a_c {
+ mux {
+ groups = "uart_ao_a_rx_c",
+ "uart_ao_a_tx_c";
+ function = "uart_ao_a_c";
+ bias-disable;
+ };
+ };
+
+ uart_b_pins: uart_b {
+ mux {
+ groups = "uart_b_tx",
+ "uart_b_rx";
+ function = "uart_b";
+ bias-disable;
+ };
+ };
+
+ uart_c_pins: uart_c {
+ mux {
+ groups = "uart_c_tx",
+ "uart_c_rx";
+ function = "uart_c";
+ bias-disable;
+ };
+ };
+
+ uart_c_cts_rts_pins: uart_c_cts_rts {
+ mux {
+ groups = "uart_c_cts",
+ "uart_c_rts";
+ function = "uart_c";
+ bias-disable;
+ };
+ };
+ };
};
hiu: bus@3c000 {
@@ -256,6 +311,33 @@
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
};
+
+ uart_C: serial@22000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_B: serial@23000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x23000 0x0 0x18>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_A: serial@24000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x24000 0x0 0x18>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
};
};
--
2.20.1
This patch adds the ARM Mali G31 GPU node.
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 991883ea023c..bd2d9379dcb5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -431,6 +431,33 @@
snps,quirk-frame-length-adjustment;
};
};
+
+ mali: gpu@ffe40000 {
+ compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
+ reg = <0x0 0xffe40000 0x0 0x40000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpu", "mmu", "job";
+ clocks = <&clkc CLKID_MALI>;
+ resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <800000000>,
+ <0>; /* Do Nothing */
+ };
};
timer {
--
2.20.1
This patch adds the nodes for the USB Complex found in the Amlogic
G12A SoC.
It includes the :
- 2 USB2 PHYs
- 1 USB3 + PCIE Combo PHY
- the USB Glue with it's DWC2 and DWC3 sub-nodes
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 78 +++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 3bcddd412aa1..991883ea023c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -3,9 +3,13 @@
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/g12a-clkc.h>
+#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
/ {
compatible = "amlogic,g12a";
@@ -170,6 +174,26 @@
};
};
+ usb2_phy0: phy@36000 {
+ compatible = "amlogic,g12a-usb2-phy";
+ reg = <0x0 0x36000 0x0 0x2000>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ resets = <&reset RESET_USB_PHY20>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
+ usb2_phy1: phy@3a000 {
+ compatible = "amlogic,g12a-usb2-phy";
+ reg = <0x0 0x3a000 0x0 0x2000>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ resets = <&reset RESET_USB_PHY21>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
hiu: bus@3c000 {
compatible = "simple-bus";
reg = <0x0 0x3c000 0x0 0x1400>;
@@ -190,6 +214,18 @@
};
};
};
+
+ usb3_pcie_phy: phy@46000 {
+ compatible = "amlogic,g12a-usb3-pcie-phy";
+ reg = <0x0 0x46000 0x0 0x2000>;
+ clocks = <&clkc CLKID_PCIE_PLL>;
+ clock-names = "ref_clk";
+ resets = <&reset RESET_PCIE_PHY>;
+ reset-names = "phy";
+ assigned-clocks = <&clkc CLKID_PCIE_PLL>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ };
};
aobus: bus@ff800000 {
@@ -353,6 +389,48 @@
status = "disabled";
};
};
+
+ usb: usb@ffe09000 {
+ status = "disabled";
+ compatible = "amlogic,meson-g12a-usb-ctrl";
+ reg = <0x0 0xffe09000 0x0 0xa0>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>;
+ resets = <&reset RESET_USB>;
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy0>, <&usb2_phy1>,
+ <&usb3_pcie_phy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
+
+ dwc2: usb@ff400000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "ddr";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ status = "disabled";
+ };
+
+ dwc3: usb@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_u2_susphy_quirk;
+ snps,quirk-frame-length-adjustment;
+ };
+ };
};
timer {
--
2.20.1
From: Jerome Brunet <[email protected]>
Add the reset controller device of g12a SoC family
Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index f8f055c49f9a..2a700bb45d04 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -245,6 +245,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
+ reset: reset-controller@1004 {
+ compatible = "amlogic,meson-g12a-reset",
+ "amlogic,meson-axg-reset";
+ reg = <0x0 0x1004 0x0 0x9c>;
+ #reset-cells = <1>;
+ };
+
clk_msr: clock-measure@18000 {
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
--
2.20.1
From: Jerome Brunet <[email protected]>
Add the peripheral and always-on pinctrl controllers to the g12a soc.
Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 41 +++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index f2fc0f654150..c141cc7f6b09 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -91,6 +91,28 @@
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
+
+ periphs_pinctrl: pinctrl@40 {
+ compatible = "amlogic,meson-g12a-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@40 {
+ reg = <0x0 0x40 0x0 0x4c>,
+ <0x0 0xe8 0x0 0x18>,
+ <0x0 0x120 0x0 0x18>,
+ <0x0 0x2c0 0x0 0x40>,
+ <0x0 0x340 0x0 0x1c>;
+ reg-names = "gpio",
+ "pull",
+ "pull-enable",
+ "mux",
+ "ds";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 0 86>;
+ };
};
hiu: bus@3c000 {
@@ -137,6 +159,25 @@
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
+
+ ao_pinctrl: pinctrl@14 {
+ compatible = "amlogic,meson-g12a-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio_ao: bank@14 {
+ reg = <0x0 0x14 0x0 0x8>,
+ <0x0 0x1c 0x0 0x8>,
+ <0x0 0x24 0x0 0x14>;
+ reg-names = "mux",
+ "ds",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ao_pinctrl 0 0 15>;
+ };
+ };
};
sec_AO: ao-secure@140 {
--
2.20.1
From: Jerome Brunet <[email protected]>
Add the always on UART pinctrl setting to the g12a soc DT and
use it for the u200 reference design
Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
.../arm64/boot/dts/amlogic/meson-g12a-u200.dts | 2 ++
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
index c44dbdddf2cf..f2afd0bf3e28 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
@@ -25,5 +25,7 @@
&uart_AO {
status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index c141cc7f6b09..f8f055c49f9a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -177,6 +177,24 @@
#gpio-cells = <2>;
gpio-ranges = <&ao_pinctrl 0 0 15>;
};
+
+ uart_ao_a_pins: uart_a_ao {
+ mux {
+ groups = "uart_ao_a_tx",
+ "uart_ao_a_rx";
+ function = "uart_ao_a";
+ bias-disable;
+ };
+ };
+
+ uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+ mux {
+ groups = "uart_ao_a_cts",
+ "uart_ao_a_rts";
+ function = "uart_ao_a";
+ bias-disable;
+ };
+ };
};
};
--
2.20.1
This adds the Always-On ao-secure system control registers node,
which is used by the meson-gx-socinfo driver to detect the SoC IDs.
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 0eb5220da82c..f2fc0f654150 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -139,6 +139,12 @@
};
};
+ sec_AO: ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
+ };
+
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
2.20.1
On 07/03/2019 16:13, Neil Armstrong wrote:
> From: Jerome Brunet <[email protected]>
>
> Add the always on UART pinctrl setting to the g12a soc DT and
> use it for the u200 reference design
>
> Signed-off-by: Jerome Brunet <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> .../arm64/boot/dts/amlogic/meson-g12a-u200.dts | 2 ++
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> index c44dbdddf2cf..f2afd0bf3e28 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> @@ -25,5 +25,7 @@
>
> &uart_AO {
> status = "okay";
> + pinctrl-0 = <&uart_ao_a_pins>;
> + pinctrl-names = "default";
> };
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index c141cc7f6b09..f8f055c49f9a 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -177,6 +177,24 @@
> #gpio-cells = <2>;
> gpio-ranges = <&ao_pinctrl 0 0 15>;
> };
> +
> + uart_ao_a_pins: uart_a_ao {
> + mux {
> + groups = "uart_ao_a_tx",
> + "uart_ao_a_rx";
> + function = "uart_ao_a";
> + bias-disable;
> + };
> + };
> +
> + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
> + mux {
> + groups = "uart_ao_a_cts",
> + "uart_ao_a_rts";
> + function = "uart_ao_a";
> + bias-disable;
> + };
> + };
> };
> };
>
>
Will move this out of this patchset to the boards patchset
Neil Armstrong <[email protected]> writes:
> This patch adds the 2 UART nodes in the EE power domain with the corresponding
> pinctrl nodes.
>
> Signed-off-by: Neil Armstrong <[email protected]>
Similar to PATCH 4/9, are you wanting to move this to the board series?
Kevin
> ---
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++
> 1 file changed, 82 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index 2a700bb45d04..50e2cd36e08b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -113,6 +113,61 @@
> #gpio-cells = <2>;
> gpio-ranges = <&periphs_pinctrl 0 0 86>;
> };
> +
> + uart_a_pins: uart_a {
> + mux {
> + groups = "uart_a_tx",
> + "uart_a_rx";
> + function = "uart_a";
> + bias-disable;
> + };
> + };
> +
> + uart_a_cts_rts_pins: uart_a_cts_rts {
> + mux {
> + groups = "uart_a_cts",
> + "uart_a_rts";
> + function = "uart_a";
> + bias-disable;
> + };
> + };
> +
> + uart_ao_a_c_pins: uart_ao_a_c {
> + mux {
> + groups = "uart_ao_a_rx_c",
> + "uart_ao_a_tx_c";
> + function = "uart_ao_a_c";
> + bias-disable;
> + };
> + };
> +
> + uart_b_pins: uart_b {
> + mux {
> + groups = "uart_b_tx",
> + "uart_b_rx";
> + function = "uart_b";
> + bias-disable;
> + };
> + };
> +
> + uart_c_pins: uart_c {
> + mux {
> + groups = "uart_c_tx",
> + "uart_c_rx";
> + function = "uart_c";
> + bias-disable;
> + };
> + };
> +
> + uart_c_cts_rts_pins: uart_c_cts_rts {
> + mux {
> + groups = "uart_c_cts",
> + "uart_c_rts";
> + function = "uart_c";
> + bias-disable;
> + };
> + };
> + };
> };
>
> hiu: bus@3c000 {
> @@ -256,6 +311,33 @@
> compatible = "amlogic,meson-g12a-clk-measure";
> reg = <0x0 0x18000 0x0 0x10>;
> };
> +
> + uart_C: serial@22000 {
> + compatible = "amlogic,meson-gx-uart";
> + reg = <0x0 0x22000 0x0 0x18>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> + uart_B: serial@23000 {
> + compatible = "amlogic,meson-gx-uart";
> + reg = <0x0 0x23000 0x0 0x18>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> + uart_A: serial@24000 {
> + compatible = "amlogic,meson-gx-uart";
> + reg = <0x0 0x24000 0x0 0x18>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> };
> };
>
> --
> 2.20.1
Kevin Hilman <[email protected]> writes:
> Neil Armstrong <[email protected]> writes:
>
>> This patch adds the 2 UART nodes in the EE power domain with the corresponding
>> pinctrl nodes.
>>
>> Signed-off-by: Neil Armstrong <[email protected]>
>
> Similar to PATCH 4/9, are you wanting to move this to the board series?
Nevermind, I misunderstood how you were splitting up the two series.
Kevin
Neil Armstrong <[email protected]> writes:
> On 07/03/2019 16:13, Neil Armstrong wrote:
>> From: Jerome Brunet <[email protected]>
>>
>> Add the always on UART pinctrl setting to the g12a soc DT and
>> use it for the u200 reference design
>>
>> Signed-off-by: Jerome Brunet <[email protected]>
>> Signed-off-by: Neil Armstrong <[email protected]>
>> ---
>> .../arm64/boot/dts/amlogic/meson-g12a-u200.dts | 2 ++
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> index c44dbdddf2cf..f2afd0bf3e28 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> @@ -25,5 +25,7 @@
>>
>> &uart_AO {
>> status = "okay";
>> + pinctrl-0 = <&uart_ao_a_pins>;
>> + pinctrl-names = "default";
>> };
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index c141cc7f6b09..f8f055c49f9a 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -177,6 +177,24 @@
>> #gpio-cells = <2>;
>> gpio-ranges = <&ao_pinctrl 0 0 15>;
>> };
>> +
>> + uart_ao_a_pins: uart_a_ao {
>> + mux {
>> + groups = "uart_ao_a_tx",
>> + "uart_ao_a_rx";
>> + function = "uart_ao_a";
>> + bias-disable;
>> + };
>> + };
>> +
>> + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
>> + mux {
>> + groups = "uart_ao_a_cts",
>> + "uart_ao_a_rts";
>> + function = "uart_ao_a";
>> + bias-disable;
>> + };
>> + };
>> };
>> };
>>
>>
>
> Will move this out of this patchset to the boards patchset
I assume you meant you'd move the first hunk, the one that modifies the
u200 board to the other series, but keep this hunk in this series?
Kevin
On 12/03/2019 22:15, Kevin Hilman wrote:
> Neil Armstrong <[email protected]> writes:
>
>> On 07/03/2019 16:13, Neil Armstrong wrote:
>>> From: Jerome Brunet <[email protected]>
>>>
>>> Add the always on UART pinctrl setting to the g12a soc DT and
>>> use it for the u200 reference design
>>>
>>> Signed-off-by: Jerome Brunet <[email protected]>
>>> Signed-off-by: Neil Armstrong <[email protected]>
>>> ---
>>> .../arm64/boot/dts/amlogic/meson-g12a-u200.dts | 2 ++
>>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
>>> 2 files changed, 20 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>>> index c44dbdddf2cf..f2afd0bf3e28 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>>> @@ -25,5 +25,7 @@
>>>
>>> &uart_AO {
>>> status = "okay";
>>> + pinctrl-0 = <&uart_ao_a_pins>;
>>> + pinctrl-names = "default";
>>> };
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>>> index c141cc7f6b09..f8f055c49f9a 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>>> @@ -177,6 +177,24 @@
>>> #gpio-cells = <2>;
>>> gpio-ranges = <&ao_pinctrl 0 0 15>;
>>> };
>>> +
>>> + uart_ao_a_pins: uart_a_ao {
>>> + mux {
>>> + groups = "uart_ao_a_tx",
>>> + "uart_ao_a_rx";
>>> + function = "uart_ao_a";
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
>>> + mux {
>>> + groups = "uart_ao_a_cts",
>>> + "uart_ao_a_rts";
>>> + function = "uart_ao_a";
>>> + bias-disable;
>>> + };
>>> + };
>>> };
>>> };
>>>
>>>
>>
>> Will move this out of this patchset to the boards patchset
>
> I assume you meant you'd move the first hunk, the one that modifies the
> u200 board to the other series, but keep this hunk in this series?
Yep I will remove the board chunk in the v2 of this patchset.
Neil
>
> Kevin
>
Hi Neil,
On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <[email protected]> wrote:
>
> Add nodes and properties for the AO Clocks and Resets.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> Signed-off-by: Jerome Brunet <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index 191d31db9853..0eb5220da82c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -122,6 +122,23 @@
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
>
> + rti: sys-ctrl@0 {
> + compatible = "amlogic,meson-gx-ao-sysctrl",
> + "simple-mfd", "syscon";
> + reg = <0x0 0x0 0x0 0x1000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x0 0x0 0x1000>;
is this supposed to be 0x1000 (GX uses 0x100 here)?
my understanding is that G12A has the AO CEC at aobus + 0x100, so
using a size of 0x1000 would make it overlap
Regards
Martin
On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <[email protected]> wrote:
>
> This adds the Always-On ao-secure system control registers node,
> which is used by the meson-gx-socinfo driver to detect the SoC IDs.
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <[email protected]> wrote:
>
> This patch adds the SAR ADC controller node.
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Hi Neil,
On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <[email protected]> wrote:
>
> This patch adds the 2 UART nodes in the EE power domain with the corresponding
> pinctrl nodes.
there are 3 UART controllers in the EE power domain
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++
> 1 file changed, 82 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index 2a700bb45d04..50e2cd36e08b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -113,6 +113,61 @@
> #gpio-cells = <2>;
> gpio-ranges = <&periphs_pinctrl 0 0 86>;
> };
> +
> + uart_a_pins: uart_a {
(this applies to all new nodes)
we started using dashes for the node names for new pin definitions on
the GX SoCs.
I don't remember where it was discussed exactly but I think this was
requested from Rob
since G12A is a new SoC we should do it "right" from the beginning
[...]
> + uart_ao_a_c_pins: uart_ao_a_c {
> + mux {
> + groups = "uart_ao_a_rx_c",
> + "uart_ao_a_tx_c";
> + function = "uart_ao_a_c";
> + bias-disable;
> + };
> + };
I'm fine with this part if you mention it in the subject and/or the description
uart_ao_a_c routes two pins from bank C (from the EE domain) to the
uart_AO controller (from the AO domain)
> + uart_b_pins: uart_b {
> + mux {
> + groups = "uart_b_tx",
> + "uart_b_rx";
> + function = "uart_b";
> + bias-disable;
> + };
> + };
> +
> + uart_c_pins: uart_c {
> + mux {
> + groups = "uart_c_tx",
> + "uart_c_rx";
> + function = "uart_c";
> + bias-disable;
> + };
> + };
> +
> + uart_c_cts_rts_pins: uart_c_cts_rts {
> + mux {
> + groups = "uart_c_cts",
> + "uart_c_rts";
> + function = "uart_c";
> + bias-disable;
> + };
> + };
> + };
> };
>
> hiu: bus@3c000 {
> @@ -256,6 +311,33 @@
> compatible = "amlogic,meson-g12a-clk-measure";
> reg = <0x0 0x18000 0x0 0x10>;
> };
> +
> + uart_C: serial@22000 {
> + compatible = "amlogic,meson-gx-uart";
> + reg = <0x0 0x22000 0x0 0x18>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2
Regards
Martin
Hi Neil and Jerome,
On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <[email protected]> wrote:
>
> From: Jerome Brunet <[email protected]>
>
> Add the reset controller device of g12a SoC family
>
> Signed-off-by: Jerome Brunet <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index f8f055c49f9a..2a700bb45d04 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -245,6 +245,13 @@
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
>
> + reset: reset-controller@1004 {
> + compatible = "amlogic,meson-g12a-reset",
> + "amlogic,meson-axg-reset";
> + reg = <0x0 0x1004 0x0 0x9c>;
> + #reset-cells = <1>;
> + };
I tried to compare this with what is publicly available in
buildroot_openlinux_kernel_4.9_fbdev_20180706 - unfortunately this is
harder than I thought:
the buildroot kernel doesn't define the reset controller in mesong12a.dtsi
so I tried to follow the code in the HDMITX driver instead:
kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_txlx.c
uses P_RESET0_REGISTER and P_RESET2_REGISTER
these are defined in
kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/txlx_reg.h
using:
> #define RESET_CBUS_REG_IDX 5
> #define BASE_REG_OFFSET 24
> #define RESET_CBUS_REG_ADDR(reg) \
> ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
>
> #define RESET0_REGISTER 0x01
> #define P_RESET0_REGISTER RESET_CBUS_REG_ADDR(RESET0_REGISTER)
when I do the maths:
(5 << 24) + (0x01 << 2) = 0x5000004
The GX SoCs have the reset controller at cbus + 0x4404
however, the offset may have changed in G12A because the SAR ADC
offset also changed (just one example).
Do you have any hint how to verify the CBUS offset (0x1004) of the
reset controller?
Regards
Martin
On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <[email protected]> wrote:
>
> This patch adds the nodes for the USB Complex found in the Amlogic
> G12A SoC.
>
> It includes the :
> - 2 USB2 PHYs
> - 1 USB3 + PCIE Combo PHY
> - the USB Glue with it's DWC2 and DWC3 sub-nodes
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
[...]
> + g-tx-fifo-size = <128 128 16 16 16>;
I'm not sure about these values but it seems you have already successfully them.
buildroot_openlinux_kernel_4.9_fbdev_20180706 uses the following
values (which are identical to the ones on GXL/GXM, but using the
values below I couldn't get dwc2 to work on GXL when I tried it last):
dev_tx_fifo_size[0] = 128;
dev_tx_fifo_size[1] = 128;
dev_tx_fifo_size[2] = 128;
dev_tx_fifo_size[3] = 16;
dev_tx_fifo_size[4] = 16;
Thus I'm still giving my Reviewed-by based on the assumption that the
g-tx-fifo-size values you have are working (at least for you)
Regards
Martin
Hi,
Le 15/03/2019 22:07, Martin Blumenstingl a écrit :
> Hi Neil,
>
> On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <[email protected]> wrote:
>>
>> Add nodes and properties for the AO Clocks and Resets.
>>
>> Signed-off-by: Neil Armstrong <[email protected]>
>> Signed-off-by: Jerome Brunet <[email protected]>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index 191d31db9853..0eb5220da82c 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -122,6 +122,23 @@
>> #size-cells = <2>;
>> ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
>>
>> + rti: sys-ctrl@0 {
>> + compatible = "amlogic,meson-gx-ao-sysctrl",
>> + "simple-mfd", "syscon";
>> + reg = <0x0 0x0 0x0 0x1000>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x0 0x0 0x0 0x0 0x0 0x1000>;
> is this supposed to be 0x1000 (GX uses 0x100 here)?
> my understanding is that G12A has the AO CEC at aobus + 0x100, so
> using a size of 0x1000 would make it overlap
Hmm, Let me check
Neil
>
>
> Regards
> Martin
>
Le 15/03/2019 22:31, Martin Blumenstingl a écrit :
> Hi Neil and Jerome,
>
> On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <[email protected]> wrote:
>>
>> From: Jerome Brunet <[email protected]>
>>
>> Add the reset controller device of g12a SoC family
>>
>> Signed-off-by: Jerome Brunet <[email protected]>
>> Signed-off-by: Neil Armstrong <[email protected]>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index f8f055c49f9a..2a700bb45d04 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -245,6 +245,13 @@
>> #size-cells = <2>;
>> ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
>>
>> + reset: reset-controller@1004 {
>> + compatible = "amlogic,meson-g12a-reset",
>> + "amlogic,meson-axg-reset";
>> + reg = <0x0 0x1004 0x0 0x9c>;
>> + #reset-cells = <1>;
>> + };
> I tried to compare this with what is publicly available in
> buildroot_openlinux_kernel_4.9_fbdev_20180706 - unfortunately this is
> harder than I thought:
> the buildroot kernel doesn't define the reset controller in mesong12a.dtsi
>
> so I tried to follow the code in the HDMITX driver instead:
> kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_txlx.c
> uses P_RESET0_REGISTER and P_RESET2_REGISTER
> these are defined in
> kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/txlx_reg.h
> using:
>> #define RESET_CBUS_REG_IDX 5
>> #define BASE_REG_OFFSET 24
>> #define RESET_CBUS_REG_ADDR(reg) \
>> ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
>>
>> #define RESET0_REGISTER 0x01
>> #define P_RESET0_REGISTER RESET_CBUS_REG_ADDR(RESET0_REGISTER)
>
> when I do the maths:
> (5 << 24) + (0x01 << 2) = 0x5000004
>
> The GX SoCs have the reset controller at cbus + 0x4404
> however, the offset may have changed in G12A because the SAR ADC
> offset also changed (just one example).
>
> Do you have any hint how to verify the CBUS offset (0x1004) of the
> reset controller?
You can find base the address found in the G12A DT for the usb2 phy :
https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L379
Neil
>
>
> Regards
> Martin
>
Le 15/03/2019 22:24, Martin Blumenstingl a écrit :
> Hi Neil,
>
> On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <[email protected]> wrote:
>>
>> This patch adds the 2 UART nodes in the EE power domain with the corresponding
>> pinctrl nodes.
> there are 3 UART controllers in the EE power domain
Good catch !
>
>> Signed-off-by: Neil Armstrong <[email protected]>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++
>> 1 file changed, 82 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index 2a700bb45d04..50e2cd36e08b 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -113,6 +113,61 @@
>> #gpio-cells = <2>;
>> gpio-ranges = <&periphs_pinctrl 0 0 86>;
>> };
>> +
>> + uart_a_pins: uart_a {
> (this applies to all new nodes)
> we started using dashes for the node names for new pin definitions on
> the GX SoCs.
> I don't remember where it was discussed exactly but I think this was
> requested from Rob
Yes I remember, will fix
>
> since G12A is a new SoC we should do it "right" from the beginning
>
> [...]
>> + uart_ao_a_c_pins: uart_ao_a_c {
>> + mux {
>> + groups = "uart_ao_a_rx_c",
>> + "uart_ao_a_tx_c";
>> + function = "uart_ao_a_c";
>> + bias-disable;
>> + };
>> + };
> I'm fine with this part if you mention it in the subject and/or the description
> uart_ao_a_c routes two pins from bank C (from the EE domain) to the
> uart_AO controller (from the AO domain)
Not sure DT is the right place for that, I think I'll remove this until
we have it actually used somewhere.
>
>> + uart_b_pins: uart_b {
>> + mux {
>> + groups = "uart_b_tx",
>> + "uart_b_rx";
>> + function = "uart_b";
>> + bias-disable;
>> + };
>> + };
>> +
>> + uart_c_pins: uart_c {
>> + mux {
>> + groups = "uart_c_tx",
>> + "uart_c_rx";
>> + function = "uart_c";
>> + bias-disable;
>> + };
>> + };
>> +
>> + uart_c_cts_rts_pins: uart_c_cts_rts {
>> + mux {
>> + groups = "uart_c_cts",
>> + "uart_c_rts";
>> + function = "uart_c";
>> + bias-disable;
>> + };
>> + };
>> + };
>> };
>>
>> hiu: bus@3c000 {
>> @@ -256,6 +311,33 @@
>> compatible = "amlogic,meson-g12a-clk-measure";
>> reg = <0x0 0x18000 0x0 0x10>;
>> };
>> +
>> + uart_C: serial@22000 {
>> + compatible = "amlogic,meson-gx-uart";
>> + reg = <0x0 0x22000 0x0 0x18>;
>> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
> does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2
It seems so :
https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020
Neil
>
>
> Regards
> Martin
>
Le 15/03/2019 22:40, Martin Blumenstingl a écrit :
> On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <[email protected]> wrote:
>>
>> This patch adds the nodes for the USB Complex found in the Amlogic
>> G12A SoC.
>>
>> It includes the :
>> - 2 USB2 PHYs
>> - 1 USB3 + PCIE Combo PHY
>> - the USB Glue with it's DWC2 and DWC3 sub-nodes
>>
>> Signed-off-by: Neil Armstrong <[email protected]>
> Reviewed-by: Martin Blumenstingl <[email protected]>
>
> [...]
>> + g-tx-fifo-size = <128 128 16 16 16>;
> I'm not sure about these values but it seems you have already successfully them.
> buildroot_openlinux_kernel_4.9_fbdev_20180706 uses the following
> values (which are identical to the ones on GXL/GXM, but using the
> values below I couldn't get dwc2 to work on GXL when I tried it last):
> dev_tx_fifo_size[0] = 128;
> dev_tx_fifo_size[1] = 128;
> dev_tx_fifo_size[2] = 128;
> dev_tx_fifo_size[3] = 16;
> dev_tx_fifo_size[4] = 16;
Same for me, only <128 128 16 16 16> worked for me.
>
> Thus I'm still giving my Reviewed-by based on the assumption that the
> g-tx-fifo-size values you have are working (at least for you)
Indeed, I tried the amlogic values without success, I suspect the driver they use
(the Sysnopsys out-of-tree driver) uses these values differently.
Thanks,
Neil
>
>
> Regards
> Martin
>
Hi Neil,
On Sat, Mar 16, 2019 at 3:32 PM Neil Armstrong <[email protected]> wrote:
[...]
> > Do you have any hint how to verify the CBUS offset (0x1004) of the
> > reset controller?
>
> You can find base the address found in the G12A DT for the usb2 phy :
> https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L379
perfect, thank you!
feel free to add my:
Reviewed-by: Martin Blumenstingl <[email protected]>
Regards
Martin
Hi Neil,
On Sat, Mar 16, 2019 at 3:35 PM Neil Armstrong <[email protected]> wrote:
[...]
> >> + uart_ao_a_c_pins: uart_ao_a_c {
> >> + mux {
> >> + groups = "uart_ao_a_rx_c",
> >> + "uart_ao_a_tx_c";
> >> + function = "uart_ao_a_c";
> >> + bias-disable;
> >> + };
> >> + };
> > I'm fine with this part if you mention it in the subject and/or the description
> > uart_ao_a_c routes two pins from bank C (from the EE domain) to the
> > uart_AO controller (from the AO domain)
>
> Not sure DT is the right place for that, I think I'll remove this until
> we have it actually used somewhere.
I'm fine with that as well
[...]
> >> +
> >> + uart_C: serial@22000 {
> >> + compatible = "amlogic,meson-gx-uart";
> >> + reg = <0x0 0x22000 0x0 0x18>;
> >> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
> >> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
> > does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2
>
> It seems so :
> https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020
it's weird but we can always fix it up later if needed. so let's keep
it for now to stay consistent with the vendor kernel until we know
better
Jianxin, can you please check with the hardware team whether the
uart_C gate clock (pclk) is CLKID_UART1 or CLKID_UART2 on G12A?
Regards
Martin
Le 16/03/2019 23:14, Martin Blumenstingl a écrit :
> Hi Neil,
>
> On Sat, Mar 16, 2019 at 3:35 PM Neil Armstrong <[email protected]> wrote:
> [...]
>>>> + uart_ao_a_c_pins: uart_ao_a_c {
>>>> + mux {
>>>> + groups = "uart_ao_a_rx_c",
>>>> + "uart_ao_a_tx_c";
>>>> + function = "uart_ao_a_c";
>>>> + bias-disable;
>>>> + };
>>>> + };
>>> I'm fine with this part if you mention it in the subject and/or the description
>>> uart_ao_a_c routes two pins from bank C (from the EE domain) to the
>>> uart_AO controller (from the AO domain)
>>
>> Not sure DT is the right place for that, I think I'll remove this until
>> we have it actually used somewhere.
> I'm fine with that as well
>
> [...]
>>>> +
>>>> + uart_C: serial@22000 {
>>>> + compatible = "amlogic,meson-gx-uart";
>>>> + reg = <0x0 0x22000 0x0 0x18>;
>>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
>>>> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
>>> does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2
>>
>> It seems so :
>> https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020
> it's weird but we can always fix it up later if needed. so let's keep
> it for now to stay consistent with the vendor kernel until we know
> better
>
> Jianxin, can you please check with the hardware team whether the
> uart_C gate clock (pclk) is CLKID_UART1 or CLKID_UART2 on G12A?
I think it's a typo, it should use CLKID_UART2
Neil
>
>
> Regards
> Martin
>