This series provides the support for turning on the arm-smmu's
clocks/power domains using runtime pm. This is done using
device links between smmu and client devices. The device link
framework keeps the two devices in correct order for power-cycling
across runtime PM or across system-wide PM.
With addition of a new device link flag DL_FLAG_AUTOREMOVE_SUPPLIER [8]
(available in linux-next of Rafael's linux-pm tree [9]), the device links
created between arm-smmu and its clients will be automatically purged
when arm-smmu driver unbinds from its device.
As not all implementations support clock/power gating, we are checking
for a valid 'smmu->dev's pm_domain' to conditionally enable the runtime
power management for such smmu implementations that can support it.
Otherwise, the clocks are turned to be always on in .probe until .remove.
With conditional runtime pm now, we avoid touching dev->power.lock
in fastpaths for smmu implementations that don't need to do anything
useful with pm_runtime.
This lets us to use the much-argued pm_runtime_get_sync/put_sync()
calls in map/unmap callbacks so that the clients do not have to
worry about handling any of the arm-smmu's power.
This series also adds support for Qcom's arm-smmu-v2 variant that
has different clocks and power requirements.
Previous version of this patch series is @ [2].
Tested this series on msm8996, and sdm845 after pulling in Rafael's linux-pm
linux-next[9] and Joerg's iommu next[10] branches.
[v13]
Addressing Rafael's comments:
* Added .suspend pm callback to disable the clocks in system wide suspend.
* Added corresponding clock enable in .resume pm callback.
* Explicitly enabling/disabling the clocks now when runtime PM is disabled.
* device_link_add() doesn't depend on pm_runtime_enabled() as we can
use device links across system suspend/resume too.
Addressing Robin's comments:
* Making device_link_add failures as non-fatal.
* Removed IOMMU_OF_DECLARE() declaration as we don't need this after Rob's
patch that removed all of these declarations.
[v12]
* Use new device link's flag introduced in [8] -
DL_FLAG_AUTOREMOVE_SUPPLIER. With this devices links are automatically
purged when arm-smmu driver unbinds.
* Using pm_runtime_force_suspend() instead of pm_runtime_disable() to
avoid following warning from arm_smmu_device_remove()
[295711.537507] ------------[ cut here ]------------
[295711.544226] Unpreparing enabled smmu_mdp_ahb_clk
[295711.549099] WARNING: CPU: 0 PID: 1 at ../drivers/clk/clk.c:697
clk_core_unprepare+0xd8/0xe0
...
[295711.674073] Call trace:
[295711.679454] clk_core_unprepare+0xd8/0xe0
[295711.682059] clk_unprepare+0x28/0x40
[295711.685964] clk_bulk_unprepare+0x28/0x40
[295711.689701] arm_smmu_device_remove+0x88/0xd8
[295711.693692] arm_smmu_device_shutdown+0xc/0x18
[295711.698120] platform_drv_shutdown+0x20/0x30
[v11]
* Some more cleanups for device link. We don't need an explicit
delete for device link from the driver, but just set the flag
DL_FLAG_AUTOREMOVE.
device_link_add() API description says -
"If the DL_FLAG_AUTOREMOVE is set, the link will be removed
automatically when the consumer device driver unbinds."
* Addressed the comments for 'smmu' in arm_smmu_map/unmap().
* Dropped the patch [7] that introduced device_link_del_dev() API.
[v10]
* Introduce device_link_del_dev() API to delete the link between
given consumer and supplier devices. The users of device link
do not need to store link pointer to delete the link later.
They can straightaway use this API by passing consumer and
supplier devices.
* Made corresponding changes to arm-smmu driver patch handling the
device links.
* Dropped the patch [6] that was adding device_link_find() API to
device core layer. device_link_del_dev() serves the purpose to
directly delete the link between two given devices.
[v9]
* Removed 'rpm_supported' flag, instead checking on pm_domain
to enable runtime pm.
* Creating device link only when the runtime pm is enabled, as we
don't need a device link besides managing the power dependency
between supplier and consumer devices.
* Introducing a patch to add device_link_find() API that finds
and existing link between supplier and consumer devices.
Also, made necessary change to device_link_add() to use this API.
* arm_smmu_remove_device() now uses this device_link_find() to find
the device link between smmu device and the master device, and then
delete this link.
* Dropped the destroy_domain_context() fix [5] as it was rather,
introducing catastrophically bad problem by destroying
'good dev's domain context.
* Added 'Reviwed-by' tag for Tomasz's review.
[v8]
* Major change -
- Added a flag 'rpm_supported' which each platform that supports
runtime pm, can enable, and we enable runtime_pm over arm-smmu
only when this flag is set.
- Adding the conditional pm_runtime_get/put() calls to .map, .unmap
and .attach_dev ops.
- Dropped the patch [3] that exported pm_runtim_get/put_suupliers(),
and also dropped the user driver patch [4] for these APIs.
* Clock code further cleanup
- doing only clk_bulk_enable() and clk_bulk_disable() in runtime pm
callbacks. We shouldn't be taking a slow path (clk_prepare/unprepare())
from these runtime pm callbacks. Thereby, moved clk_bulk_prepare() to
arm_smmu_device_probe(), and clk_bulk_unprepare() to
arm_smmu_device_remove().
- clk data filling to a common method arm_smmu_fill_clk_data() that
fills the clock ids and number of clocks.
* Addressed other nits and comments
- device_link_add() error path fixed.
- Fix for checking negative error value from pm_runtime_get_sync().
- Documentation redo.
* Added another patch fixing the error path in arm_smmu_attach_dev()
to destroy allocated domain context.
[v7]
* Addressed review comments given by Robin Murphy -
- Added device_link_del() in .remove_device path.
- Error path cleanup in arm_smmu_add_device().
- Added pm_runtime_get/put_sync() in .remove path, and replaced
pm_runtime_force_suspend() with pm_runtime_disable().
- clk_names cleanup in arm_smmu_init_clks()
* Added 'Reviewed-by' given by Rob H.
** Change logs for previous versions is available in last series [4].
[1] https://patchwork.kernel.org/patch/10204925/
[2] https://lkml.org/lkml/2018/7/8/124
[3] https://patchwork.kernel.org/patch/10204945/
[4] https://patchwork.kernel.org/patch/10204925/
[5] https://patchwork.kernel.org/patch/10254105/
[6] https://patchwork.kernel.org/patch/10277975/
[7] https://patchwork.kernel.org/patch/10281613/
[8] https://patchwork.kernel.org/patch/10491481/
[9] https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/log/?h=linux-next
[10] https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git/log/?h=next
Sricharan R (3):
iommu/arm-smmu: Add pm_runtime/sleep ops
iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device
iommu/arm-smmu: Add the device_link between masters and smmu
Vivek Gautam (1):
iommu/arm-smmu: Add support for qcom,smmu-v2 variant
.../devicetree/bindings/iommu/arm,smmu.txt | 42 +++++
drivers/iommu/arm-smmu.c | 192 +++++++++++++++++++--
2 files changed, 224 insertions(+), 10 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sricharan R <[email protected]>
The smmu needs to be functional only when the respective
master's using it are active. The device_link feature
helps to track such functional dependencies, so that the
iommu gets powered when the master device enables itself
using pm_runtime. So by adapting the smmu driver for
runtime pm, above said dependency can be addressed.
This patch adds the pm runtime/sleep callbacks to the
driver and also the functions to parse the smmu clocks
from DT and enable them in resume/suspend.
Also, while we enable the runtime pm add a pm sleep suspend
callback that pushes devices to low power state by turning
the clocks off in a system sleep.
Also add corresponding clock enable path in resume callback.
Signed-off-by: Sricharan R <[email protected]>
Signed-off-by: Archit Taneja <[email protected]>
[vivek: rework for clock and pm ops]
Signed-off-by: Vivek Gautam <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
---
Changes since v12:
- Added pm sleep .suspend callback. This disables the clocks.
- Added corresponding change to enable clocks in .resume
pm sleep callback.
drivers/iommu/arm-smmu.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index c73cfce1ccc0..9138a6fffe04 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -48,6 +48,7 @@
#include <linux/of_iommu.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
@@ -205,6 +206,8 @@ struct arm_smmu_device {
u32 num_global_irqs;
u32 num_context_irqs;
unsigned int *irqs;
+ struct clk_bulk_data *clks;
+ int num_clks;
u32 cavium_id_base; /* Specific to Cavium */
@@ -1897,10 +1900,12 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
struct arm_smmu_match_data {
enum arm_smmu_arch_version version;
enum arm_smmu_implementation model;
+ const char * const *clks;
+ int num_clks;
};
#define ARM_SMMU_MATCH_DATA(name, ver, imp) \
-static struct arm_smmu_match_data name = { .version = ver, .model = imp }
+static const struct arm_smmu_match_data name = { .version = ver, .model = imp }
ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
@@ -1919,6 +1924,23 @@ static const struct of_device_id arm_smmu_of_match[] = {
};
MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
+static void arm_smmu_fill_clk_data(struct arm_smmu_device *smmu,
+ const char * const *clks)
+{
+ int i;
+
+ if (smmu->num_clks < 1)
+ return;
+
+ smmu->clks = devm_kcalloc(smmu->dev, smmu->num_clks,
+ sizeof(*smmu->clks), GFP_KERNEL);
+ if (!smmu->clks)
+ return;
+
+ for (i = 0; i < smmu->num_clks; i++)
+ smmu->clks[i].id = clks[i];
+}
+
#ifdef CONFIG_ACPI
static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
{
@@ -2001,6 +2023,9 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
data = of_device_get_match_data(dev);
smmu->version = data->version;
smmu->model = data->model;
+ smmu->num_clks = data->num_clks;
+
+ arm_smmu_fill_clk_data(smmu, data->clks);
parse_driver_options(smmu);
@@ -2099,6 +2124,14 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
smmu->irqs[i] = irq;
}
+ err = devm_clk_bulk_get(smmu->dev, smmu->num_clks, smmu->clks);
+ if (err)
+ return err;
+
+ err = clk_bulk_prepare(smmu->num_clks, smmu->clks);
+ if (err)
+ return err;
+
err = arm_smmu_device_cfg_probe(smmu);
if (err)
return err;
@@ -2181,6 +2214,9 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
/* Turn the thing off */
writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
+
+ clk_bulk_unprepare(smmu->num_clks, smmu->clks);
+
return 0;
}
@@ -2189,15 +2225,50 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev)
arm_smmu_device_remove(pdev);
}
+static int __maybe_unused arm_smmu_runtime_resume(struct device *dev)
+{
+ struct arm_smmu_device *smmu = dev_get_drvdata(dev);
+
+ return clk_bulk_enable(smmu->num_clks, smmu->clks);
+}
+
+static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev)
+{
+ struct arm_smmu_device *smmu = dev_get_drvdata(dev);
+
+ clk_bulk_disable(smmu->num_clks, smmu->clks);
+
+ return 0;
+}
+
static int __maybe_unused arm_smmu_pm_resume(struct device *dev)
{
struct arm_smmu_device *smmu = dev_get_drvdata(dev);
+ int ret;
+
+ if (!pm_runtime_suspended(dev)) {
+ ret = arm_smmu_runtime_resume(dev);
+ if (ret)
+ return ret;
+ }
arm_smmu_device_reset(smmu);
return 0;
}
-static SIMPLE_DEV_PM_OPS(arm_smmu_pm_ops, NULL, arm_smmu_pm_resume);
+static int __maybe_unused arm_smmu_pm_suspend(struct device *dev)
+{
+ if (!pm_runtime_suspended(dev))
+ return arm_smmu_runtime_suspend(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops arm_smmu_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(arm_smmu_pm_suspend, arm_smmu_pm_resume)
+ SET_RUNTIME_PM_OPS(arm_smmu_runtime_suspend,
+ arm_smmu_runtime_resume, NULL)
+};
static struct platform_driver arm_smmu_driver = {
.driver = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sricharan R <[email protected]>
The smmu device probe/remove and add/remove master device callbacks
gets called when the smmu is not linked to its master, that is without
the context of the master device. So calling runtime apis in those places
separately.
Signed-off-by: Sricharan R <[email protected]>
[vivek: Cleanup pm runtime calls]
Signed-off-by: Vivek Gautam <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
---
Changes since v12:
- Explicitly enabling and disabling clocks in probe and remove routines
if runtime PM is disabled,
drivers/iommu/arm-smmu.c | 101 +++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 93 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 9138a6fffe04..15b20941441a 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -268,6 +268,20 @@ static struct arm_smmu_option_prop arm_smmu_options[] = {
{ 0, NULL},
};
+static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu)
+{
+ if (pm_runtime_enabled(smmu->dev))
+ return pm_runtime_get_sync(smmu->dev);
+
+ return 0;
+}
+
+static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu)
+{
+ if (pm_runtime_enabled(smmu->dev))
+ pm_runtime_put(smmu->dev);
+}
+
static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
{
return container_of(dom, struct arm_smmu_domain, domain);
@@ -913,11 +927,15 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
- int irq;
+ int ret, irq;
if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY)
return;
+ ret = arm_smmu_rpm_get(smmu);
+ if (ret < 0)
+ return;
+
/*
* Disable the context bank and free the page tables before freeing
* it.
@@ -932,6 +950,8 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
free_io_pgtable_ops(smmu_domain->pgtbl_ops);
__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
+
+ arm_smmu_rpm_put(smmu);
}
static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
@@ -1213,10 +1233,15 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
return -ENODEV;
smmu = fwspec_smmu(fwspec);
+
+ ret = arm_smmu_rpm_get(smmu);
+ if (ret < 0)
+ return ret;
+
/* Ensure that the domain is finalised */
ret = arm_smmu_init_domain_context(domain, smmu);
if (ret < 0)
- return ret;
+ goto rpm_put;
/*
* Sanity check the domain. We don't support domains across
@@ -1226,33 +1251,50 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
dev_err(dev,
"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
- return -EINVAL;
+ ret = -EINVAL;
+ goto rpm_put;
}
/* Looks ok, so add the device to the domain */
- return arm_smmu_domain_add_master(smmu_domain, fwspec);
+ ret = arm_smmu_domain_add_master(smmu_domain, fwspec);
+
+rpm_put:
+ arm_smmu_rpm_put(smmu);
+ return ret;
}
static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot)
{
struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops;
+ struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu;
+ int ret;
if (!ops)
return -ENODEV;
- return ops->map(ops, iova, paddr, size, prot);
+ arm_smmu_rpm_get(smmu);
+ ret = ops->map(ops, iova, paddr, size, prot);
+ arm_smmu_rpm_put(smmu);
+
+ return ret;
}
static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
size_t size)
{
struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops;
+ struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu;
+ size_t ret;
if (!ops)
return 0;
- return ops->unmap(ops, iova, size);
+ arm_smmu_rpm_get(smmu);
+ ret = ops->unmap(ops, iova, size);
+ arm_smmu_rpm_put(smmu);
+
+ return ret;
}
static void arm_smmu_iotlb_sync(struct iommu_domain *domain)
@@ -1407,7 +1449,13 @@ static int arm_smmu_add_device(struct device *dev)
while (i--)
cfg->smendx[i] = INVALID_SMENDX;
+ ret = arm_smmu_rpm_get(smmu);
+ if (ret < 0)
+ goto out_cfg_free;
+
ret = arm_smmu_master_alloc_smes(dev);
+ arm_smmu_rpm_put(smmu);
+
if (ret)
goto out_cfg_free;
@@ -1427,7 +1475,7 @@ static void arm_smmu_remove_device(struct device *dev)
struct iommu_fwspec *fwspec = dev->iommu_fwspec;
struct arm_smmu_master_cfg *cfg;
struct arm_smmu_device *smmu;
-
+ int ret;
if (!fwspec || fwspec->ops != &arm_smmu_ops)
return;
@@ -1435,8 +1483,15 @@ static void arm_smmu_remove_device(struct device *dev)
cfg = fwspec->iommu_priv;
smmu = cfg->smmu;
+ ret = arm_smmu_rpm_get(smmu);
+ if (ret < 0)
+ return;
+
iommu_device_unlink(&smmu->iommu, dev);
arm_smmu_master_free_smes(fwspec);
+
+ arm_smmu_rpm_put(smmu);
+
iommu_group_remove_device(dev);
kfree(fwspec->iommu_priv);
iommu_fwspec_free(dev);
@@ -2124,6 +2179,8 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
smmu->irqs[i] = irq;
}
+ platform_set_drvdata(pdev, smmu);
+
err = devm_clk_bulk_get(smmu->dev, smmu->num_clks, smmu->clks);
if (err)
return err;
@@ -2132,6 +2189,26 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
if (err)
return err;
+ /*
+ * We want to avoid touching dev->power.lock in fastpaths unless
+ * it's really going to do something useful - pm_runtime_enabled()
+ * can serve as an ideal proxy for that decision. So, conditionally
+ * enable pm_runtime.
+ */
+ if (dev->pm_domain)
+ pm_runtime_enable(dev);
+
+ err = arm_smmu_rpm_get(smmu);
+ if (err < 0)
+ return err;
+
+ /* Enable clocks explicitly if runtime PM is disabled */
+ if (!pm_runtime_enabled(dev)) {
+ err = clk_bulk_enable(smmu->num_clks, smmu->clks);
+ if (err)
+ return err;
+ }
+
err = arm_smmu_device_cfg_probe(smmu);
if (err)
return err;
@@ -2173,10 +2250,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
return err;
}
- platform_set_drvdata(pdev, smmu);
arm_smmu_device_reset(smmu);
arm_smmu_test_smr_masks(smmu);
+ arm_smmu_rpm_put(smmu);
+
/*
* For ACPI and generic DT bindings, an SMMU will be probed before
* any device which might need it, so we want the bus ops in place
@@ -2212,8 +2290,15 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
dev_err(&pdev->dev, "removing device with active domains!\n");
+ arm_smmu_rpm_get(smmu);
/* Turn the thing off */
writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
+ arm_smmu_rpm_put(smmu);
+
+ if (pm_runtime_enabled(smmu->dev))
+ pm_runtime_force_suspend(smmu->dev);
+ else
+ clk_bulk_disable(smmu->num_clks, smmu->clks);
clk_bulk_unprepare(smmu->num_clks, smmu->clks);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sricharan R <[email protected]>
Finally add the device link between the master device and
smmu, so that the smmu gets runtime enabled/disabled only when the
master needs it. This is done from add_device callback which gets
called once when the master is added to the smmu.
Signed-off-by: Sricharan R <[email protected]>
Signed-off-by: Vivek Gautam <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
---
Changes since v12:
- device_link_add() doesn't depend on pm_runtime_enabled() now.
- Treat failure in device link addition as non-fatal.
drivers/iommu/arm-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 15b20941441a..25ff3bdbf7a3 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1461,6 +1461,9 @@ static int arm_smmu_add_device(struct device *dev)
iommu_device_link(&smmu->iommu, dev);
+ device_link_add(dev, smmu->dev,
+ DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_SUPPLIER);
+
return 0;
out_cfg_free:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
qcom,smmu-v2 is an arm,smmu-v2 implementation with specific
clock and power requirements. This smmu core is used with
multiple masters on msm8996, viz. mdss, video, etc.
Add bindings for the same.
Signed-off-by: Vivek Gautam <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
---
Change since v12:
- Removed IOMMU_OF_DECLARE() definition after Rob H's patch that is merged
in driver-core-next.
.../devicetree/bindings/iommu/arm,smmu.txt | 42 ++++++++++++++++++++++
drivers/iommu/arm-smmu.c | 13 +++++++
2 files changed, 55 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 8a6ffce12af5..7c71a6ed465a 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -17,10 +17,19 @@ conditions.
"arm,mmu-401"
"arm,mmu-500"
"cavium,smmu-v2"
+ "qcom,<soc>-smmu-v2", "qcom,smmu-v2"
depending on the particular implementation and/or the
version of the architecture implemented.
+ A number of Qcom SoCs use qcom,smmu-v2 version of the IP.
+ "qcom,<soc>-smmu-v2" represents a soc specific compatible
+ string that should be present along with the "qcom,smmu-v2"
+ to facilitate SoC specific clocks/power connections and to
+ address specific bug fixes.
+ An example string would be -
+ "qcom,msm8996-smmu-v2", "qcom,smmu-v2".
+
- reg : Base address and size of the SMMU.
- #global-interrupts : The number of global interrupts exposed by the
@@ -71,6 +80,22 @@ conditions.
or using stream matching with #iommu-cells = <2>, and
may be ignored if present in such cases.
+- clock-names: List of the names of clocks input to the device. The
+ required list depends on particular implementation and
+ is as follows:
+ - for "qcom,smmu-v2":
+ - "bus": clock required for downstream bus access and
+ for the smmu ptw,
+ - "iface": clock required to access smmu's registers
+ through the TCU's programming interface.
+ - unspecified for other implementations.
+
+- clocks: Specifiers for all clocks listed in the clock-names property,
+ as per generic clock bindings.
+
+- power-domains: Specifiers for power domains required to be powered on for
+ the SMMU to operate, as per generic power domain bindings.
+
** Deprecated properties:
- mmu-masters (deprecated in favour of the generic "iommus" binding) :
@@ -137,3 +162,20 @@ conditions.
iommu-map = <0 &smmu3 0 0x400>;
...
};
+
+ /* Qcom's arm,smmu-v2 implementation */
+ smmu4: iommu {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0xd00000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&mmcc MDSS_GDSC>;
+
+ clocks = <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc SMMU_MDP_AHB_CLK>;
+ clock-names = "bus", "iface";
+ };
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 25ff3bdbf7a3..7c69736a30f8 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -119,6 +119,7 @@ enum arm_smmu_implementation {
GENERIC_SMMU,
ARM_MMU500,
CAVIUM_SMMUV2,
+ QCOM_SMMUV2,
};
struct arm_smmu_s2cr {
@@ -1971,6 +1972,17 @@ ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
+static const char * const qcom_smmuv2_clks[] = {
+ "bus", "iface",
+};
+
+static const struct arm_smmu_match_data qcom_smmuv2 = {
+ .version = ARM_SMMU_V2,
+ .model = QCOM_SMMUV2,
+ .clks = qcom_smmuv2_clks,
+ .num_clks = ARRAY_SIZE(qcom_smmuv2_clks),
+};
+
static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
{ .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
@@ -1978,6 +1990,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
+ { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
{ },
};
MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On Thu, Jul 19, 2018 at 3:45 PM, Vivek Gautam
<[email protected]> wrote:
> This series provides the support for turning on the arm-smmu's
> clocks/power domains using runtime pm. This is done using
> device links between smmu and client devices. The device link
> framework keeps the two devices in correct order for power-cycling
> across runtime PM or across system-wide PM.
>
> With addition of a new device link flag DL_FLAG_AUTOREMOVE_SUPPLIER [8]
> (available in linux-next of Rafael's linux-pm tree [9]), the device links
> created between arm-smmu and its clients will be automatically purged
> when arm-smmu driver unbinds from its device.
>
> As not all implementations support clock/power gating, we are checking
> for a valid 'smmu->dev's pm_domain' to conditionally enable the runtime
> power management for such smmu implementations that can support it.
> Otherwise, the clocks are turned to be always on in .probe until .remove.
> With conditional runtime pm now, we avoid touching dev->power.lock
> in fastpaths for smmu implementations that don't need to do anything
> useful with pm_runtime.
> This lets us to use the much-argued pm_runtime_get_sync/put_sync()
> calls in map/unmap callbacks so that the clients do not have to
> worry about handling any of the arm-smmu's power.
>
> This series also adds support for Qcom's arm-smmu-v2 variant that
> has different clocks and power requirements.
>
> Previous version of this patch series is @ [2].
>
> Tested this series on msm8996, and sdm845 after pulling in Rafael's linux-pm
> linux-next[9] and Joerg's iommu next[10] branches.
Hi Rafael,
If the changes look good to you now, can you please consider giving your Ack.
Thanks.
Hi Robin, Will,
If the series looks good to you, and if there's a chance, can you
please consider
picking this series for 4.19. Thanks.
Best regards
Vivek
>
> [v13]
> Addressing Rafael's comments:
> * Added .suspend pm callback to disable the clocks in system wide suspend.
> * Added corresponding clock enable in .resume pm callback.
> * Explicitly enabling/disabling the clocks now when runtime PM is disabled.
> * device_link_add() doesn't depend on pm_runtime_enabled() as we can
> use device links across system suspend/resume too.
>
> Addressing Robin's comments:
> * Making device_link_add failures as non-fatal.
>
> * Removed IOMMU_OF_DECLARE() declaration as we don't need this after Rob's
> patch that removed all of these declarations.
>
> [v12]
> * Use new device link's flag introduced in [8] -
> DL_FLAG_AUTOREMOVE_SUPPLIER. With this devices links are automatically
> purged when arm-smmu driver unbinds.
> * Using pm_runtime_force_suspend() instead of pm_runtime_disable() to
> avoid following warning from arm_smmu_device_remove()
>
> [295711.537507] ------------[ cut here ]------------
> [295711.544226] Unpreparing enabled smmu_mdp_ahb_clk
> [295711.549099] WARNING: CPU: 0 PID: 1 at ../drivers/clk/clk.c:697
> clk_core_unprepare+0xd8/0xe0
> ...
> [295711.674073] Call trace:
> [295711.679454] clk_core_unprepare+0xd8/0xe0
> [295711.682059] clk_unprepare+0x28/0x40
> [295711.685964] clk_bulk_unprepare+0x28/0x40
> [295711.689701] arm_smmu_device_remove+0x88/0xd8
> [295711.693692] arm_smmu_device_shutdown+0xc/0x18
> [295711.698120] platform_drv_shutdown+0x20/0x30
>
> [v11]
> * Some more cleanups for device link. We don't need an explicit
> delete for device link from the driver, but just set the flag
> DL_FLAG_AUTOREMOVE.
> device_link_add() API description says -
> "If the DL_FLAG_AUTOREMOVE is set, the link will be removed
> automatically when the consumer device driver unbinds."
> * Addressed the comments for 'smmu' in arm_smmu_map/unmap().
> * Dropped the patch [7] that introduced device_link_del_dev() API.
>
> [v10]
> * Introduce device_link_del_dev() API to delete the link between
> given consumer and supplier devices. The users of device link
> do not need to store link pointer to delete the link later.
> They can straightaway use this API by passing consumer and
> supplier devices.
> * Made corresponding changes to arm-smmu driver patch handling the
> device links.
> * Dropped the patch [6] that was adding device_link_find() API to
> device core layer. device_link_del_dev() serves the purpose to
> directly delete the link between two given devices.
>
> [v9]
> * Removed 'rpm_supported' flag, instead checking on pm_domain
> to enable runtime pm.
> * Creating device link only when the runtime pm is enabled, as we
> don't need a device link besides managing the power dependency
> between supplier and consumer devices.
> * Introducing a patch to add device_link_find() API that finds
> and existing link between supplier and consumer devices.
> Also, made necessary change to device_link_add() to use this API.
> * arm_smmu_remove_device() now uses this device_link_find() to find
> the device link between smmu device and the master device, and then
> delete this link.
> * Dropped the destroy_domain_context() fix [5] as it was rather,
> introducing catastrophically bad problem by destroying
> 'good dev's domain context.
> * Added 'Reviwed-by' tag for Tomasz's review.
>
> [v8]
> * Major change -
> - Added a flag 'rpm_supported' which each platform that supports
> runtime pm, can enable, and we enable runtime_pm over arm-smmu
> only when this flag is set.
> - Adding the conditional pm_runtime_get/put() calls to .map, .unmap
> and .attach_dev ops.
> - Dropped the patch [3] that exported pm_runtim_get/put_suupliers(),
> and also dropped the user driver patch [4] for these APIs.
>
> * Clock code further cleanup
> - doing only clk_bulk_enable() and clk_bulk_disable() in runtime pm
> callbacks. We shouldn't be taking a slow path (clk_prepare/unprepare())
> from these runtime pm callbacks. Thereby, moved clk_bulk_prepare() to
> arm_smmu_device_probe(), and clk_bulk_unprepare() to
> arm_smmu_device_remove().
> - clk data filling to a common method arm_smmu_fill_clk_data() that
> fills the clock ids and number of clocks.
>
> * Addressed other nits and comments
> - device_link_add() error path fixed.
> - Fix for checking negative error value from pm_runtime_get_sync().
> - Documentation redo.
>
> * Added another patch fixing the error path in arm_smmu_attach_dev()
> to destroy allocated domain context.
>
> [v7]
> * Addressed review comments given by Robin Murphy -
> - Added device_link_del() in .remove_device path.
> - Error path cleanup in arm_smmu_add_device().
> - Added pm_runtime_get/put_sync() in .remove path, and replaced
> pm_runtime_force_suspend() with pm_runtime_disable().
> - clk_names cleanup in arm_smmu_init_clks()
> * Added 'Reviewed-by' given by Rob H.
>
> ** Change logs for previous versions is available in last series [4].
>
>
> [1] https://patchwork.kernel.org/patch/10204925/
> [2] https://lkml.org/lkml/2018/7/8/124
> [3] https://patchwork.kernel.org/patch/10204945/
> [4] https://patchwork.kernel.org/patch/10204925/
> [5] https://patchwork.kernel.org/patch/10254105/
> [6] https://patchwork.kernel.org/patch/10277975/
> [7] https://patchwork.kernel.org/patch/10281613/
> [8] https://patchwork.kernel.org/patch/10491481/
> [9] https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/log/?h=linux-next
> [10] https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git/log/?h=next
>
> Sricharan R (3):
> iommu/arm-smmu: Add pm_runtime/sleep ops
> iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device
> iommu/arm-smmu: Add the device_link between masters and smmu
>
> Vivek Gautam (1):
> iommu/arm-smmu: Add support for qcom,smmu-v2 variant
>
> .../devicetree/bindings/iommu/arm,smmu.txt | 42 +++++
> drivers/iommu/arm-smmu.c | 192 +++++++++++++++++++--
> 2 files changed, 224 insertions(+), 10 deletions(-)
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
> _______________________________________________
> iommu mailing list
> [email protected]
> https://lists.linuxfoundation.org/mailman/listinfo/iommu
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 19/07/18 11:15, Vivek Gautam wrote:
> From: Sricharan R <[email protected]>
>
> The smmu needs to be functional only when the respective
> master's using it are active. The device_link feature
> helps to track such functional dependencies, so that the
> iommu gets powered when the master device enables itself
> using pm_runtime. So by adapting the smmu driver for
> runtime pm, above said dependency can be addressed.
>
> This patch adds the pm runtime/sleep callbacks to the
> driver and also the functions to parse the smmu clocks
> from DT and enable them in resume/suspend.
>
> Also, while we enable the runtime pm add a pm sleep suspend
> callback that pushes devices to low power state by turning
> the clocks off in a system sleep.
> Also add corresponding clock enable path in resume callback.
>
> Signed-off-by: Sricharan R <[email protected]>
> Signed-off-by: Archit Taneja <[email protected]>
> [vivek: rework for clock and pm ops]
> Signed-off-by: Vivek Gautam <[email protected]>
> Reviewed-by: Tomasz Figa <[email protected]>
> ---
>
> Changes since v12:
> - Added pm sleep .suspend callback. This disables the clocks.
> - Added corresponding change to enable clocks in .resume
> pm sleep callback.
>
> drivers/iommu/arm-smmu.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 73 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index c73cfce1ccc0..9138a6fffe04 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -48,6 +48,7 @@
> #include <linux/of_iommu.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/slab.h>
> #include <linux/spinlock.h>
>
> @@ -205,6 +206,8 @@ struct arm_smmu_device {
> u32 num_global_irqs;
> u32 num_context_irqs;
> unsigned int *irqs;
> + struct clk_bulk_data *clks;
> + int num_clks;
>
> u32 cavium_id_base; /* Specific to Cavium */
>
> @@ -1897,10 +1900,12 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
> struct arm_smmu_match_data {
> enum arm_smmu_arch_version version;
> enum arm_smmu_implementation model;
> + const char * const *clks;
> + int num_clks;
> };
>
> #define ARM_SMMU_MATCH_DATA(name, ver, imp) \
> -static struct arm_smmu_match_data name = { .version = ver, .model = imp }
> +static const struct arm_smmu_match_data name = { .version = ver, .model = imp }
>
> ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
> ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
> @@ -1919,6 +1924,23 @@ static const struct of_device_id arm_smmu_of_match[] = {
> };
> MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>
> +static void arm_smmu_fill_clk_data(struct arm_smmu_device *smmu,
> + const char * const *clks)
> +{
> + int i;
> +
> + if (smmu->num_clks < 1)
> + return;
> +
> + smmu->clks = devm_kcalloc(smmu->dev, smmu->num_clks,
> + sizeof(*smmu->clks), GFP_KERNEL);
> + if (!smmu->clks)
> + return;
> +
> + for (i = 0; i < smmu->num_clks; i++)
> + smmu->clks[i].id = clks[i];
> +}
> +
> #ifdef CONFIG_ACPI
> static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
> {
> @@ -2001,6 +2023,9 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
> data = of_device_get_match_data(dev);
> smmu->version = data->version;
> smmu->model = data->model;
> + smmu->num_clks = data->num_clks;
> +
> + arm_smmu_fill_clk_data(smmu, data->clks);
>
> parse_driver_options(smmu);
>
> @@ -2099,6 +2124,14 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
> smmu->irqs[i] = irq;
> }
>
> + err = devm_clk_bulk_get(smmu->dev, smmu->num_clks, smmu->clks);
> + if (err)
> + return err;
> +
> + err = clk_bulk_prepare(smmu->num_clks, smmu->clks);
> + if (err)
> + return err;
> +
> err = arm_smmu_device_cfg_probe(smmu);
> if (err)
> return err;
> @@ -2181,6 +2214,9 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
>
> /* Turn the thing off */
> writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
> +
> + clk_bulk_unprepare(smmu->num_clks, smmu->clks);
> +
> return 0;
> }
>
> @@ -2189,15 +2225,50 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev)
> arm_smmu_device_remove(pdev);
> }
>
> +static int __maybe_unused arm_smmu_runtime_resume(struct device *dev)
> +{
> + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
> +
> + return clk_bulk_enable(smmu->num_clks, smmu->clks);
If there's a power domain being automatically switched by genpd then we
need a reset here because we may have lost state entirely. Since I
remembered the otherwise-useless GPU SMMU on Juno is in a separate power
domain, I gave it a poking via sysfs with some debug stuff to dump sCR0
in these callbacks, and the problem is clear:
...
[ 4.625551] arm-smmu 2b400000.iommu: genpd_runtime_suspend()
[ 4.631163] arm-smmu 2b400000.iommu: arm_smmu_runtime_suspend: 0x00201936
[ 4.637897] arm-smmu 2b400000.iommu: suspend latency exceeded, 6733980 ns
[ 21.566983] arm-smmu 2b400000.iommu: genpd_runtime_resume()
[ 21.584796] arm-smmu 2b400000.iommu: arm_smmu_runtime_resume: 0x00220101
[ 21.591452] arm-smmu 2b400000.iommu: resume latency exceeded, 6658020 ns
...
> +}
> +
> +static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev)
> +{
> + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
> +
> + clk_bulk_disable(smmu->num_clks, smmu->clks);
> +
> + return 0;
> +}
> +
> static int __maybe_unused arm_smmu_pm_resume(struct device *dev)
> {
> struct arm_smmu_device *smmu = dev_get_drvdata(dev);
> + int ret;
> +
> + if (!pm_runtime_suspended(dev)) {
> + ret = arm_smmu_runtime_resume(dev);
> + if (ret)
> + return ret;
> + }
>
> arm_smmu_device_reset(smmu);
This looks a bit off too - if we wake from sleep when the SMMU was also
runtime-suspended, it appears we might end up trying to restore the
register state without clocks enabled. Surely we need to always enable
clocks for the reset, then restore the previous suspended state?
Although given my previous point, it's probably not worth doing anything
at all here for that case.
Robin.
> return 0;
> }
>
> -static SIMPLE_DEV_PM_OPS(arm_smmu_pm_ops, NULL, arm_smmu_pm_resume);
> +static int __maybe_unused arm_smmu_pm_suspend(struct device *dev)
> +{
> + if (!pm_runtime_suspended(dev))
> + return arm_smmu_runtime_suspend(dev);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops arm_smmu_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(arm_smmu_pm_suspend, arm_smmu_pm_resume)
> + SET_RUNTIME_PM_OPS(arm_smmu_runtime_suspend,
> + arm_smmu_runtime_resume, NULL)
> +};
>
> static struct platform_driver arm_smmu_driver = {
> .driver = {
>
On Wed, Jul 25, 2018 at 12:21 AM Robin Murphy <[email protected]> wrote:
>
> On 19/07/18 11:15, Vivek Gautam wrote:
> > From: Sricharan R <[email protected]>
> >
> > The smmu needs to be functional only when the respective
> > master's using it are active. The device_link feature
> > helps to track such functional dependencies, so that the
> > iommu gets powered when the master device enables itself
> > using pm_runtime. So by adapting the smmu driver for
> > runtime pm, above said dependency can be addressed.
> >
> > This patch adds the pm runtime/sleep callbacks to the
> > driver and also the functions to parse the smmu clocks
> > from DT and enable them in resume/suspend.
> >
> > Also, while we enable the runtime pm add a pm sleep suspend
> > callback that pushes devices to low power state by turning
> > the clocks off in a system sleep.
> > Also add corresponding clock enable path in resume callback.
> >
> > Signed-off-by: Sricharan R <[email protected]>
> > Signed-off-by: Archit Taneja <[email protected]>
> > [vivek: rework for clock and pm ops]
> > Signed-off-by: Vivek Gautam <[email protected]>
> > Reviewed-by: Tomasz Figa <[email protected]>
> > ---
> >
> > Changes since v12:
> > - Added pm sleep .suspend callback. This disables the clocks.
> > - Added corresponding change to enable clocks in .resume
> > pm sleep callback.
> >
> > drivers/iommu/arm-smmu.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 73 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> > index c73cfce1ccc0..9138a6fffe04 100644
> > --- a/drivers/iommu/arm-smmu.c
> > +++ b/drivers/iommu/arm-smmu.c
> > @@ -48,6 +48,7 @@
> > #include <linux/of_iommu.h>
> > #include <linux/pci.h>
> > #include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > #include <linux/slab.h>
> > #include <linux/spinlock.h>
> >
> > @@ -205,6 +206,8 @@ struct arm_smmu_device {
> > u32 num_global_irqs;
> > u32 num_context_irqs;
> > unsigned int *irqs;
> > + struct clk_bulk_data *clks;
> > + int num_clks;
> >
> > u32 cavium_id_base; /* Specific to Cavium */
> >
> > @@ -1897,10 +1900,12 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
> > struct arm_smmu_match_data {
> > enum arm_smmu_arch_version version;
> > enum arm_smmu_implementation model;
> > + const char * const *clks;
> > + int num_clks;
> > };
> >
> > #define ARM_SMMU_MATCH_DATA(name, ver, imp) \
> > -static struct arm_smmu_match_data name = { .version = ver, .model = imp }
> > +static const struct arm_smmu_match_data name = { .version = ver, .model = imp }
> >
> > ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
> > ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
> > @@ -1919,6 +1924,23 @@ static const struct of_device_id arm_smmu_of_match[] = {
> > };
> > MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
> >
> > +static void arm_smmu_fill_clk_data(struct arm_smmu_device *smmu,
> > + const char * const *clks)
> > +{
> > + int i;
> > +
> > + if (smmu->num_clks < 1)
> > + return;
> > +
> > + smmu->clks = devm_kcalloc(smmu->dev, smmu->num_clks,
> > + sizeof(*smmu->clks), GFP_KERNEL);
> > + if (!smmu->clks)
> > + return;
> > +
> > + for (i = 0; i < smmu->num_clks; i++)
> > + smmu->clks[i].id = clks[i];
> > +}
> > +
> > #ifdef CONFIG_ACPI
> > static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
> > {
> > @@ -2001,6 +2023,9 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
> > data = of_device_get_match_data(dev);
> > smmu->version = data->version;
> > smmu->model = data->model;
> > + smmu->num_clks = data->num_clks;
> > +
> > + arm_smmu_fill_clk_data(smmu, data->clks);
> >
> > parse_driver_options(smmu);
> >
> > @@ -2099,6 +2124,14 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
> > smmu->irqs[i] = irq;
> > }
> >
> > + err = devm_clk_bulk_get(smmu->dev, smmu->num_clks, smmu->clks);
> > + if (err)
> > + return err;
> > +
> > + err = clk_bulk_prepare(smmu->num_clks, smmu->clks);
> > + if (err)
> > + return err;
> > +
> > err = arm_smmu_device_cfg_probe(smmu);
> > if (err)
> > return err;
> > @@ -2181,6 +2214,9 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
> >
> > /* Turn the thing off */
> > writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
> > +
> > + clk_bulk_unprepare(smmu->num_clks, smmu->clks);
> > +
> > return 0;
> > }
> >
> > @@ -2189,15 +2225,50 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev)
> > arm_smmu_device_remove(pdev);
> > }
> >
> > +static int __maybe_unused arm_smmu_runtime_resume(struct device *dev)
> > +{
> > + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
> > +
> > + return clk_bulk_enable(smmu->num_clks, smmu->clks);
>
> If there's a power domain being automatically switched by genpd then we
> need a reset here because we may have lost state entirely. Since I
> remembered the otherwise-useless GPU SMMU on Juno is in a separate power
> domain, I gave it a poking via sysfs with some debug stuff to dump sCR0
> in these callbacks, and the problem is clear:
>
> ...
> [ 4.625551] arm-smmu 2b400000.iommu: genpd_runtime_suspend()
> [ 4.631163] arm-smmu 2b400000.iommu: arm_smmu_runtime_suspend: 0x00201936
> [ 4.637897] arm-smmu 2b400000.iommu: suspend latency exceeded, 6733980 ns
> [ 21.566983] arm-smmu 2b400000.iommu: genpd_runtime_resume()
> [ 21.584796] arm-smmu 2b400000.iommu: arm_smmu_runtime_resume: 0x00220101
> [ 21.591452] arm-smmu 2b400000.iommu: resume latency exceeded, 6658020 ns
> ...
>
> > +}
> > +
> > +static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev)
> > +{
> > + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
> > +
> > + clk_bulk_disable(smmu->num_clks, smmu->clks);
> > +
> > + return 0;
> > +}
> > +
> > static int __maybe_unused arm_smmu_pm_resume(struct device *dev)
> > {
> > struct arm_smmu_device *smmu = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + if (!pm_runtime_suspended(dev)) {
> > + ret = arm_smmu_runtime_resume(dev);
> > + if (ret)
> > + return ret;
> > + }
> >
> > arm_smmu_device_reset(smmu);
>
> This looks a bit off too - if we wake from sleep when the SMMU was also
> runtime-suspended, it appears we might end up trying to restore the
> register state without clocks enabled. Surely we need to always enable
> clocks for the reset, then restore the previous suspended state?
> Although given my previous point, it's probably not worth doing anything
> at all here for that case.
With a reset added to arm_smmu_runtime_resume(), we wouldn't need the
reset here anymore. With that, the code below should work.
if (pm_runtime_suspended(dev))
return 0;
return arm_smmu_runtime_resume(dev);
Best regards,
Tomasz
On Tue, Jul 24, 2018 at 8:51 PM, Robin Murphy <[email protected]> wrote:
> On 19/07/18 11:15, Vivek Gautam wrote:
>>
>> From: Sricharan R <[email protected]>
>>
>> The smmu needs to be functional only when the respective
>> master's using it are active. The device_link feature
>> helps to track such functional dependencies, so that the
>> iommu gets powered when the master device enables itself
>> using pm_runtime. So by adapting the smmu driver for
>> runtime pm, above said dependency can be addressed.
>>
>> This patch adds the pm runtime/sleep callbacks to the
>> driver and also the functions to parse the smmu clocks
>> from DT and enable them in resume/suspend.
>>
>> Also, while we enable the runtime pm add a pm sleep suspend
>> callback that pushes devices to low power state by turning
>> the clocks off in a system sleep.
>> Also add corresponding clock enable path in resume callback.
>>
>> Signed-off-by: Sricharan R <[email protected]>
>> Signed-off-by: Archit Taneja <[email protected]>
>> [vivek: rework for clock and pm ops]
>> Signed-off-by: Vivek Gautam <[email protected]>
>> Reviewed-by: Tomasz Figa <[email protected]>
>> ---
>>
>> Changes since v12:
>> - Added pm sleep .suspend callback. This disables the clocks.
>> - Added corresponding change to enable clocks in .resume
>> pm sleep callback.
>>
>> drivers/iommu/arm-smmu.c | 75
>> ++++++++++++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 73 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>> index c73cfce1ccc0..9138a6fffe04 100644
>> --- a/drivers/iommu/arm-smmu.c
>> +++ b/drivers/iommu/arm-smmu.c
>> @@ -48,6 +48,7 @@
>> #include <linux/of_iommu.h>
>> #include <linux/pci.h>
>> #include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>> #include <linux/slab.h>
>> #include <linux/spinlock.h>
>> @@ -205,6 +206,8 @@ struct arm_smmu_device {
>> u32 num_global_irqs;
>> u32 num_context_irqs;
>> unsigned int *irqs;
>> + struct clk_bulk_data *clks;
>> + int num_clks;
>> u32 cavium_id_base; /* Specific to
>> Cavium */
>> @@ -1897,10 +1900,12 @@ static int arm_smmu_device_cfg_probe(struct
>> arm_smmu_device *smmu)
>> struct arm_smmu_match_data {
>> enum arm_smmu_arch_version version;
>> enum arm_smmu_implementation model;
>> + const char * const *clks;
>> + int num_clks;
>> };
>> #define ARM_SMMU_MATCH_DATA(name, ver, imp) \
>> -static struct arm_smmu_match_data name = { .version = ver, .model = imp }
>> +static const struct arm_smmu_match_data name = { .version = ver, .model =
>> imp }
>> ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
>> ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
>> @@ -1919,6 +1924,23 @@ static const struct of_device_id
>> arm_smmu_of_match[] = {
>> };
>> MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
>> +static void arm_smmu_fill_clk_data(struct arm_smmu_device *smmu,
>> + const char * const *clks)
>> +{
>> + int i;
>> +
>> + if (smmu->num_clks < 1)
>> + return;
>> +
>> + smmu->clks = devm_kcalloc(smmu->dev, smmu->num_clks,
>> + sizeof(*smmu->clks), GFP_KERNEL);
>> + if (!smmu->clks)
>> + return;
>> +
>> + for (i = 0; i < smmu->num_clks; i++)
>> + smmu->clks[i].id = clks[i];
>> +}
>> +
>> #ifdef CONFIG_ACPI
>> static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
>> {
>> @@ -2001,6 +2023,9 @@ static int arm_smmu_device_dt_probe(struct
>> platform_device *pdev,
>> data = of_device_get_match_data(dev);
>> smmu->version = data->version;
>> smmu->model = data->model;
>> + smmu->num_clks = data->num_clks;
>> +
>> + arm_smmu_fill_clk_data(smmu, data->clks);
>> parse_driver_options(smmu);
>> @@ -2099,6 +2124,14 @@ static int arm_smmu_device_probe(struct
>> platform_device *pdev)
>> smmu->irqs[i] = irq;
>> }
>> + err = devm_clk_bulk_get(smmu->dev, smmu->num_clks, smmu->clks);
>> + if (err)
>> + return err;
>> +
>> + err = clk_bulk_prepare(smmu->num_clks, smmu->clks);
>> + if (err)
>> + return err;
>> +
>> err = arm_smmu_device_cfg_probe(smmu);
>> if (err)
>> return err;
>> @@ -2181,6 +2214,9 @@ static int arm_smmu_device_remove(struct
>> platform_device *pdev)
>> /* Turn the thing off */
>> writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
>> +
>> + clk_bulk_unprepare(smmu->num_clks, smmu->clks);
>> +
>> return 0;
>> }
>> @@ -2189,15 +2225,50 @@ static void arm_smmu_device_shutdown(struct
>> platform_device *pdev)
>> arm_smmu_device_remove(pdev);
>> }
>> +static int __maybe_unused arm_smmu_runtime_resume(struct device *dev)
>> +{
>> + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
>> +
>> + return clk_bulk_enable(smmu->num_clks, smmu->clks);
>
>
> If there's a power domain being automatically switched by genpd then we need
> a reset here because we may have lost state entirely. Since I remembered the
> otherwise-useless GPU SMMU on Juno is in a separate power domain, I gave it
> a poking via sysfs with some debug stuff to dump sCR0 in these callbacks,
> and the problem is clear:
>
> ...
> [ 4.625551] arm-smmu 2b400000.iommu: genpd_runtime_suspend()
> [ 4.631163] arm-smmu 2b400000.iommu: arm_smmu_runtime_suspend: 0x00201936
> [ 4.637897] arm-smmu 2b400000.iommu: suspend latency exceeded, 6733980 ns
> [ 21.566983] arm-smmu 2b400000.iommu: genpd_runtime_resume()
> [ 21.584796] arm-smmu 2b400000.iommu: arm_smmu_runtime_resume: 0x00220101
> [ 21.591452] arm-smmu 2b400000.iommu: resume latency exceeded, 6658020 ns
> ...
Qualcomm SoCs have retention enabled for SMMU registers so they don't
lose state.
...
[ 256.013367] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
SCR0 = 0x201e36
[ 256.013367]
[ 256.019160] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
SCR0 = 0x201e36
[ 256.019160]
[ 256.027368] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
SCR0 = 0x201e36
[ 256.027368]
[ 256.036786] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
SCR0 = 0x201e36
...
However after adding arm_smmu_device_reset() in runtime_resume() I observe
some performance degradation when kill an instance of 'kmscube' and
start it again.
The launch time with arm_smmu_device_reset() in runtime_resume() change is
more.
Could this be because of frequent TLB invalidation and sync?
Best regards
Vivek
>
>> +}
>> +
>> +static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev)
>> +{
>> + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
>> +
>> + clk_bulk_disable(smmu->num_clks, smmu->clks);
>> +
>> + return 0;
>> +}
>> +
>> static int __maybe_unused arm_smmu_pm_resume(struct device *dev)
>> {
>> struct arm_smmu_device *smmu = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + if (!pm_runtime_suspended(dev)) {
>> + ret = arm_smmu_runtime_resume(dev);
>> + if (ret)
>> + return ret;
>> + }
>> arm_smmu_device_reset(smmu);
>
>
> This looks a bit off too - if we wake from sleep when the SMMU was also
> runtime-suspended, it appears we might end up trying to restore the register
> state without clocks enabled. Surely we need to always enable clocks for the
> reset, then restore the previous suspended state? Although given my previous
> point, it's probably not worth doing anything at all here for that case.
>
> Robin.
>
>> return 0;
>> }
>> -static SIMPLE_DEV_PM_OPS(arm_smmu_pm_ops, NULL, arm_smmu_pm_resume);
>> +static int __maybe_unused arm_smmu_pm_suspend(struct device *dev)
>> +{
>> + if (!pm_runtime_suspended(dev))
>> + return arm_smmu_runtime_suspend(dev);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct dev_pm_ops arm_smmu_pm_ops = {
>> + SET_SYSTEM_SLEEP_PM_OPS(arm_smmu_pm_suspend, arm_smmu_pm_resume)
>> + SET_RUNTIME_PM_OPS(arm_smmu_runtime_suspend,
>> + arm_smmu_runtime_resume, NULL)
>> +};
>> static struct platform_driver arm_smmu_driver = {
>> .driver = {
>>
> _______________________________________________
> iommu mailing list
> [email protected]
> https://lists.linuxfoundation.org/mailman/listinfo/iommu
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On Wed, Jul 25, 2018 at 11:46 PM, Vivek Gautam
<[email protected]> wrote:
> On Tue, Jul 24, 2018 at 8:51 PM, Robin Murphy <[email protected]> wrote:
>> On 19/07/18 11:15, Vivek Gautam wrote:
>>>
>>> From: Sricharan R <[email protected]>
>>>
>>> The smmu needs to be functional only when the respective
>>> master's using it are active. The device_link feature
>>> helps to track such functional dependencies, so that the
>>> iommu gets powered when the master device enables itself
>>> using pm_runtime. So by adapting the smmu driver for
>>> runtime pm, above said dependency can be addressed.
>>>
>>> This patch adds the pm runtime/sleep callbacks to the
>>> driver and also the functions to parse the smmu clocks
>>> from DT and enable them in resume/suspend.
>>>
>>> Also, while we enable the runtime pm add a pm sleep suspend
>>> callback that pushes devices to low power state by turning
>>> the clocks off in a system sleep.
>>> Also add corresponding clock enable path in resume callback.
>>>
>>> Signed-off-by: Sricharan R <[email protected]>
>>> Signed-off-by: Archit Taneja <[email protected]>
>>> [vivek: rework for clock and pm ops]
>>> Signed-off-by: Vivek Gautam <[email protected]>
>>> Reviewed-by: Tomasz Figa <[email protected]>
>>> ---
>>>
>>> Changes since v12:
>>> - Added pm sleep .suspend callback. This disables the clocks.
>>> - Added corresponding change to enable clocks in .resume
>>> pm sleep callback.
>>>
>>> drivers/iommu/arm-smmu.c | 75
>>> ++++++++++++++++++++++++++++++++++++++++++++++--
>>> 1 file changed, 73 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>> index c73cfce1ccc0..9138a6fffe04 100644
>>> --- a/drivers/iommu/arm-smmu.c
>>> +++ b/drivers/iommu/arm-smmu.c
[snip]
>>> platform_device *pdev)
>>> arm_smmu_device_remove(pdev);
>>> }
>>> +static int __maybe_unused arm_smmu_runtime_resume(struct device *dev)
>>> +{
>>> + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
>>> +
>>> + return clk_bulk_enable(smmu->num_clks, smmu->clks);
>>
>>
>> If there's a power domain being automatically switched by genpd then we need
>> a reset here because we may have lost state entirely. Since I remembered the
>> otherwise-useless GPU SMMU on Juno is in a separate power domain, I gave it
>> a poking via sysfs with some debug stuff to dump sCR0 in these callbacks,
>> and the problem is clear:
>>
>> ...
>> [ 4.625551] arm-smmu 2b400000.iommu: genpd_runtime_suspend()
>> [ 4.631163] arm-smmu 2b400000.iommu: arm_smmu_runtime_suspend: 0x00201936
>> [ 4.637897] arm-smmu 2b400000.iommu: suspend latency exceeded, 6733980 ns
>> [ 21.566983] arm-smmu 2b400000.iommu: genpd_runtime_resume()
>> [ 21.584796] arm-smmu 2b400000.iommu: arm_smmu_runtime_resume: 0x00220101
>> [ 21.591452] arm-smmu 2b400000.iommu: resume latency exceeded, 6658020 ns
>> ...
>
> Qualcomm SoCs have retention enabled for SMMU registers so they don't
> lose state.
> ...
> [ 256.013367] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
> SCR0 = 0x201e36
> [ 256.013367]
> [ 256.019160] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
> SCR0 = 0x201e36
> [ 256.019160]
> [ 256.027368] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
> SCR0 = 0x201e36
> [ 256.027368]
> [ 256.036786] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
> SCR0 = 0x201e36
> ...
>
> However after adding arm_smmu_device_reset() in runtime_resume() I observe
> some performance degradation when kill an instance of 'kmscube' and
> start it again.
> The launch time with arm_smmu_device_reset() in runtime_resume() change is
> more.
> Could this be because of frequent TLB invalidation and sync?
Some more information that i gathered.
On Qcom SoCs besides the registers retention, TCU invalidates TLB cache on
a CX power collapse exit, which is the system wide suspend case.
The arm-smmu software is not aware of this CX power collapse /
auto-invalidation.
So wouldn't doing an explicit TLB invalidations during runtime resume be
detrimental to performance?
I have one more doubt here -
We do runtime power cycle around arm_smmu_map/unmap() too.
Now during map/unmap we selectively do TLB maintenance (either
tlb_sync or tlb_add_flush).
But with runtime pm we want to do TLBIALL*. Is that a problem?
Best regards
Vivek
>
> Best regards
> Vivek
[snip]
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 26/07/18 08:12, Vivek Gautam wrote:
> On Wed, Jul 25, 2018 at 11:46 PM, Vivek Gautam
> <[email protected]> wrote:
>> On Tue, Jul 24, 2018 at 8:51 PM, Robin Murphy <[email protected]> wrote:
>>> On 19/07/18 11:15, Vivek Gautam wrote:
>>>>
>>>> From: Sricharan R <[email protected]>
>>>>
>>>> The smmu needs to be functional only when the respective
>>>> master's using it are active. The device_link feature
>>>> helps to track such functional dependencies, so that the
>>>> iommu gets powered when the master device enables itself
>>>> using pm_runtime. So by adapting the smmu driver for
>>>> runtime pm, above said dependency can be addressed.
>>>>
>>>> This patch adds the pm runtime/sleep callbacks to the
>>>> driver and also the functions to parse the smmu clocks
>>>> from DT and enable them in resume/suspend.
>>>>
>>>> Also, while we enable the runtime pm add a pm sleep suspend
>>>> callback that pushes devices to low power state by turning
>>>> the clocks off in a system sleep.
>>>> Also add corresponding clock enable path in resume callback.
>>>>
>>>> Signed-off-by: Sricharan R <[email protected]>
>>>> Signed-off-by: Archit Taneja <[email protected]>
>>>> [vivek: rework for clock and pm ops]
>>>> Signed-off-by: Vivek Gautam <[email protected]>
>>>> Reviewed-by: Tomasz Figa <[email protected]>
>>>> ---
>>>>
>>>> Changes since v12:
>>>> - Added pm sleep .suspend callback. This disables the clocks.
>>>> - Added corresponding change to enable clocks in .resume
>>>> pm sleep callback.
>>>>
>>>> drivers/iommu/arm-smmu.c | 75
>>>> ++++++++++++++++++++++++++++++++++++++++++++++--
>>>> 1 file changed, 73 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>>> index c73cfce1ccc0..9138a6fffe04 100644
>>>> --- a/drivers/iommu/arm-smmu.c
>>>> +++ b/drivers/iommu/arm-smmu.c
>
> [snip]
>
>>>> platform_device *pdev)
>>>> arm_smmu_device_remove(pdev);
>>>> }
>>>> +static int __maybe_unused arm_smmu_runtime_resume(struct device *dev)
>>>> +{
>>>> + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
>>>> +
>>>> + return clk_bulk_enable(smmu->num_clks, smmu->clks);
>>>
>>>
>>> If there's a power domain being automatically switched by genpd then we need
>>> a reset here because we may have lost state entirely. Since I remembered the
>>> otherwise-useless GPU SMMU on Juno is in a separate power domain, I gave it
>>> a poking via sysfs with some debug stuff to dump sCR0 in these callbacks,
>>> and the problem is clear:
>>>
>>> ...
>>> [ 4.625551] arm-smmu 2b400000.iommu: genpd_runtime_suspend()
>>> [ 4.631163] arm-smmu 2b400000.iommu: arm_smmu_runtime_suspend: 0x00201936
>>> [ 4.637897] arm-smmu 2b400000.iommu: suspend latency exceeded, 6733980 ns
>>> [ 21.566983] arm-smmu 2b400000.iommu: genpd_runtime_resume()
>>> [ 21.584796] arm-smmu 2b400000.iommu: arm_smmu_runtime_resume: 0x00220101
>>> [ 21.591452] arm-smmu 2b400000.iommu: resume latency exceeded, 6658020 ns
>>> ...
>>
>> Qualcomm SoCs have retention enabled for SMMU registers so they don't
>> lose state.
>> ...
>> [ 256.013367] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
>> SCR0 = 0x201e36
>> [ 256.013367]
>> [ 256.019160] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
>> SCR0 = 0x201e36
>> [ 256.019160]
>> [ 256.027368] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
>> SCR0 = 0x201e36
>> [ 256.027368]
>> [ 256.036786] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
>> SCR0 = 0x201e36
>> ...
>>
>> However after adding arm_smmu_device_reset() in runtime_resume() I observe
>> some performance degradation when kill an instance of 'kmscube' and
>> start it again.
>> The launch time with arm_smmu_device_reset() in runtime_resume() change is
>> more.
>> Could this be because of frequent TLB invalidation and sync?
Probably. Plus the reset procedure is a big chunk of MMIO accesses,
which for a non-trivial SMMU configuration probably isn't negligible in
itself. Unfortunately, unless you know for absolute certain that you
don't need to do that, you do.
> Some more information that i gathered.
> On Qcom SoCs besides the registers retention, TCU invalidates TLB cache on
> a CX power collapse exit, which is the system wide suspend case.
> The arm-smmu software is not aware of this CX power collapse /
> auto-invalidation.
>
> So wouldn't doing an explicit TLB invalidations during runtime resume be
> detrimental to performance?
Indeed it would be, but resuming with TLBs full of random valid-looking
junk is even more so.
> I have one more doubt here -
> We do runtime power cycle around arm_smmu_map/unmap() too.
> Now during map/unmap we selectively do TLB maintenance (either
> tlb_sync or tlb_add_flush).
> But with runtime pm we want to do TLBIALL*. Is that a problem?
It's technically redundant to do both, true, but as we've covered in
previous rounds of discussion it's very difficult to know *which* one is
sufficient at any given time, so in order to make progress for now I
think we have to settle with doing both.
Robin.
On 7/26/2018 9:00 PM, Robin Murphy wrote:
> On 26/07/18 08:12, Vivek Gautam wrote:
>> On Wed, Jul 25, 2018 at 11:46 PM, Vivek Gautam
>> <[email protected]> wrote:
>>> On Tue, Jul 24, 2018 at 8:51 PM, Robin Murphy <[email protected]>
>>> wrote:
>>>> On 19/07/18 11:15, Vivek Gautam wrote:
>>>>>
>>>>> From: Sricharan R <[email protected]>
>>>>>
>>>>> The smmu needs to be functional only when the respective
>>>>> master's using it are active. The device_link feature
>>>>> helps to track such functional dependencies, so that the
>>>>> iommu gets powered when the master device enables itself
>>>>> using pm_runtime. So by adapting the smmu driver for
>>>>> runtime pm, above said dependency can be addressed.
>>>>>
>>>>> This patch adds the pm runtime/sleep callbacks to the
>>>>> driver and also the functions to parse the smmu clocks
>>>>> from DT and enable them in resume/suspend.
>>>>>
>>>>> Also, while we enable the runtime pm add a pm sleep suspend
>>>>> callback that pushes devices to low power state by turning
>>>>> the clocks off in a system sleep.
>>>>> Also add corresponding clock enable path in resume callback.
>>>>>
>>>>> Signed-off-by: Sricharan R <[email protected]>
>>>>> Signed-off-by: Archit Taneja <[email protected]>
>>>>> [vivek: rework for clock and pm ops]
>>>>> Signed-off-by: Vivek Gautam <[email protected]>
>>>>> Reviewed-by: Tomasz Figa <[email protected]>
>>>>> ---
>>>>>
>>>>> Changes since v12:
>>>>> - Added pm sleep .suspend callback. This disables the clocks.
>>>>> - Added corresponding change to enable clocks in .resume
>>>>> pm sleep callback.
>>>>>
>>>>> drivers/iommu/arm-smmu.c | 75
>>>>> ++++++++++++++++++++++++++++++++++++++++++++++--
>>>>> 1 file changed, 73 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>>>> index c73cfce1ccc0..9138a6fffe04 100644
>>>>> --- a/drivers/iommu/arm-smmu.c
>>>>> +++ b/drivers/iommu/arm-smmu.c
>>
>> [snip]
>>
>>>>> platform_device *pdev)
>>>>> arm_smmu_device_remove(pdev);
>>>>> }
>>>>> +static int __maybe_unused arm_smmu_runtime_resume(struct
>>>>> device *dev)
>>>>> +{
>>>>> + struct arm_smmu_device *smmu = dev_get_drvdata(dev);
>>>>> +
>>>>> + return clk_bulk_enable(smmu->num_clks, smmu->clks);
>>>>
>>>>
>>>> If there's a power domain being automatically switched by genpd
>>>> then we need
>>>> a reset here because we may have lost state entirely. Since I
>>>> remembered the
>>>> otherwise-useless GPU SMMU on Juno is in a separate power domain, I
>>>> gave it
>>>> a poking via sysfs with some debug stuff to dump sCR0 in these
>>>> callbacks,
>>>> and the problem is clear:
>>>>
>>>> ...
>>>> [ 4.625551] arm-smmu 2b400000.iommu: genpd_runtime_suspend()
>>>> [ 4.631163] arm-smmu 2b400000.iommu: arm_smmu_runtime_suspend:
>>>> 0x00201936
>>>> [ 4.637897] arm-smmu 2b400000.iommu: suspend latency exceeded,
>>>> 6733980 ns
>>>> [ 21.566983] arm-smmu 2b400000.iommu: genpd_runtime_resume()
>>>> [ 21.584796] arm-smmu 2b400000.iommu: arm_smmu_runtime_resume:
>>>> 0x00220101
>>>> [ 21.591452] arm-smmu 2b400000.iommu: resume latency exceeded,
>>>> 6658020 ns
>>>> ...
>>>
>>> Qualcomm SoCs have retention enabled for SMMU registers so they don't
>>> lose state.
>>> ...
>>> [ 256.013367] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
>>> SCR0 = 0x201e36
>>> [ 256.013367]
>>> [ 256.019160] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
>>> SCR0 = 0x201e36
>>> [ 256.019160]
>>> [ 256.027368] arm-smmu b40000.arm,smmu: arm_smmu_runtime_suspend
>>> SCR0 = 0x201e36
>>> [ 256.027368]
>>> [ 256.036786] arm-smmu b40000.arm,smmu: arm_smmu_runtime_resume
>>> SCR0 = 0x201e36
>>> ...
>>>
>>> However after adding arm_smmu_device_reset() in runtime_resume() I
>>> observe
>>> some performance degradation when kill an instance of 'kmscube' and
>>> start it again.
>>> The launch time with arm_smmu_device_reset() in runtime_resume()
>>> change is
>>> more.
>>> Could this be because of frequent TLB invalidation and sync?
>
> Probably. Plus the reset procedure is a big chunk of MMIO accesses,
> which for a non-trivial SMMU configuration probably isn't negligible
> in itself. Unfortunately, unless you know for absolute certain that
> you don't need to do that, you do.
>
>> Some more information that i gathered.
>> On Qcom SoCs besides the registers retention, TCU invalidates TLB
>> cache on
>> a CX power collapse exit, which is the system wide suspend case.
>> The arm-smmu software is not aware of this CX power collapse /
>> auto-invalidation.
>>
>> So wouldn't doing an explicit TLB invalidations during runtime resume be
>> detrimental to performance?
>
> Indeed it would be, but resuming with TLBs full of random
> valid-looking junk is even more so.
>
>> I have one more doubt here -
>> We do runtime power cycle around arm_smmu_map/unmap() too.
>> Now during map/unmap we selectively do TLB maintenance (either
>> tlb_sync or tlb_add_flush).
>> But with runtime pm we want to do TLBIALL*. Is that a problem?
>
> It's technically redundant to do both, true, but as we've covered in
> previous rounds of discussion it's very difficult to know *which* one
> is sufficient at any given time, so in order to make progress for now
> I think we have to settle with doing both.
Thanks Robin. I will respin the patches as Tomasz also suggested;
arm_smmu_runtime_resume() will look like:
if (pm_runtime_suspended(dev))
return 0;
return arm_smmu_runtime_resume(dev);
and,
arm_smmu_runtime_resume() will have arm_smmu_device_reset().
Best regards
Vivek
>
> Robin.
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