The purpose of this series is to add the display support for the mt8365-evk.
This is the list of HWs / IPs support added:
- Connectors (HW):
- HDMI
- MIPI DSI (Mobile Industry Processor Interface Display Serial Interface)
- HDMI bridge (it66121)
- DSI pannel (startek,kd070fhfid015)
- SoC display blocks (IP):
- OVL0 (Overlay)
- RDMA0 (Data Path Read DMA)
- Color0
- CCorr0 (Color Correction)
- AAL0 (Adaptive Ambient Light)
- GAMMA0
- Dither0
- DSI0 (Display Serial Interface)
- RDMA1 (Data Path Read DMA)
- DPI0 (Display Parallel Interface)
The Mediatek DSI, DPI and DRM drivers are also improved.
Regards,
Alex
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Alexandre Mergnat (14):
dt-bindings: display: mediatek: aal: add binding for MT8365 SoC
dt-bindings: display: mediatek: ccorr: add binding for MT8365 SoC
dt-bindings: display: mediatek: color: add binding for MT8365 SoC
dt-bindings: display: mediatek: dither: add binding for MT8365 SoC
dt-bindings: display: mediatek: dsi: add binding for MT8365 SoC
dt-bindings: display: mediatek: gamma: add binding for MT8365 SoC
dt-bindings: display: mediatek: ovl: add binding for MT8365 SoC
dt-bindings: display: mediatek: rdma: add binding for MT8365 SoC
dt-bindings: pwm: add power-domains property
dt-bindings: pwm: add binding for mt8365 SoC
drm/mediatek: dsi: Improves the DSI lane setup robustness
arm64: defconfig: enable display connector support
arm64: dts: mediatek: add display blocks support for the MT8365 SoC
arm64: dts: mediatek: add display support for mt8365-evk
Fabien Parent (4):
dt-bindings: display: mediatek: dpi: add power-domains property
dt-bindings: display: mediatek: dpi: add binding for MT8365
drm/mediatek: dpi: add support for dpi clock
drm/mediatek: add MT8365 SoC support
.../bindings/display/mediatek/mediatek,aal.yaml | 1 +
.../bindings/display/mediatek/mediatek,ccorr.yaml | 3 +
.../bindings/display/mediatek/mediatek,color.yaml | 1 +
.../bindings/display/mediatek/mediatek,dither.yaml | 1 +
.../bindings/display/mediatek/mediatek,dpi.yaml | 24 +++
.../bindings/display/mediatek/mediatek,dsi.yaml | 2 +
.../bindings/display/mediatek/mediatek,gamma.yaml | 1 +
.../bindings/display/mediatek/mediatek,ovl.yaml | 1 +
.../bindings/display/mediatek/mediatek,rdma.yaml | 1 +
.../devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 9 +
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 183 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 ++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/gpu/drm/mediatek/mtk_dpi.c | 50 +++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++++
drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +
16 files changed, 455 insertions(+), 1 deletion(-)
---
base-commit: d27bed55ce32b0732ef65561851fec3dc8d01852
change-id: 20231023-display-support-c6418b30e419
Best regards,
--
Alexandre Mergnat <[email protected]>
Display Color for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index f21e44092043..fbf15242af52 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -39,6 +39,7 @@ properties:
- mediatek,mt8188-disp-color
- mediatek,mt8192-disp-color
- mediatek,mt8195-disp-color
+ - mediatek,mt8365-disp-color
- const: mediatek,mt8173-disp-color
reg:
maxItems: 1
--
2.25.1
Display Dither for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 1588b3f7cec7..6fceb1f95d2a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -30,6 +30,7 @@ properties:
- mediatek,mt8188-disp-dither
- mediatek,mt8192-disp-dither
- mediatek,mt8195-disp-dither
+ - mediatek,mt8365-disp-dither
- const: mediatek,mt8183-disp-dither
reg:
--
2.25.1
From: Fabien Parent <[email protected]>
DPI is part of the display / multimedia block in MediaTek SoCs, and
always have a power-domain (at least in the upstream device-trees).
Add the power-domains property to the binding documentation.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 803c00f26206..e126486e8eac 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -64,6 +64,9 @@ properties:
Output port node. This port should be connected to the input port of an
attached HDMI, LVDS or DisplayPort encoder chip.
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -78,11 +81,13 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
--
2.25.1
Display Serial Interface for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index 12441b937684..2479b9e4abd2 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -34,6 +34,8 @@ properties:
- enum:
- mediatek,mt6795-dsi
- const: mediatek,mt8173-dsi
+ - mediatek,mt8365-dsi
+ - const: mediatek,mt8183-dsi
reg:
maxItems: 1
--
2.25.1
From: Fabien Parent <[email protected]>
DPI for MT8365 is compatible with MT8192 but requires an additional
clock. Modify the documentation to requires this clock only on MT8365 SoCs.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
.../bindings/display/mediatek/mediatek,dpi.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index e126486e8eac..c86527c33acf 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -27,6 +27,7 @@ properties:
- mediatek,mt8188-dp-intf
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
+ - mediatek,mt8365-dpi
- items:
- enum:
- mediatek,mt6795-dpi
@@ -39,16 +40,20 @@ properties:
maxItems: 1
clocks:
+ minItems: 3
items:
- description: Pixel Clock
- description: Engine Clock
- description: DPI PLL
+ - description: DPI Clock
clock-names:
+ minItems: 3
items:
- const: pixel
- const: engine
- const: pll
+ - const: dpi
pinctrl-0: true
pinctrl-1: true
@@ -77,6 +82,20 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8365-dpi
+
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
--
2.25.1
Display GAMMA for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index c6641acd75d6..f447f4320e8b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -34,6 +34,7 @@ properties:
- mediatek,mt8188-disp-gamma
- mediatek,mt8192-disp-gamma
- mediatek,mt8195-disp-gamma
+ - mediatek,mt8365-disp-gamma
- const: mediatek,mt8183-disp-gamma
reg:
--
2.25.1
Display Data Path Read DMA for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index 39dbb5c8bcf8..4cadb245d028 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -45,6 +45,7 @@ properties:
- enum:
- mediatek,mt8186-disp-rdma
- mediatek,mt8192-disp-rdma
+ - mediatek,mt8365-disp-rdma
- const: mediatek,mt8183-disp-rdma
reg:
--
2.25.1
Display Overlay for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8192 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 3e1069b00b56..2873bbdf3979 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -43,6 +43,7 @@ properties:
- items:
- enum:
- mediatek,mt8186-disp-ovl
+ - mediatek,mt8365-disp-ovl
- const: mediatek,mt8192-disp-ovl
reg:
--
2.25.1
According to the Mediatek datasheet, the display PWM block has a power
domain.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
index 153e146df7d4..efe0cacf55b7 100644
--- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
+++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
@@ -53,6 +53,12 @@ properties:
- const: main
- const: mm
+ power-domains:
+ maxItems: 1
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
required:
- compatible
- reg
@@ -67,6 +73,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8173-power.h>
pwm0: pwm@1401e000 {
compatible = "mediatek,mt8173-disp-pwm";
@@ -75,4 +82,5 @@ examples:
clocks = <&mmsys CLK_MM_DISP_PWM026M>,
<&mmsys CLK_MM_DISP_PWM0MM>;
clock-names = "main", "mm";
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
};
--
2.25.1
Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
index efe0cacf55b7..e4069bcbf8d5 100644
--- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
+++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
@@ -32,6 +32,7 @@ properties:
- mediatek,mt8188-disp-pwm
- mediatek,mt8192-disp-pwm
- mediatek,mt8195-disp-pwm
+ - mediatek,mt8365-disp-pwm
- const: mediatek,mt8183-disp-pwm
reg:
--
2.25.1
From: Fabien Parent <[email protected]>
MT8365 requires an additional clock for DPI. Add support for that
additional clock.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 50 +++++++++++++++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 2f931e4e2b60..ddd7c54febe6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -70,6 +70,7 @@ struct mtk_dpi {
struct device *mmsys_dev;
struct clk *engine_clk;
struct clk *pixel_clk;
+ struct clk *dpi_clk;
struct clk *tvd_clk;
int irq;
struct drm_display_mode mode;
@@ -137,6 +138,7 @@ struct mtk_dpi_yc_limit {
* @csc_enable_bit: Enable bit of CSC.
* @pixels_per_iter: Quantity of transferred pixels per iteration.
* @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
+ * @is_dpi_clk_req: Support the additionnal DPI clock.
*/
struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
@@ -156,6 +158,7 @@ struct mtk_dpi_conf {
u32 csc_enable_bit;
u32 pixels_per_iter;
bool edge_cfg_in_mmsys;
+ bool is_dpi_clk_req;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -472,6 +475,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
mtk_dpi_disable(dpi);
clk_disable_unprepare(dpi->pixel_clk);
clk_disable_unprepare(dpi->engine_clk);
+ clk_disable_unprepare(dpi->dpi_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi)
@@ -481,10 +485,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
if (++dpi->refcount != 1)
return 0;
+ ret = clk_prepare_enable(dpi->dpi_clk);
+ if (ret) {
+ dev_err(dpi->dev, "failed to enable dpi clock: %d\n", ret);
+ goto err_refcount;
+ }
+
ret = clk_prepare_enable(dpi->engine_clk);
if (ret) {
dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
- goto err_refcount;
+ goto err_engine;
}
ret = clk_prepare_enable(dpi->pixel_clk);
@@ -497,6 +507,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel:
clk_disable_unprepare(dpi->engine_clk);
+err_engine:
+ clk_disable_unprepare(dpi->dpi_clk);
err_refcount:
dpi->refcount--;
return ret;
@@ -902,6 +914,7 @@ static const struct mtk_dpi_conf mt8173_conf = {
.channel_swap_shift = CH_SWAP,
.yuv422_en_bit = YUV422_EN,
.csc_enable_bit = CSC_ENABLE,
+ .is_dpi_clk_req = false,
};
static const struct mtk_dpi_conf mt2701_conf = {
@@ -920,6 +933,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
.channel_swap_shift = CH_SWAP,
.yuv422_en_bit = YUV422_EN,
.csc_enable_bit = CSC_ENABLE,
+ .is_dpi_clk_req = false,
};
static const struct mtk_dpi_conf mt8183_conf = {
@@ -937,6 +951,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
.channel_swap_shift = CH_SWAP,
.yuv422_en_bit = YUV422_EN,
.csc_enable_bit = CSC_ENABLE,
+ .is_dpi_clk_req = false,
};
static const struct mtk_dpi_conf mt8186_conf = {
@@ -969,6 +984,7 @@ static const struct mtk_dpi_conf mt8188_dpintf_conf = {
.channel_swap_shift = DPINTF_CH_SWAP,
.yuv422_en_bit = DPINTF_YUV422_EN,
.csc_enable_bit = DPINTF_CSC_ENABLE,
+ .is_dpi_clk_req = false,
};
static const struct mtk_dpi_conf mt8192_conf = {
@@ -986,6 +1002,7 @@ static const struct mtk_dpi_conf mt8192_conf = {
.channel_swap_shift = CH_SWAP,
.yuv422_en_bit = YUV422_EN,
.csc_enable_bit = CSC_ENABLE,
+ .is_dpi_clk_req = false,
};
static const struct mtk_dpi_conf mt8195_dpintf_conf = {
@@ -1000,6 +1017,25 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = {
.channel_swap_shift = DPINTF_CH_SWAP,
.yuv422_en_bit = DPINTF_YUV422_EN,
.csc_enable_bit = DPINTF_CSC_ENABLE,
+ .is_dpi_clk_req = false,
+};
+
+static const struct mtk_dpi_conf mt8365_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .channel_swap_shift = CH_SWAP,
+ .csc_enable_bit = CSC_ENABLE,
+ .dimension_mask = HPW_MASK,
+ .hvsize_mask = HSIZE_MASK,
+ .is_ck_de_pol = true,
+ .is_dpi_clk_req = true,
+ .max_clock_khz = 150000,
+ .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+ .output_fmts = mt8183_output_fmts,
+ .pixels_per_iter = 1,
+ .reg_h_fre_con = 0xe0,
+ .support_direct_pin = true,
+ .swap_input_support = true,
+ .yuv422_en_bit = YUV422_EN,
};
static int mtk_dpi_probe(struct platform_device *pdev)
@@ -1056,6 +1092,17 @@ static int mtk_dpi_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(dpi->tvd_clk),
"Failed to get tvdpll clock\n");
+ if (dpi->conf->is_dpi_clk_req) {
+ dpi->dpi_clk = devm_clk_get(dev, "dpi");
+ if (IS_ERR(dpi->dpi_clk)) {
+ ret = PTR_ERR(dpi->dpi_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get dpi clock: %d\n", ret);
+
+ return ret;
+ }
+ }
+
dpi->irq = platform_get_irq(pdev, 0);
if (dpi->irq < 0)
return dpi->irq;
@@ -1097,6 +1144,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8188-dp-intf", .data = &mt8188_dpintf_conf },
{ .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
{ .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
+ { .compatible = "mediatek,mt8365-dpi", .data = &mt8365_conf },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
--
2.25.1
Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered
before mtk_dsi_poweron. lanes_ready flag toggle to true during
mtk_dsi_lane_ready function, and the DSI module is set up during
mtk_dsi_poweron.
Later, during panel driver init, mtk_dsi_lane_ready is triggered but does
nothing because lanes are considered ready. Unfortunately, when the panel
driver try to communicate, the DSI returns a timeout.
The solution found here is to put lanes_ready flag to false after the DSI
module setup into mtk_dsi_poweron to init the DSI lanes after the power /
setup of the DSI module.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index d8bfc2cce54d..81cf0ddcc399 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -668,6 +668,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
mtk_dsi_config_vdo_timing(dsi);
mtk_dsi_set_interrupt_enable(dsi);
+ dsi->lanes_ready = false;
+
return 0;
err_disable_engine_clk:
clk_disable_unprepare(dsi->engine_clk);
--
2.25.1
From: Fabien Parent <[email protected]>
Add DRM support for MT8365 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 93552d76b6e7..682ab464186f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -227,6 +227,22 @@ static const unsigned int mt8195_mtk_ddp_ext[] = {
DDP_COMPONENT_DP_INTF1,
};
+static const unsigned int mt8365_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DSI0,
+};
+
+static const unsigned int mt8365_mtk_ddp_ext[] = {
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -311,6 +327,14 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.mmsys_dev_num = 2,
};
+static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
+ .main_path = mt8365_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main),
+ .ext_path = mt8365_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext),
+ .mmsys_dev_num = 1,
+};
+
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data},
@@ -336,6 +360,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8195_vdosys0_driver_data},
{ .compatible = "mediatek,mt8195-vdosys1",
.data = &mt8195_vdosys1_driver_data},
+ { .compatible = "mediatek,mt8365-mmsys",
+ .data = &mt8365_mmsys_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
@@ -703,6 +729,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8195-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8365-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -765,6 +793,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8186-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8365-dpi",
+ .data = (void *)MTK_DPI },
{ }
};
--
2.25.1
- Add aliases for each display components to help display drivers.
- Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals
for the LED driver of mobile LCM.
- Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane
output)
- Add the display mutex support.
- Add the following display component support:
- OVL0 (Overlay)
- RDMA0 (Data Path Read DMA)
- Color0
- CCorr0 (Color Correction)
- AAL0 (Adaptive Ambient Light)
- GAMMA0
- Dither0
- DSI0 (Display Serial Interface)
- RDMA1 (Data Path Read DMA)
- DPI0 (Display Parallel Interface)
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++++++++++++++++
1 file changed, 146 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 24581f7410aa..6096358f7d07 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>
@@ -17,6 +18,19 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ aal0 = &aal0;
+ ccorr0 = &ccorr0;
+ color0 = &color0;
+ dither0 = &dither0;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ gamma0 = &gamma0;
+ ovl0 = &ovl0;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -607,6 +621,17 @@ spi: spi@1100a000 {
status = "disabled";
};
+ disp_pwm: pwm@1100e000 {
+ compatible = "mediatek,mt8365-disp-pwm",
+ "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ clock-names = "main", "mm";
+ clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+ <&infracfg CLK_IFR_DISP_PWM>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ #pwm-cells = <2>;
+ };
+
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
@@ -703,6 +728,15 @@ ethernet: ethernet@112a0000 {
status = "disabled";
};
+ mipi_tx0: dsi-phy@11c00000 {
+ compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c00000 0 0x800>;
+ clock-output-names = "mipi_tx0_pll";
+ clocks = <&clk26m>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
@@ -732,6 +766,13 @@ mmsys: syscon@14000000 {
#clock-cells = <1>;
};
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8365-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
smi_common: smi@14002000 {
compatible = "mediatek,mt8365-smi-common";
reg = <0 0x14002000 0 0x1000>;
@@ -755,6 +796,111 @@ larb0: larb@14003000 {
mediatek,larb-id = <0>;
};
+ ovl0: ovl@1400b000 {
+ compatible = "mediatek,mt8365-disp-ovl",
+ "mediatek,mt8192-disp-ovl";
+ reg = <0 0x1400b000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_OVL0>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ rdma0: rdma@1400d000 {
+ compatible = "mediatek,mt8365-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400d000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,rdma-fifo-size = <5120>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ color0: color@1400f000 {
+ compatible = "mediatek,mt8365-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1400f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ ccorr0: ccorr@14010000 {
+ compatible = "mediatek,mt8365-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x14010000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ aal0: aal@14011000 {
+ compatible = "mediatek,mt8365-disp-aal",
+ "mediatek,mt8183-disp-aal";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_AAL0>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ gamma0: gamma@14012000 {
+ compatible = "mediatek,mt8365-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ dither0: dither@14013000 {
+ compatible = "mediatek,mt8365-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x14013000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ dsi0: dsi@14014000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14014000 0 0x1000>;
+ clock-names = "engine", "digital", "hs";
+ clocks = <&mmsys CLK_MM_MM_DSI0>,
+ <&mmsys CLK_MM_DSI0_DIG_DSI>,
+ <&mipi_tx0>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ phy-names = "dphy";
+ phys = <&mipi_tx0>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ rdma1: rdma@14016000 {
+ compatible = "mediatek,mt8365-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x14016000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,rdma-fifo-size = <2048>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ };
+
+ dpi0: dpi@14018000 {
+ compatible = "mediatek,mt8365-dpi";
+ reg = <0 0x14018000 0 0x1000>;
+ assigned-clock-parents = <&topckgen CLK_TOP_LVDSPLL_D4>;
+ assigned-clocks = <&topckgen CLK_TOP_DPI0_SEL>;
+ clock-names = "pixel", "engine", "pll", "dpi";
+ clocks = <&topckgen CLK_TOP_DPI0_SEL>,
+ <&mmsys CLK_MM_MM_DPI0>,
+ <&apmixedsys CLK_APMIXED_LVDSPLL>,
+ <&mmsys CLK_MM_DPI0_DPI0>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
+ status = "disabled";
+ };
+
camsys: syscon@15000000 {
compatible = "mediatek,mt8365-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
--
2.25.1
Enable this feature for the i350-evk HDMI connector support.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..0a60e7616abe 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -839,6 +839,7 @@ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_LONTIUM_LT8912B=m
CONFIG_DRM_LONTIUM_LT9611=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
--
2.25.1
MIPI DSI:
- Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg",
to power the pannel plugged to the DSI connector.
- Setup the Display Parallel Interface.
- Add the startek kd070fhfid015 pannel support.
HDMI:
- Add HDMI connector support.
- Add the "ite,it66121" HDMI bridge support, driven by I2C1.
- Setup the Display Parallel Interface.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 183 ++++++++++++++++++++++++++++
1 file changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 50cbaefa1a99..823d7623b8b8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -26,6 +26,18 @@ chosen {
stdout-path = "serial0:921600n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "d";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_connector_out>;
+ };
+ };
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";
@@ -86,6 +98,57 @@ optee_reserved: optee@43200000 {
reg = <0 0x43200000 0 0x00c00000>;
};
};
+
+ vsys_lcm_reg: regulator-vsys-lcm {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vsys_lcm";
+ };
+};
+
+&dpi0 {
+ pinctrl-0 = <&dpi_default_pins>;
+ pinctrl-1 = <&dpi_idle_pins>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&it66121_in>;
+ };
+ };
+};
+
+
+&dsi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "startek,kd070fhfid015";
+ status = "okay";
+ reg = <0>;
+ enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ iovcc-supply = <&mt6357_vsim1_reg>;
+ power-supply = <&vsys_lcm_reg>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+
+ port {
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
&cpu0 {
@@ -138,6 +201,50 @@ &i2c0 {
status = "okay";
};
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-div = <2>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ it66121hdmitx: it66121hdmitx@4c {
+ #sound-dai-cells = <0>;
+ compatible = "ite,it66121";
+ interrupt-parent = <&pio>;
+ interrupts = <68 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&ite_pins>;
+ pinctrl-names = "default";
+ reg = <0x4c>;
+ reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
+ vcn18-supply = <&mt6357_vsim2_reg>;
+ vcn33-supply = <&mt6357_vibr_reg>;
+ vrf12-supply = <&mt6357_vrf12_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ it66121_in: endpoint {
+ bus-width = <12>;
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
&mmc0 {
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
@@ -180,7 +287,55 @@ &mt6357_pmic {
#interrupt-cells = <2>;
};
+&mt6357_vsim1_reg {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+};
+
&pio {
+ dpi_default_pins: dpi-default-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
+ <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
+ <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
+ <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
+ <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
+ <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
+ <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
+ <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
+ <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
+ <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
+ <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
+ <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
+ <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
+ <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
+ <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
+ <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ dpi_idle_pins: dpi-idle-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
+ <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
+ <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
+ <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
+ <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
+ <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
+ <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
+ <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
+ <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
+ <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
+ <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
+ <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
+ <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
+ <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
+ <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
+ <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
+ };
+ };
+
ethernet_pins: ethernet-pins {
phy_reset_pins {
pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
@@ -222,6 +377,34 @@ pins {
};
};
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
+ <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
+ bias-pull-up;
+ };
+ };
+
+ ite_pins: ite-pins {
+
+ irq_ite_pins {
+ pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pwr_pins {
+ pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
+ <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
+ output-high;
+ };
+
+ rst_ite_pins {
+ pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
+ output-high;
+ };
+ };
+
mmc0_default_pins: mmc0-default-pins {
clk-pins {
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
--
2.25.1
On Mon, Oct 23, 2023 at 04:40:12PM +0200, Alexandre Mergnat wrote:
> Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
> along with MT8183 SoC.
Additionally here, for the subject,
"dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC"
Cheers
Conor.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> index efe0cacf55b7..e4069bcbf8d5 100644
> --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> @@ -32,6 +32,7 @@ properties:
> - mediatek,mt8188-disp-pwm
> - mediatek,mt8192-disp-pwm
> - mediatek,mt8195-disp-pwm
> + - mediatek,mt8365-disp-pwm
> - const: mediatek,mt8183-disp-pwm
>
> reg:
>
> --
> 2.25.1
>
Yo,
On Mon, Oct 23, 2023 at 04:40:11PM +0200, Alexandre Mergnat wrote:
> According to the Mediatek datasheet, the display PWM block has a power
> domain.
Datasheet for which soc? The mt8173? Is it valid for all devices in this
binding?
Cheers,
Conor.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> index 153e146df7d4..efe0cacf55b7 100644
> --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> @@ -53,6 +53,12 @@ properties:
> - const: main
> - const: mm
>
> + power-domains:
> + maxItems: 1
> + description: A phandle and PM domain specifier as defined by bindings of
> + the power controller specified by phandle. See
> + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> required:
> - compatible
> - reg
> @@ -67,6 +73,7 @@ examples:
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/mt8173-clk.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mt8173-power.h>
>
> pwm0: pwm@1401e000 {
> compatible = "mediatek,mt8173-disp-pwm";
> @@ -75,4 +82,5 @@ examples:
> clocks = <&mmsys CLK_MM_DISP_PWM026M>,
> <&mmsys CLK_MM_DISP_PWM0MM>;
> clock-names = "main", "mm";
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> };
>
> --
> 2.25.1
>
On Mon, Oct 23, 2023 at 04:40:12PM +0200, Alexandre Mergnat wrote:
> Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
> along with MT8183 SoC.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Acked-by: Uwe Kleine-K?nig <[email protected]>
What is the merge plan here? Should the whole series go in via drm?
Thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
Il 23/10/23 16:40, [email protected] ha scritto:
> From: Fabien Parent <[email protected]>
>
> MT8365 requires an additional clock for DPI. Add support for that
> additional clock.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
I'm not convinced that this is right... at all.
From a fast check of the MT8365 DPI clocks, I can see that the DPI0 clock declares
parent VPLL_DPIX (a fixed clock), but nothing ever has VPLL_DPIX_EN (which is the
GATE clock, enabling output of DPIx VPLL?).
But then, there's even more: no clock ever references the CLK_TOP_DPI0_SEL nor the
CLK_TOP_DPI1_SEL gate, which is a PLL parent selector... in other platforms, that
is muxing through the TVDPLL, but on MT8365 that is LVDSPLL?!
I have many questions now:
* Two PLLs are apparently brought up, but which one is the right one?!
* Is the LVDS PLL really used for DisplayPort? (dpi0_sel)
* Is the VPLL_DPIx PLL used for DisplayPort instead? (dpi0_dpi0)
* Why is the LVDSTX_PXL clock using the same PLL as DPI0?!
* Why is the VPLL_DPIx gate never enabled?
* Are you sure that CLK_MM_DPI0_DPI0's parent shouldn't be dpi0_sel instead?
* Where is DPI1 in this SoC? Why is there a dpi1_sel clock, but no MM clock
for the DPI1 controller? Is there any DPI1 controller, even?!
* Why is there a DPI1 MUX, if there's no DPI1 controller?!
Answering all those questions will lead you to the right change, which I believe
to be in the clock drivers, not here in mtk_dpi.c.
Cheers!
Angelo
Il 23/10/23 16:40, Alexandre Mergnat ha scritto:
> Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
> along with MT8183 SoC.
MT8365's Display PWM controller IP is the same as MT8183: blah blah blah :-)
because saying that it is compatible doesn't mean that it is the same...
That's a nitpick anyway, but whatever - you'll still have to send a v2 of
this series, so you have an easy chance to edit the commit description of
this one.
Nitpicks apart...
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> index efe0cacf55b7..e4069bcbf8d5 100644
> --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> @@ -32,6 +32,7 @@ properties:
> - mediatek,mt8188-disp-pwm
> - mediatek,mt8192-disp-pwm
> - mediatek,mt8195-disp-pwm
> + - mediatek,mt8365-disp-pwm
> - const: mediatek,mt8183-disp-pwm
>
> reg:
>
Il 23/10/23 16:40, [email protected] ha scritto:
> From: Fabien Parent <[email protected]>
>
> Add DRM support for MT8365 SoC.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Hello Conor
On 23/10/2023 19:38, Conor Dooley wrote:
> Yo,
>
> On Mon, Oct 23, 2023 at 04:40:11PM +0200, Alexandre Mergnat wrote:
>> According to the Mediatek datasheet, the display PWM block has a power
>> domain.
>
> Datasheet for which soc? The mt8173? Is it valid for all devices in this
> binding?
I can't verify for other SoC. Then, I fix the commit message
and remove the example changes.
>
> Cheers,
> Conor.
>
>>
..snip..
>> --
>> 2.25.1
>>
--
Regards,
Alexandre
On Mon, Oct 23, 2023 at 10:40 PM Alexandre Mergnat
<[email protected]> wrote:
>
> Display Color for MT8365 is compatible with another SoC.
> Then, add MT8365 binding along with MT8183 SoC.
This unfortunately doesn't match what the patch is doing.
ChenYu
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> index f21e44092043..fbf15242af52 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> @@ -39,6 +39,7 @@ properties:
> - mediatek,mt8188-disp-color
> - mediatek,mt8192-disp-color
> - mediatek,mt8195-disp-color
> + - mediatek,mt8365-disp-color
> - const: mediatek,mt8173-disp-color
> reg:
> maxItems: 1
>
> --
> 2.25.1
>
>
On 24/10/2023 11:40, Chen-Yu Tsai wrote:
> On Mon, Oct 23, 2023 at 10:40 PM Alexandre Mergnat
> <[email protected]> wrote:
>>
>> Display Color for MT8365 is compatible with another SoC.
>> Then, add MT8365 binding along with MT8183 SoC.
>
> This unfortunately doesn't match what the patch is doing.
Yeah, I fixed it for v2.
>
> ChenYu
>
>> Signed-off-by: Alexandre Mergnat <[email protected]>
>> ---
>> Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
>> index f21e44092043..fbf15242af52 100644
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
>> @@ -39,6 +39,7 @@ properties:
>> - mediatek,mt8188-disp-color
>> - mediatek,mt8192-disp-color
>> - mediatek,mt8195-disp-color
>> + - mediatek,mt8365-disp-color
>> - const: mediatek,mt8173-disp-color
>> reg:
>> maxItems: 1
>>
>> --
>> 2.25.1
>>
>>
--
Regards,
Alexandre
On Mon, Oct 23, 2023 at 04:40:05PM +0200, Alexandre Mergnat wrote:
> Display Serial Interface for MT8365 is compatible with another SoC.
> Then, add MT8365 binding along with MT8183 SoC.
>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> index 12441b937684..2479b9e4abd2 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> @@ -34,6 +34,8 @@ properties:
> - enum:
> - mediatek,mt6795-dsi
> - const: mediatek,mt8173-dsi
> + - mediatek,mt8365-dsi
Not valid YAML nor json-schema. Please test your series before sending.
> + - const: mediatek,mt8183-dsi
>
> reg:
> maxItems: 1
>
> --
> 2.25.1
>
On 24/10/2023 22:30, Rob Herring wrote:
> On Mon, Oct 23, 2023 at 04:40:05PM +0200, Alexandre Mergnat wrote:
>> Display Serial Interface for MT8365 is compatible with another SoC.
>> Then, add MT8365 binding along with MT8183 SoC.
>>
>> Signed-off-by: Alexandre Mergnat <[email protected]>
>> ---
>> Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
>> index 12441b937684..2479b9e4abd2 100644
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
>> @@ -34,6 +34,8 @@ properties:
>> - enum:
>> - mediatek,mt6795-dsi
>> - const: mediatek,mt8173-dsi
>> + - mediatek,mt8365-dsi
>
> Not valid YAML nor json-schema. Please test your series before sending.
The serie has been successfully tested with the 2 following command
before being sent:
make DT_CHECKER_FLAGS=-m dt_binding_check DT_SCHEMA_FILES=mediatek,dsi.yaml
dt-validate -s Documentation/devicetree/bindings
arch/arm64/boot/dts/mediatek/mt8365-evk.dtb
I made a rebase error, that will be fixed for the next revision thanks.
>
>> + - const: mediatek,mt8183-dsi
>>
>> reg:
>> maxItems: 1
>>
>> --
>> 2.25.1
>>
--
Regards,
Alexandre
Hello,
On Mon, Oct 23, 2023 at 11:44:11PM +0200, Uwe Kleine-K?nig wrote:
> On Mon, Oct 23, 2023 at 04:40:12PM +0200, Alexandre Mergnat wrote:
> > Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
> > along with MT8183 SoC.
> >
> > Signed-off-by: Alexandre Mergnat <[email protected]>
>
> Acked-by: Uwe Kleine-K?nig <[email protected]>
>
> What is the merge plan here? Should the whole series go in via drm?
I'll assume that Alexandre will send out a new round of this series and
this patch isn't supposed to be applied as is to the pwm tree. So I'm
marking this patch as "changes requested" in our patchwork.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On 24/10/2023 11:12, AngeloGioacchino Del Regno wrote:
> Il 23/10/23 16:40, [email protected] ha scritto:
>> From: Fabien Parent <[email protected]>
>>
>> MT8365 requires an additional clock for DPI. Add support for that
>> additional clock.
>>
>> Signed-off-by: Fabien Parent <[email protected]>
>> Signed-off-by: Alexandre Mergnat <[email protected]>
>
> I'm not convinced that this is right... at all.
>
> From a fast check of the MT8365 DPI clocks, I can see that the DPI0
> clock declares
> parent VPLL_DPIX (a fixed clock), but nothing ever has VPLL_DPIX_EN
> (which is the
> GATE clock, enabling output of DPIx VPLL?).
>
> But then, there's even more: no clock ever references the
> CLK_TOP_DPI0_SEL nor the
> CLK_TOP_DPI1_SEL gate, which is a PLL parent selector... in other
> platforms, that
> is muxing through the TVDPLL, but on MT8365 that is LVDSPLL?!
AFAI see into mt8365 documentation, there is no TVDPLL, only LVDSPLL
>
> I have many questions now:
> * Two PLLs are apparently brought up, but which one is the right one?!
> * Is the LVDS PLL really used for DisplayPort? (dpi0_sel)
Seems to be LVDS
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
clk26m 18 19 1 26000000 0 0 Y
vpll_dpix 1 1 0 75000000 0 0 50000 Y
mm_flvdstx_pxl 0 0 0 75000000 0 0 50000 N
mm_dpi0_dpi0 1 1 0 75000000 0 0 50000 Y
vpll_dpix_en 0 0 0 75000000 0 0 50000 N
lvdspll 1 1 0 283999497 0 0 50000 Y
lvdspll_d16 0 0 0 17749968 0 0 50000 Y
lvdspll_d8 0 0 0 35499937 0 0 50000 Y
lvdspll_d4 0 0 0 70999874 0 0 50000 Y
lvdspll_d2 1 1 0 141999748 0 0 50000 Y
dpi0_sel 1 1 0 141999748 0 0 50000 Y
dpi1_sel 0 0 0 141999748 0 0 50000 N
mmpll 1 1 0 456999909 0 0 50000 Y
mmpll_ck 1 1 0 456999909 0 0 50000 Y
mm_sel 15 15 0 456999909 0 0 50000 Y
mm_dpi0 1 1 0 456999909 0 0 50000 Y
> * Are you sure that CLK_MM_DPI0_DPI0's parent shouldn't be dpi0_sel
> instead?
I'm agree with you. After few change, it works.
- GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
+ GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20),
- clocks = <&topckgen CLK_TOP_DPI0_SEL>,
+ clocks = <&mmsys CLK_MM_DPI0_DPI0>,
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
vpll_dpix 0 0 0 75000000 0 0 50000 Y
mm_flvdstx_pxl 0 0 0 75000000 0 0 50000 N
vpll_dpix_en 0 0 0 75000000 0 0 50000 N
lvdspll 1 1 0 283999497 0 0 50000 Y
lvdspll_d16 0 0 0 17749968 0 0 50000 Y
lvdspll_d8 0 0 0 35499937 0 0 50000 Y
lvdspll_d4 0 0 0 70999874 0 0 50000 Y
lvdspll_d2 1 1 0 141999748 0 0 50000 Y
dpi0_sel 1 1 0 141999748 0 0 50000 Y
mm_dpi0_dpi0 1 1 0 141999748 0 0 50000 Y
dpi1_sel 0 0 0 141999748 0 0 50000 N
mmpll 1 1 0 456999909 0 0 50000 Y
mmpll_d2 0 0 0 228499954 0 0 50000 Y
mmpll_ck 1 1 0 456999909 0 0 50000 Y
mm_sel 15 15 0 456999909 0 0 50000 Y
mm_dpi0 1 1 0 456999909 0 0 50000 Y
> * Where is DPI1 in this SoC? Why is there a dpi1_sel clock, but no MM clock
> for the DPI1 controller? Is there any DPI1 controller, even?!
DPI1 isn't documented.
> * Why is there a DPI1 MUX, if there's no DPI1 controller?!
Good question, I don't know. Legacy of the downstream code.
That will be fixed for the next version.
--
Regards,
Alexandre