From: Guo Ren <[email protected]>
The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
The patch implement basic context switch, sigcontext save/restore and
ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
is implemented. We need to discuss about vlen-size for libc sigcontext and
ptrace (the maximum size of vlen is unlimited in spec).
Puzzle:
Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
before, and riscv also met vlen size problem. Let's discuss the common issue
for all architectures and we need a better solution for unlimited vlen.
Any help are welcomed :)
1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html
---
Changelog V3
- Rebase linux-5.6-rc3 and tested with qemu
- Seperate patches with Anup's advice
- Give out a ABI puzzle with unlimited vlen
Changelog V2
- Fixup typo "vecotr, fstate_save->vstate_save".
- Fixup wrong saved registers' length in vector.S.
- Seperate unrelated patches from this one.
Guo Ren (11):
riscv: Separate patch for cflags and aflags
riscv: Rename __switch_to_aux -> fpu
riscv: Extending cpufeature.c to detect V-extension
riscv: Add CSR defines related to VECTOR extension
riscv: Add vector feature to compile
riscv: Add has_vector detect
riscv: Reset vector register
riscv: Add vector struct and assembler definitions
riscv: Add task switch support for VECTOR
riscv: Add ptrace support
riscv: Add sigcontext save/restore
arch/riscv/Kconfig | 9 ++
arch/riscv/Makefile | 19 ++-
arch/riscv/include/asm/csr.h | 17 ++-
arch/riscv/include/asm/processor.h | 1 +
arch/riscv/include/asm/switch_to.h | 54 ++++++-
arch/riscv/include/uapi/asm/elf.h | 1 +
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/ptrace.h | 9 ++
arch/riscv/include/uapi/asm/sigcontext.h | 1 +
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/asm-offsets.c | 187 +++++++++++++++++++++++
arch/riscv/kernel/cpufeature.c | 12 +-
arch/riscv/kernel/entry.S | 2 +-
arch/riscv/kernel/head.S | 49 +++++-
arch/riscv/kernel/process.c | 10 ++
arch/riscv/kernel/ptrace.c | 41 +++++
arch/riscv/kernel/signal.c | 40 +++++
arch/riscv/kernel/vector.S | 84 ++++++++++
include/uapi/linux/elf.h | 1 +
19 files changed, 524 insertions(+), 15 deletions(-)
create mode 100644 arch/riscv/kernel/vector.S
--
2.17.0
From: Guo Ren <[email protected]>
From: Guo Ren <[email protected]>
Use "subst fd" in Makefile is a hack way and it's not convenient
to add new ISA feature. Just separate them into riscv-march-cflags
and riscv-march-aflags.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/Makefile | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index b9009a2fbaf5..6d09b53cf106 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -35,12 +35,18 @@ else
endif
# ISA string setting
-riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
-riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
-riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
-riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
-KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
-KBUILD_AFLAGS += -march=$(riscv-march-y)
+riscv-march-cflags-$(CONFIG_ARCH_RV32I) := rv32ima
+riscv-march-cflags-$(CONFIG_ARCH_RV64I) := rv64ima
+riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
+riscv-march-cflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-cflags-y)c
+
+riscv-march-aflags-$(CONFIG_ARCH_RV32I) := rv32ima
+riscv-march-aflags-$(CONFIG_ARCH_RV64I) := rv64ima
+riscv-march-aflags-$(CONFIG_FPU) := $(riscv-march-aflags-y)fd
+riscv-march-aflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-aflags-y)c
+
+KBUILD_CFLAGS += -march=$(riscv-march-cflags-y)
+KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
KBUILD_CFLAGS += -mno-save-restore
KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
--
2.17.0
From: Guo Ren <[email protected]>
From: Guo Ren <[email protected]>
The name of __switch_to_aux is not clear and rename it with the
determine function: __switch_to_fpu. Next we could add other regs'
switch.
Signed-off-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
---
arch/riscv/include/asm/switch_to.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 407bcc96a710..b9234e7178d0 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -44,7 +44,7 @@ static inline void fstate_restore(struct task_struct *task,
}
}
-static inline void __switch_to_aux(struct task_struct *prev,
+static inline void __switch_to_fpu(struct task_struct *prev,
struct task_struct *next)
{
struct pt_regs *regs;
@@ -60,7 +60,7 @@ extern bool has_fpu;
#define has_fpu false
#define fstate_save(task, regs) do { } while (0)
#define fstate_restore(task, regs) do { } while (0)
-#define __switch_to_aux(__prev, __next) do { } while (0)
+#define __switch_to_fpu(__prev, __next) do { } while (0)
#endif
extern struct task_struct *__switch_to(struct task_struct *,
@@ -71,7 +71,7 @@ do { \
struct task_struct *__prev = (prev); \
struct task_struct *__next = (next); \
if (has_fpu) \
- __switch_to_aux(__prev, __next); \
+ __switch_to_fpu(__prev, __next); \
((last) = __switch_to(__prev, __next)); \
} while (0)
--
2.17.0
From: Guo Ren <[email protected]>
From: Guo Ren <[email protected]>
Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.
Signed-off-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
---
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index dee98ee28318..a913e9a38819 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))
#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a5ad00043104..c8527d770c98 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -30,6 +30,7 @@ void riscv_fill_hwcap(void)
isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+ isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
elf_hwcap = 0;
@@ -44,7 +45,8 @@ void riscv_fill_hwcap(void)
continue;
}
- for (i = 0; i < strlen(isa); ++i)
+ /* Skip rv64/rv32 to support v/V:vector */
+ for (i = 4; i < strlen(isa); ++i)
this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
/*
--
2.17.0
From: Guo Ren <[email protected]>
Follow the spec to define the regs' bits and regs' number.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/include/asm/csr.h | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 435b65532e29..49b93b638680 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -24,6 +24,12 @@
#define SR_FS_CLEAN _AC(0x00004000, UL)
#define SR_FS_DIRTY _AC(0x00006000, UL)
+#define SR_VS _AC(0x01800000, UL) /* Vector Status */
+#define SR_VS_OFF _AC(0x00000000, UL)
+#define SR_VS_INITIAL _AC(0x00800000, UL)
+#define SR_VS_CLEAN _AC(0x01000000, UL)
+#define SR_VS_DIRTY _AC(0x01800000, UL)
+
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
#define SR_XS_OFF _AC(0x00000000, UL)
#define SR_XS_INITIAL _AC(0x00008000, UL)
@@ -31,9 +37,9 @@
#define SR_XS_DIRTY _AC(0x00018000, UL)
#ifndef CONFIG_64BIT
-#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
+#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
#else
-#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
+#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
#endif
/* SATP flags */
@@ -102,6 +108,13 @@
#define CSR_MIP 0x344
#define CSR_MHARTID 0xf14
+#define CSR_VSTART 0x8
+#define CSR_VXSAT 0x9
+#define CSR_VXRM 0xa
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
+
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE
--
2.17.0
From: Guo Ren <[email protected]>
This patch add a config option which could enable assembler's
vector feature.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/Kconfig | 9 +++++++++
arch/riscv/Makefile | 1 +
2 files changed, 10 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 73f029eae0cc..c36589c85700 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -288,6 +288,15 @@ config FPU
If you don't know what to do here, say Y.
+config VECTOR
+ bool "VECTOR support"
+ default n
+ help
+ Say N here if you want to disable all vector related procedure
+ in the kernel.
+
+ If you don't know what to do here, say Y.
+
endmenu
menu "Kernel features"
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6d09b53cf106..071eb1148e01 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -44,6 +44,7 @@ riscv-march-aflags-$(CONFIG_ARCH_RV32I) := rv32ima
riscv-march-aflags-$(CONFIG_ARCH_RV64I) := rv64ima
riscv-march-aflags-$(CONFIG_FPU) := $(riscv-march-aflags-y)fd
riscv-march-aflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-aflags-y)c
+riscv-march-aflags-$(CONFIG_VECTOR) := $(riscv-march-aflags-y)v
KBUILD_CFLAGS += -march=$(riscv-march-cflags-y)
KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
--
2.17.0
From: Guo Ren <[email protected]>
This patch is to detect "has_vector" at time of CPU feature
parsing.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/kernel/cpufeature.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c8527d770c98..c9ab24e3c79e 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -16,6 +16,9 @@ unsigned long elf_hwcap __read_mostly;
#ifdef CONFIG_FPU
bool has_fpu __read_mostly;
#endif
+#ifdef CONFIG_VECTOR
+bool has_vector __read_mostly;
+#endif
void riscv_fill_hwcap(void)
{
@@ -73,4 +76,9 @@ void riscv_fill_hwcap(void)
if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
has_fpu = true;
#endif
+
+#ifdef CONFIG_VECTOR
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V)
+ has_vector = true;
+#endif
}
--
2.17.0
From: Guo Ren <[email protected]>
This patch add sigcontext save/restore and it's very similar to
fpu.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/include/uapi/asm/sigcontext.h | 1 +
arch/riscv/kernel/signal.c | 40 ++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h
index 84f2dfcfdbce..f74b3c814423 100644
--- a/arch/riscv/include/uapi/asm/sigcontext.h
+++ b/arch/riscv/include/uapi/asm/sigcontext.h
@@ -17,6 +17,7 @@
struct sigcontext {
struct user_regs_struct sc_regs;
union __riscv_fp_state sc_fpregs;
+ struct __riscv_v_state sc_vregs;
};
#endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index 17ba190e84a5..4295c00e8934 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -83,6 +83,40 @@ static long save_fp_state(struct pt_regs *regs,
#define restore_fp_state(task, regs) (0)
#endif
+#ifdef CONFIG_VECTOR
+static long restore_v_state(struct pt_regs *regs,
+ struct __riscv_v_state *sc_vregs)
+{
+ long err;
+ struct __riscv_v_state __user *state = sc_vregs;
+
+ err = __copy_from_user(¤t->thread.vstate, state, sizeof(*state));
+ if (unlikely(err))
+ return err;
+
+ vstate_restore(current, regs);
+
+ return err;
+}
+
+static long save_v_state(struct pt_regs *regs,
+ struct __riscv_v_state *sc_vregs)
+{
+ long err;
+ struct __riscv_v_state __user *state = sc_vregs;
+
+ vstate_save(current, regs);
+ err = __copy_to_user(state, ¤t->thread.vstate, sizeof(*state));
+ if (unlikely(err))
+ return err;
+
+ return err;
+}
+#else
+#define save_v_state(task, regs) (0)
+#define restore_v_state(task, regs) (0)
+#endif
+
static long restore_sigcontext(struct pt_regs *regs,
struct sigcontext __user *sc)
{
@@ -92,6 +126,9 @@ static long restore_sigcontext(struct pt_regs *regs,
/* Restore the floating-point state. */
if (has_fpu)
err |= restore_fp_state(regs, &sc->sc_fpregs);
+ /* Restore the vector state. */
+ if (has_vector)
+ err |= restore_v_state(regs, &sc->sc_vregs);
return err;
}
@@ -145,6 +182,9 @@ static long setup_sigcontext(struct rt_sigframe __user *frame,
/* Save the floating-point state. */
if (has_fpu)
err |= save_fp_state(regs, &sc->sc_fpregs);
+ /* Save the vector state. */
+ if (has_vector)
+ err |= save_v_state(regs, &sc->sc_vregs);
return err;
}
--
2.17.0
From: Guo Ren <[email protected]>
This patch add task switch and task create for VECTOR, and now
the applications with vector instructions wouldn't be broken by
linux task switch.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/include/asm/switch_to.h | 48 +++++++++++++++++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/process.c | 10 ++++
arch/riscv/kernel/vector.S | 84 ++++++++++++++++++++++++++++++
4 files changed, 143 insertions(+)
create mode 100644 arch/riscv/kernel/vector.S
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index b9234e7178d0..6e1c7fa599be 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -63,6 +63,52 @@ extern bool has_fpu;
#define __switch_to_fpu(__prev, __next) do { } while (0)
#endif
+#ifdef CONFIG_VECTOR
+extern void __vstate_save(struct task_struct *save_to);
+extern void __vstate_restore(struct task_struct *restore_from);
+
+static inline void __vstate_clean(struct pt_regs *regs)
+{
+ regs->status |= (regs->status & ~(SR_VS)) | SR_VS_CLEAN;
+}
+
+static inline void vstate_save(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ if ((regs->status & SR_VS) == SR_VS_DIRTY) {
+ __vstate_save(task);
+ __vstate_clean(regs);
+ }
+}
+
+static inline void vstate_restore(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ if ((regs->status & SR_VS) != SR_VS_OFF) {
+ __vstate_restore(task);
+ __vstate_clean(regs);
+ }
+}
+
+static inline void __switch_to_vector(struct task_struct *prev,
+ struct task_struct *next)
+{
+ struct pt_regs *regs;
+
+ regs = task_pt_regs(prev);
+ if (unlikely(regs->status & SR_SD))
+ vstate_save(prev, regs);
+ vstate_restore(next, task_pt_regs(next));
+}
+
+extern bool has_vector;
+#else
+#define has_vector false
+#define vstate_save(task, regs) do { } while (0)
+#define vstate_restore(task, regs) do { } while (0)
+#define __switch_to_vector(__prev, __next) do { } while (0)
+#endif
+
extern struct task_struct *__switch_to(struct task_struct *,
struct task_struct *);
@@ -72,6 +118,8 @@ do { \
struct task_struct *__next = (next); \
if (has_fpu) \
__switch_to_fpu(__prev, __next); \
+ if (has_vector) \
+ __switch_to_vector(__prev, __next); \
((last) = __switch_to(__prev, __next)); \
} while (0)
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index f40205cb9a22..e5276c3bdffc 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
obj-$(CONFIG_RISCV_M_MODE) += clint.o
obj-$(CONFIG_FPU) += fpu.o
+obj-$(CONFIG_VECTOR) += vector.o
obj-$(CONFIG_SMP) += smpboot.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 817cf7b0974c..c572557701b4 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -74,6 +74,16 @@ void start_thread(struct pt_regs *regs, unsigned long pc,
*/
fstate_restore(current, regs);
}
+
+ if (has_vector) {
+ regs->status |= SR_VS_INITIAL;
+ /*
+ * Restore the initial value to the vector register
+ * before starting the user program.
+ */
+ vstate_restore(current, regs);
+ }
+
regs->epc = pc;
regs->sp = sp;
set_fs(USER_DS);
diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S
new file mode 100644
index 000000000000..dbe1989fa9d7
--- /dev/null
+++ b/arch/riscv/kernel/vector.S
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ * Copyright (C) 2019 Alibaba Group Holding Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/asm.h>
+#include <asm/csr.h>
+#include <asm/asm-offsets.h>
+
+ENTRY(__vstate_save)
+ li a2, TASK_THREAD_V0
+ add a0, a0, a2
+
+ li t1, (SR_VS | SR_FS)
+ csrs sstatus, t1
+
+ csrr t0, CSR_VSTART
+ sd t0, TASK_THREAD_VSTART_V0(a0)
+ csrr t0, CSR_VXSAT
+ sd t0, TASK_THREAD_VXSAT_V0(a0)
+ csrr t0, CSR_VXRM
+ sd t0, TASK_THREAD_VXRM_V0(a0)
+ csrr t0, CSR_VL
+ sd t0, TASK_THREAD_VL_V0(a0)
+ csrr t0, CSR_VTYPE
+ sd t0, TASK_THREAD_VTYPE_V0(a0)
+
+ vsetvli t0, x0, e8,m8
+ vsb.v v0, (a0)
+ addi a0, a0, 128*8
+ vsb.v v8, (a0)
+ addi a0, a0, 128*8
+ vsb.v v16, (a0)
+ addi a0, a0, 128*8
+ vsb.v v24, (a0)
+
+ csrc sstatus, t1
+ ret
+ENDPROC(__vstate_save)
+
+ENTRY(__vstate_restore)
+ li a2, TASK_THREAD_V0
+ add a0, a0, a2
+ mv t2, a0
+
+ li t1, (SR_VS | SR_FS)
+ csrs sstatus, t1
+
+ vsetvli t0, x0, e8,m8
+ vlb.v v0, (a0)
+ addi a0, a0, 128*8
+ vlb.v v8, (a0)
+ addi a0, a0, 128*8
+ vlb.v v16, (a0)
+ addi a0, a0, 128*8
+ vlb.v v24, (a0)
+
+ mv a0, t2
+ ld t0, TASK_THREAD_VSTART_V0(a0)
+ csrw CSR_VSTART, t0
+ ld t0, TASK_THREAD_VXSAT_V0(a0)
+ csrw CSR_VXSAT, t0
+ ld t0, TASK_THREAD_VXRM_V0(a0)
+ csrw CSR_VXRM, t0
+ ld t0, TASK_THREAD_VL_V0(a0)
+ ld t2, TASK_THREAD_VTYPE_V0(a0)
+ vsetvl t0, t0, t2
+
+ csrc sstatus, t1
+ ret
+ENDPROC(__vstate_restore)
--
2.17.0
From: Guo Ren <[email protected]>
Add new regset for vector and the implementation is similar to
fpu.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/include/uapi/asm/elf.h | 1 +
arch/riscv/kernel/ptrace.c | 41 +++++++++++++++++++++++++++++++
include/uapi/linux/elf.h | 1 +
3 files changed, 43 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h
index d696d6610231..099434d075a7 100644
--- a/arch/riscv/include/uapi/asm/elf.h
+++ b/arch/riscv/include/uapi/asm/elf.h
@@ -23,6 +23,7 @@ typedef struct user_regs_struct elf_gregset_t;
typedef __u64 elf_fpreg_t;
typedef union __riscv_fp_state elf_fpregset_t;
#define ELF_NFPREG (sizeof(struct __riscv_d_ext_state) / sizeof(elf_fpreg_t))
+#define ELF_NVREG (sizeof(struct __riscv_v_state) / sizeof(elf_greg_t))
#if __riscv_xlen == 64
#define ELF_RISCV_R_SYM(r_info) ELF64_R_SYM(r_info)
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index 407464201b91..0e3c3543476c 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -26,6 +26,9 @@ enum riscv_regset {
#ifdef CONFIG_FPU
REGSET_F,
#endif
+#ifdef CONFIG_VECTOR
+ REGSET_V,
+#endif
};
static int riscv_gpr_get(struct task_struct *target,
@@ -92,6 +95,34 @@ static int riscv_fpr_set(struct task_struct *target,
}
#endif
+#ifdef CONFIG_VECTOR
+static int riscv_vr_get(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ void *kbuf, void __user *ubuf)
+{
+ int ret;
+ struct __riscv_v_state *vstate = &target->thread.vstate;
+
+ ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, vstate, 0,
+ offsetof(struct __riscv_v_state, vtype));
+ return ret;
+}
+
+static int riscv_vr_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ int ret;
+ struct __riscv_v_state *vstate = &target->thread.vstate;
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0,
+ offsetof(struct __riscv_v_state, vtype));
+ return ret;
+}
+#endif
+
static const struct user_regset riscv_user_regset[] = {
[REGSET_X] = {
.core_note_type = NT_PRSTATUS,
@@ -111,6 +142,16 @@ static const struct user_regset riscv_user_regset[] = {
.set = &riscv_fpr_set,
},
#endif
+#ifdef CONFIG_VECTOR
+ [REGSET_V] = {
+ .core_note_type = NT_RISCV_VECTOR,
+ .n = ELF_NVREG,
+ .size = sizeof(elf_greg_t),
+ .align = sizeof(elf_greg_t),
+ .get = &riscv_vr_get,
+ .set = &riscv_vr_set,
+ },
+#endif
};
static const struct user_regset_view riscv_user_native_view = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 34c02e4290fe..e428f9e8710a 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -428,6 +428,7 @@ typedef struct elf64_shdr {
#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */
#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */
#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
+#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */
/* Note header in a PT_NOTE section */
typedef struct elf32_note {
--
2.17.0
From: Guo Ren <[email protected]>
Add vector state context struct in struct thread and asm-offsets.c
definitions.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/include/asm/processor.h | 1 +
arch/riscv/include/uapi/asm/ptrace.h | 9 ++
arch/riscv/kernel/asm-offsets.c | 187 +++++++++++++++++++++++++++
3 files changed, 197 insertions(+)
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 3ddb798264f1..217273375cfb 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -32,6 +32,7 @@ struct thread_struct {
unsigned long sp; /* Kernel mode stack */
unsigned long s[12]; /* s[0]: frame pointer */
struct __riscv_d_ext_state fstate;
+ struct __riscv_v_state vstate;
};
#define INIT_THREAD { \
diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h
index 882547f6bd5c..d913e8949b87 100644
--- a/arch/riscv/include/uapi/asm/ptrace.h
+++ b/arch/riscv/include/uapi/asm/ptrace.h
@@ -71,6 +71,15 @@ struct __riscv_q_ext_state {
__u32 reserved[3];
};
+struct __riscv_v_state {
+ __uint128_t v[32];
+ unsigned long vstart;
+ unsigned long vxsat;
+ unsigned long vxrm;
+ unsigned long vl;
+ unsigned long vtype;
+};
+
union __riscv_fp_state {
struct __riscv_f_ext_state f;
struct __riscv_d_ext_state d;
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
index 07cb9c10de4e..ab6eae41c2ad 100644
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
@@ -70,6 +70,44 @@ void asm_offsets(void)
OFFSET(TASK_THREAD_F31, task_struct, thread.fstate.f[31]);
OFFSET(TASK_THREAD_FCSR, task_struct, thread.fstate.fcsr);
+ OFFSET(TASK_THREAD_V0, task_struct, thread.vstate.v[0]);
+ OFFSET(TASK_THREAD_V1, task_struct, thread.vstate.v[1]);
+ OFFSET(TASK_THREAD_V2, task_struct, thread.vstate.v[2]);
+ OFFSET(TASK_THREAD_V3, task_struct, thread.vstate.v[3]);
+ OFFSET(TASK_THREAD_V4, task_struct, thread.vstate.v[4]);
+ OFFSET(TASK_THREAD_V5, task_struct, thread.vstate.v[5]);
+ OFFSET(TASK_THREAD_V6, task_struct, thread.vstate.v[6]);
+ OFFSET(TASK_THREAD_V7, task_struct, thread.vstate.v[7]);
+ OFFSET(TASK_THREAD_V8, task_struct, thread.vstate.v[8]);
+ OFFSET(TASK_THREAD_V9, task_struct, thread.vstate.v[9]);
+ OFFSET(TASK_THREAD_V10, task_struct, thread.vstate.v[10]);
+ OFFSET(TASK_THREAD_V11, task_struct, thread.vstate.v[11]);
+ OFFSET(TASK_THREAD_V12, task_struct, thread.vstate.v[12]);
+ OFFSET(TASK_THREAD_V13, task_struct, thread.vstate.v[13]);
+ OFFSET(TASK_THREAD_V14, task_struct, thread.vstate.v[14]);
+ OFFSET(TASK_THREAD_V15, task_struct, thread.vstate.v[15]);
+ OFFSET(TASK_THREAD_V16, task_struct, thread.vstate.v[16]);
+ OFFSET(TASK_THREAD_V17, task_struct, thread.vstate.v[17]);
+ OFFSET(TASK_THREAD_V18, task_struct, thread.vstate.v[18]);
+ OFFSET(TASK_THREAD_V19, task_struct, thread.vstate.v[19]);
+ OFFSET(TASK_THREAD_V20, task_struct, thread.vstate.v[20]);
+ OFFSET(TASK_THREAD_V21, task_struct, thread.vstate.v[21]);
+ OFFSET(TASK_THREAD_V22, task_struct, thread.vstate.v[22]);
+ OFFSET(TASK_THREAD_V23, task_struct, thread.vstate.v[23]);
+ OFFSET(TASK_THREAD_V24, task_struct, thread.vstate.v[24]);
+ OFFSET(TASK_THREAD_V25, task_struct, thread.vstate.v[25]);
+ OFFSET(TASK_THREAD_V26, task_struct, thread.vstate.v[26]);
+ OFFSET(TASK_THREAD_V27, task_struct, thread.vstate.v[27]);
+ OFFSET(TASK_THREAD_V28, task_struct, thread.vstate.v[28]);
+ OFFSET(TASK_THREAD_V29, task_struct, thread.vstate.v[29]);
+ OFFSET(TASK_THREAD_V30, task_struct, thread.vstate.v[30]);
+ OFFSET(TASK_THREAD_V31, task_struct, thread.vstate.v[31]);
+ OFFSET(TASK_THREAD_VSTART, task_struct, thread.vstate.vstart);
+ OFFSET(TASK_THREAD_VXSAT, task_struct, thread.vstate.vxsat);
+ OFFSET(TASK_THREAD_VXRM, task_struct, thread.vstate.vxrm);
+ OFFSET(TASK_THREAD_VL, task_struct, thread.vstate.vl);
+ OFFSET(TASK_THREAD_VTYPE, task_struct, thread.vstate.vtype);
+
DEFINE(PT_SIZE, sizeof(struct pt_regs));
OFFSET(PT_EPC, pt_regs, epc);
OFFSET(PT_RA, pt_regs, ra);
@@ -304,6 +342,155 @@ void asm_offsets(void)
- offsetof(struct task_struct, thread.fstate.f[0])
);
+ DEFINE(TASK_THREAD_V0_V0,
+ offsetof(struct task_struct, thread.vstate.v[0])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V1_V0,
+ offsetof(struct task_struct, thread.vstate.v[1])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V2_V0,
+ offsetof(struct task_struct, thread.vstate.v[2])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V3_V0,
+ offsetof(struct task_struct, thread.vstate.v[3])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V4_V0,
+ offsetof(struct task_struct, thread.vstate.v[4])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V5_V0,
+ offsetof(struct task_struct, thread.vstate.v[5])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V6_V0,
+ offsetof(struct task_struct, thread.vstate.v[6])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V7_V0,
+ offsetof(struct task_struct, thread.vstate.v[7])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V8_V0,
+ offsetof(struct task_struct, thread.vstate.v[8])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V9_V0,
+ offsetof(struct task_struct, thread.vstate.v[9])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V10_V0,
+ offsetof(struct task_struct, thread.vstate.v[10])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V11_V0,
+ offsetof(struct task_struct, thread.vstate.v[11])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V12_V0,
+ offsetof(struct task_struct, thread.vstate.v[12])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V13_V0,
+ offsetof(struct task_struct, thread.vstate.v[13])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V14_V0,
+ offsetof(struct task_struct, thread.vstate.v[14])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V15_V0,
+ offsetof(struct task_struct, thread.vstate.v[15])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V16_V0,
+ offsetof(struct task_struct, thread.vstate.v[16])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V17_V0,
+ offsetof(struct task_struct, thread.vstate.v[17])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V18_V0,
+ offsetof(struct task_struct, thread.vstate.v[18])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V19_V0,
+ offsetof(struct task_struct, thread.vstate.v[19])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V20_V0,
+ offsetof(struct task_struct, thread.vstate.v[20])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V21_V0,
+ offsetof(struct task_struct, thread.vstate.v[21])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V22_V0,
+ offsetof(struct task_struct, thread.vstate.v[22])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V23_V0,
+ offsetof(struct task_struct, thread.vstate.v[23])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V24_V0,
+ offsetof(struct task_struct, thread.vstate.v[24])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V25_V0,
+ offsetof(struct task_struct, thread.vstate.v[25])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V26_V0,
+ offsetof(struct task_struct, thread.vstate.v[26])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V27_V0,
+ offsetof(struct task_struct, thread.vstate.v[27])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V28_V0,
+ offsetof(struct task_struct, thread.vstate.v[28])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V29_V0,
+ offsetof(struct task_struct, thread.vstate.v[29])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V30_V0,
+ offsetof(struct task_struct, thread.vstate.v[30])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_V31_V0,
+ offsetof(struct task_struct, thread.vstate.v[31])
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_VSTART_V0,
+ offsetof(struct task_struct, thread.vstate.vstart)
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_VXSAT_V0,
+ offsetof(struct task_struct, thread.vstate.vxsat)
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_VXRM_V0,
+ offsetof(struct task_struct, thread.vstate.vxrm)
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_VL_V0,
+ offsetof(struct task_struct, thread.vstate.vl)
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+ DEFINE(TASK_THREAD_VTYPE_V0,
+ offsetof(struct task_struct, thread.vstate.vtype)
+ - offsetof(struct task_struct, thread.vstate.v[0])
+ );
+
/*
* We allocate a pt_regs on the stack when entering the kernel. This
* ensures the alignment is sane.
--
2.17.0
From: Guo Ren <[email protected]>
Reset vector registers at boot-time and disable vector instructions
execution for kernel mode.
Signed-off-by: Guo Ren <[email protected]>
---
arch/riscv/kernel/entry.S | 2 +-
arch/riscv/kernel/head.S | 49 +++++++++++++++++++++++++++++++++++++--
2 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index bad4d85b5e91..449e0a7ef115 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -76,7 +76,7 @@ _save_context:
* Disable the FPU to detect illegal usage of floating point in kernel
* space.
*/
- li t0, SR_SUM | SR_FS
+ li t0, SR_SUM | SR_FS | SR_VS
REG_L s0, TASK_TI_USER_SP(tp)
csrrc s1, CSR_STATUS, t0
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 271860fc2c3f..b40d8ec7ad5d 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -72,10 +72,10 @@ _start_kernel:
.option pop
/*
- * Disable FPU to detect illegal usage of
+ * Disable FPU & VECTOR to detect illegal usage of
* floating point in kernel space
*/
- li t0, SR_FS
+ li t0, SR_FS | SR_VS
csrc CSR_STATUS, t0
#ifdef CONFIG_SMP
@@ -290,6 +290,51 @@ ENTRY(reset_regs)
csrw fcsr, 0
/* note that the caller must clear SR_FS */
#endif /* CONFIG_FPU */
+
+#ifdef CONFIG_VECTOR
+ csrr t0, CSR_MISA
+ li t1, (COMPAT_HWCAP_ISA_V >> 16)
+ slli t1, t1, 16
+ and t0, t0, t1
+ beqz t0, .Lreset_regs_done
+
+ li t1, SR_VS
+ csrs CSR_STATUS, t1
+ vmv.v.i v0, 0
+ vmv.v.i v1, 0
+ vmv.v.i v2, 0
+ vmv.v.i v3, 0
+ vmv.v.i v4, 0
+ vmv.v.i v5, 0
+ vmv.v.i v6, 0
+ vmv.v.i v7, 0
+ vmv.v.i v8, 0
+ vmv.v.i v9, 0
+ vmv.v.i v10, 0
+ vmv.v.i v11, 0
+ vmv.v.i v12, 0
+ vmv.v.i v13, 0
+ vmv.v.i v14, 0
+ vmv.v.i v15, 0
+ vmv.v.i v16, 0
+ vmv.v.i v17, 0
+ vmv.v.i v18, 0
+ vmv.v.i v19, 0
+ vmv.v.i v20, 0
+ vmv.v.i v21, 0
+ vmv.v.i v22, 0
+ vmv.v.i v23, 0
+ vmv.v.i v24, 0
+ vmv.v.i v25, 0
+ vmv.v.i v26, 0
+ vmv.v.i v27, 0
+ vmv.v.i v28, 0
+ vmv.v.i v29, 0
+ vmv.v.i v30, 0
+ vmv.v.i v31, 0
+ /* note that the caller must clear SR_VS */
+#endif /* CONFIG_VECTOR */
+
.Lreset_regs_done:
ret
END(reset_regs)
--
2.17.0
On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:
>
> From: Guo Ren <[email protected]>
>
> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
>
> The patch implement basic context switch, sigcontext save/restore and
> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> is implemented. We need to discuss about vlen-size for libc sigcontext and
> ptrace (the maximum size of vlen is unlimited in spec).
>
> Puzzle:
> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> before, and riscv also met vlen size problem. Let's discuss the common issue
> for all architectures and we need a better solution for unlimited vlen.
>
> Any help are welcomed :)
>
> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
Hi Guo,
Thanks for your patch.
It seems the qemu repo doesn't have this branch?
On 2020/3/9 11:41, Greentime Hu wrote:
> On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:
>> From: Guo Ren <[email protected]>
>>
>> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
>> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
>>
>> The patch implement basic context switch, sigcontext save/restore and
>> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
>> is implemented. We need to discuss about vlen-size for libc sigcontext and
>> ptrace (the maximum size of vlen is unlimited in spec).
>>
>> Puzzle:
>> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
>> before, and riscv also met vlen size problem. Let's discuss the common issue
>> for all architectures and we need a better solution for unlimited vlen.
>>
>> Any help are welcomed :)
>>
>> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> Hi Guo,
>
> Thanks for your patch.
> It seems the qemu repo doesn't have this branch?
Hi Greentime,
It's a promise from me. Now it's ready. You can turn on vector by
"qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".
Zhiwei
On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei <[email protected]> wrote:
> On 2020/3/9 11:41, Greentime Hu wrote:
> > On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:
> >> From: Guo Ren <[email protected]>
> >>
> >> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> >> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
> >>
> >> The patch implement basic context switch, sigcontext save/restore and
> >> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> >> is implemented. We need to discuss about vlen-size for libc sigcontext and
> >> ptrace (the maximum size of vlen is unlimited in spec).
> >>
> >> Puzzle:
> >> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> >> before, and riscv also met vlen size problem. Let's discuss the common issue
> >> for all architectures and we need a better solution for unlimited vlen.
> >>
> >> Any help are welcomed :)
> >>
> >> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> > Hi Guo,
> >
> > Thanks for your patch.
> > It seems the qemu repo doesn't have this branch?
> Hi Greentime,
>
> It's a promise from me. Now it's ready. You can turn on vector by
> "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".
>
> Zhiwei
>
>
Hi Zhiwei,
Thank you, I see the branch in the repo now. I will give it a try and
let you know if I have any problem. :)
On Tue, Mar 10, 2020 at 4:54 PM Greentime Hu <[email protected]> wrote:
>
> On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei <[email protected]> wrote:
> > On 2020/3/9 11:41, Greentime Hu wrote:
> > > On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:
> > >> From: Guo Ren <[email protected]>
> > >>
> > >> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> > >> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
> > >>
> > >> The patch implement basic context switch, sigcontext save/restore and
> > >> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> > >> is implemented. We need to discuss about vlen-size for libc sigcontext and
> > >> ptrace (the maximum size of vlen is unlimited in spec).
> > >>
> > >> Puzzle:
> > >> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> > >> before, and riscv also met vlen size problem. Let's discuss the common issue
> > >> for all architectures and we need a better solution for unlimited vlen.
> > >>
> > >> Any help are welcomed :)
> > >>
> > >> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> > > Hi Guo,
> > >
> > > Thanks for your patch.
> > > It seems the qemu repo doesn't have this branch?
> > Hi Greentime,
> >
> > It's a promise from me. Now it's ready. You can turn on vector by
> > "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".
> >
> > Zhiwei
> >
> >
>
> Hi Zhiwei,
>
> Thank you, I see the branch in the repo now. I will give it a try and
> let you know if I have any problem. :)
Hi Zhiwei & Guo,
It seems current version only support v0.7.1 in qemu but this patchset
is verified in qemu too and it is based on 0.8.
Would you please provide the qemu with 0.8 vector spec supported? or
Did I miss something?
489 if (cpu->cfg.vext_spec) {
490 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
491 vext_version = VEXT_VERSION_0_07_1;
492 } else {
493 error_setg(errp,
494 "Unsupported vector spec version '%s'",
495 cpu->cfg.vext_spec);
496 return;
497 }
498 }
By the way, can I specify vlen in Qemu?
Thank you. :)
On 2020/3/10 17:19, Greentime Hu wrote:
> On Tue, Mar 10, 2020 at 4:54 PM Greentime Hu <[email protected]> wrote:
>> On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei <[email protected]> wrote:
>>> On 2020/3/9 11:41, Greentime Hu wrote:
>>>> On Sun, Mar 8, 2020 at 5:50 PM <[email protected]> wrote:
>>>>> From: Guo Ren <[email protected]>
>>>>>
>>>>> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
>>>>> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
>>>>>
>>>>> The patch implement basic context switch, sigcontext save/restore and
>>>>> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
>>>>> is implemented. We need to discuss about vlen-size for libc sigcontext and
>>>>> ptrace (the maximum size of vlen is unlimited in spec).
>>>>>
>>>>> Puzzle:
>>>>> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
>>>>> before, and riscv also met vlen size problem. Let's discuss the common issue
>>>>> for all architectures and we need a better solution for unlimited vlen.
>>>>>
>>>>> Any help are welcomed :)
>>>>>
>>>>> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
>>>> Hi Guo,
>>>>
>>>> Thanks for your patch.
>>>> It seems the qemu repo doesn't have this branch?
>>> Hi Greentime,
>>>
>>> It's a promise from me. Now it's ready. You can turn on vector by
>>> "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".
>>>
>>> Zhiwei
>>>
>>>
>> Hi Zhiwei,
>>
>> Thank you, I see the branch in the repo now. I will give it a try and
>> let you know if I have any problem. :)
> Hi Zhiwei & Guo,
>
> It seems current version only support v0.7.1 in qemu but this patchset
> is verified in qemu too and it is based on 0.8.
> Would you please provide the qemu with 0.8 vector spec supported?
Hi Greentime,
vector-upstream-v3 only supports v0.7.1. It is under reviewed in QEMU
community.
Maybe I will also support v0.8 after it is merged.
As Guo Ren said, the kernel patch set works both for v0.7.1 and v0.8,
which only uses the common instructions and CSRs.
> or
> Did I miss something?
>
> 489 if (cpu->cfg.vext_spec) {
> 490 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
> 491 vext_version = VEXT_VERSION_0_07_1;
> 492 } else {
> 493 error_setg(errp,
> 494 "Unsupported vector spec version '%s'",
> 495 cpu->cfg.vext_spec);
> 496 return;
> 497 }
> 498 }
>
> By the way, can I specify vlen in Qemu?
Yes, you can specify vlen through QEMU command line like
“-cpu rv64,v=true,vext_spec=v0.7.1,vlen=256”
Currently , vlen supports up to 512 bits, with a default value 128 bits.
> Thank you. :)
<[email protected]> 於 2020年3月8日 週日 下午5:50寫道：
>
> From: Guo Ren <[email protected]>
>
> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
>
> The patch implement basic context switch, sigcontext save/restore and
> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> is implemented. We need to discuss about vlen-size for libc sigcontext and
> ptrace (the maximum size of vlen is unlimited in spec).
>
> Puzzle:
> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> before, and riscv also met vlen size problem. Let's discuss the common issue
> for all architectures and we need a better solution for unlimited vlen.
>
> Any help are welcomed :)
>
> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html
>
Hi Ren,
Thanks for the patch. I have some ideas about the vlen and sigcontext.
Since vlen may not be fixed of each RISC-V cores and it could be super
big, it means we have to allocate the memory dynamically.
In kernel space, we may use a pointer in the context data structure.
Something like https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/fpsimd.c#L498
In user space, we need to let user space know the length of vector
registers. We may create a special header in sigcontext. Something
like https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L36
https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L127
For the implementation in makecontext, swapcontext, getcontext,
setcontext of glibc, we may not need to port because it seems to be
deprecated?
https://stackoverflow.com/questions/4298986/is-there-something-to-replace-the-ucontext-h-functions
For the unwinding implementation of libgcc since it needs to know the
meaning of data structure is changed. It also need to be port.
> ---
> Changelog V3
> - Rebase linux-5.6-rc3 and tested with qemu
> - Seperate patches with Anup's advice
> - Give out a ABI puzzle with unlimited vlen
>
> Changelog V2
> - Fixup typo "vecotr, fstate_save->vstate_save".
> - Fixup wrong saved registers' length in vector.S.
> - Seperate unrelated patches from this one.
>
> Guo Ren (11):
> riscv: Separate patch for cflags and aflags
> riscv: Rename __switch_to_aux -> fpu
> riscv: Extending cpufeature.c to detect V-extension
> riscv: Add CSR defines related to VECTOR extension
> riscv: Add vector feature to compile
> riscv: Add has_vector detect
> riscv: Reset vector register
> riscv: Add vector struct and assembler definitions
> riscv: Add task switch support for VECTOR
> riscv: Add ptrace support
> riscv: Add sigcontext save/restore
>
> arch/riscv/Kconfig | 9 ++
> arch/riscv/Makefile | 19 ++-
> arch/riscv/include/asm/csr.h | 17 ++-
> arch/riscv/include/asm/processor.h | 1 +
> arch/riscv/include/asm/switch_to.h | 54 ++++++-
> arch/riscv/include/uapi/asm/elf.h | 1 +
> arch/riscv/include/uapi/asm/hwcap.h | 1 +
> arch/riscv/include/uapi/asm/ptrace.h | 9 ++
> arch/riscv/include/uapi/asm/sigcontext.h | 1 +
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/asm-offsets.c | 187 +++++++++++++++++++++++
> arch/riscv/kernel/cpufeature.c | 12 +-
> arch/riscv/kernel/entry.S | 2 +-
> arch/riscv/kernel/head.S | 49 +++++-
> arch/riscv/kernel/process.c | 10 ++
> arch/riscv/kernel/ptrace.c | 41 +++++
> arch/riscv/kernel/signal.c | 40 +++++
> arch/riscv/kernel/vector.S | 84 ++++++++++
> include/uapi/linux/elf.h | 1 +
> 19 files changed, 524 insertions(+), 15 deletions(-)
> create mode 100644 arch/riscv/kernel/vector.S
>
> --
> 2.17.0
>
Hi Greentime,
On Mon, Mar 23, 2020 at 12:00 PM Greentime Hu <[email protected]> wrote:
>
> <[email protected]> 於 2020年3月8日 週日 下午5:50寫道：
> >
> > From: Guo Ren <[email protected]>
> >
> > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> > 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
> >
> > The patch implement basic context switch, sigcontext save/restore and
> > ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> > is implemented. We need to discuss about vlen-size for libc sigcontext and
> > ptrace (the maximum size of vlen is unlimited in spec).
> >
> > Puzzle:
> > Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> > before, and riscv also met vlen size problem. Let's discuss the common issue
> > for all architectures and we need a better solution for unlimited vlen.
> >
> > Any help are welcomed :)
> >
> > 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> > 2: https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html
> >
>
> Hi Ren,
>
> Thanks for the patch. I have some ideas about the vlen and sigcontext.
> Since vlen may not be fixed of each RISC-V cores and it could be super
> big, it means we have to allocate the memory dynamically.
> In kernel space, we may use a pointer in the context data structure.
> Something like https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/fpsimd.c#L498
> In user space, we need to let user space know the length of vector
> registers. We may create a special header in sigcontext. Something
> like https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L36
> https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/sigcontext.h#L127
As you've mentioned codes above, arm64 use a fixed pre-allocate
sigcontext with a large space:
struct sigcontext {
__u64 fault_address;
/* AArch64 registers */
__u64 regs[31];
__u64 sp;
__u64 pc;
__u64 pstate;
/* 4K reserved for FP/SIMD state and future expansion */
__u8 __reserved[4096] __attribute__((__aligned__(16)));
};
There are several contexts in the space above: fpsimd, esr, sve, extra
__reserved[4096]:
* 0x210 fpsimd_context
* 0x10 esr_context
* 0x8a0 sve_context (vl <= 64) (optional)
* 0x20 extra_context (optional)
* 0x10 terminator (null _aarch64_ctx)
* 0x510 (reserved for future allocation)
0x210 + 0x10 + 0x8a0 + 0x20 + 0x10 + 0x510 = 4096
The max vl is 64 in arm sve, but for riscv want an unlimited size
solution and more extensible/flexible solution, such as dynamic
allocating user-space context with hwinfo. But there is no ref
solution around all arches.
There is a choice puzzle for me:
1) A pre-allocated&limited reserved size of sigcontext, the solution
has been practiced and we just need to determine the size.
2) Dynamically allocated/unlimited size of sigcontext, but may deal
with glibc, libgcc infrastructure on abi view.
Before the next stage of work, we need to choose the direction and
it's also a common puzzle for all architectures with extending
vector/simd like co-processor solutions.
ps:
Have a look on Dave's patch, he just follow the arm64 fixed
pre-allocate limited sigcontext infrastructure:
(I don't think it's a proper example for riscv vector design.)
commit d0b8cd3187889476144bd9b13bf36a932c3e7952
Author: Dave Martin <[email protected]>
Date: Tue Oct 31 15:51:03 2017 +0000
arm64/sve: Signal frame and context structure definition
>
> For the implementation in makecontext, swapcontext, getcontext,
> setcontext of glibc, we may not need to port because it seems to be
> deprecated?
> https://stackoverflow.com/questions/4298986/is-there-something-to-replace-the-ucontext-h-functions
Agree, we needn't deal with them at beginning.
>
> For the unwinding implementation of libgcc since it needs to know the
> meaning of data structure is changed. It also need to be port.
Yes, it'll break the abi and such as the elf with -fexception compiled
will be broken.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/