2015-06-08 10:40:24

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 0/8] ARM64: juno: add SCPI mailbox protocol, clock and CPUFreq support

Hi,

This patch series adds support for:
1. SCPI(System Control and Power Interface) mailbox protocol driver.
It uses ARM MHU mailbox controller driver on Juno but can work with
any mailbox controllers using standard mailbox APIs
2. Add support for clocks provided by SCP firmware through the SCPI
interface
3. Using the existing arm_big_little cpufreq driver and the newly
added SCPI clock driver, it also adds support for CPU DVFS on
ARM64 JUNO development platforms.

The SCPI protocol document is available @[1],[2]

Changes v3->v4:
- Updated the SCPI binding based on MarkR's feedback
- Updated SCPI clock driver to incorporate Stephen Boyd's review
comments + used clk_set_rate_range to limit the clock range
- Since no major changes are expected in SCPI DT, updated the
Juno DTS to support SCPI and dependent device nodes. The DT
patches are based on Liviu's recent Juno[3]

Changes v2->v3:
- Minor fix in SCPI driver and added Tixy's reviewed-by tag
- Updated scpi clock driver to incorporate all the comments from
Stephen
- Added Viresh's ack

Changes v1->v2:
- Updated the token handling in scpi driver as per Tixy's
suggestion along with other review comments
- Removed multiple drivers in scpi clock as Lorenzo suggested
- Added free_opp_table in scpi-cpufreq as Viresh suggested
- Separated the DT binding document
- Moved SCPI protocol driver to drivers/firmware

Regards,
Sudeep

[1] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf
[2] https://wiki.linaro.org/ARM/Juno?action=AttachFile&do=get&target=DUI0922B_scp_message_interface.pdf
[3] http://www.spinics.net/lists/arm-kernel/msg420945.html
v1: https://lkml.org/lkml/2015/4/27/232
v2: https://lkml.org/lkml/2015/5/14/470
v3: https://lkml.org/lkml/2015/5/27/220

Sudeep Holla (8):
Documentation: add DT binding for ARM System Control and Power
Interface(SCPI) protocol
firmware: add support for ARM System Control and Power Interface(SCPI)
protocol
clk: add support for clocks provided by SCP(System Control Processor)
clk: scpi: add support for cpufreq virtual device
cpufreq: arm_big_little: add SCPI interface driver
arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
arm64: dts: add CPU topology on Juno
arm64: dts: add clock support for all the cpus

Documentation/devicetree/bindings/arm/arm,scpi.txt | 156 +++++
arch/arm64/boot/dts/arm/juno-base.dtsi | 31 +
arch/arm64/boot/dts/arm/juno-clocks.dtsi | 23 +
arch/arm64/boot/dts/arm/juno-r1.dts | 32 +
arch/arm64/boot/dts/arm/juno.dts | 32 +
drivers/clk/Kconfig | 10 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-scpi.c | 299 +++++++++
drivers/cpufreq/Kconfig.arm | 9 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/scpi-cpufreq.c | 124 ++++
drivers/firmware/Kconfig | 19 +
drivers/firmware/Makefile | 1 +
drivers/firmware/arm_scpi.c | 709 +++++++++++++++++++++
include/linux/scpi_protocol.h | 62 ++
15 files changed, 1509 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt
create mode 100644 drivers/clk/clk-scpi.c
create mode 100644 drivers/cpufreq/scpi-cpufreq.c
create mode 100644 drivers/firmware/arm_scpi.c
create mode 100644 include/linux/scpi_protocol.h

--
1.9.1


2015-06-08 10:42:35

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 1/8] Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol

This patch adds devicetree binding for System Control and Power
Interface (SCPI) Message Protocol used between the Application Cores(AP)
and the System Control Processor(SCP). The MHU peripheral provides a
mechanism for inter-processor communication between SCP's M3 processor
and AP.

SCP offers control and management of the core/cluster power states,
various power domain DVFS including the core/cluster, certain system
clocks configuration, thermal sensors and many others.

Signed-off-by: Sudeep Holla <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
CC: Jassi Brar <[email protected]>
Cc: Liviu Dudau <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Jon Medhurst (Tixy) <[email protected]>
Cc: [email protected]
---
Documentation/devicetree/bindings/arm/arm,scpi.txt | 156 +++++++++++++++++++++
1 file changed, 156 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt

diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt
new file mode 100644
index 000000000000..f5f9684e23b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt
@@ -0,0 +1,156 @@
+System Control and Power Interface (SCPI) Message Protocol
+----------------------------------------------------------
+
+Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
+("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
+by Linux to initiate various system control and power operations.
+
+Required properties:
+
+- compatible : should be "arm,scpi"
+- mboxes: List of phandle and mailbox channel specifiers
+ All the channels reserved by remote SCP firmware for use by
+ SCPI message protocol should be specified in any order
+- shmem : List of phandle pointing to the shared memory(SHM) area between the
+ processors using these mailboxes for IPC, one for each mailbox
+ SHM can be any memory reserved for the purpose of this communication
+ between the processors.
+
+See Documentation/devicetree/bindings/mailbox/mailbox.txt
+for more details about the generic mailbox controller and
+client driver bindings.
+
+Clock bindings for the clocks based on SCPI Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Container Node
+==============
+Required properties:
+- compatible : should be "arm,scpi-clocks"
+ All the clocks provided by SCP firmware via SCPI message
+ protocol much be listed as sub-nodes under this node.
+
+Sub-nodes
+=========
+Required properties:
+- compatible : shall include one of the following
+ "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
+ These clocks don't provide the full range between the limits
+ but only discrete points within the range. The firmware
+ provides the mapping for each such operating frequency and the
+ index associated with it. The firmware also manages the
+ voltage scaling appropriately with the clock scaling.
+ "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
+ range within the specified range. The firmware provides the
+ supported range for each clock.
+
+Other required properties for all clocks(all from common clock binding):
+- #clock-cells : should be set to 1 as each of the SCPI clocks have multiple
+ outputs. The clock specifier will be the index to an entry in the list
+ of output clocks.
+- clock-output-names : shall be the corresponding names of the outputs.
+- clock-indices: The identifyng number for the clocks(clock_id) in the node as
+ expected by the firmware. It can be non linear and hence provide the
+ mapping of identifiers into the clock-output-names array.
+
+SRAM and Shared Memory for SCPI
+-------------------------------
+
+A small area of SRAM is reserved for SCPI communication between application
+processors and SCP.
+
+Required properties:
+- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sysram.txt
+
+Each sub-node represents the reserved area for SCPI.
+
+Required sub-node properties:
+- reg : The base offset and size of the reserved area with the SRAM
+- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
+ shared memory on Juno platforms
+
+[0] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Example:
+
+sram: sram@50000000 {
+ compatible = "arm,juno-sram-ns", "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x200 0x200>;
+ };
+};
+
+mailbox: mailbox0@40000000 {
+ ....
+ #mbox-cells = <1>;
+};
+
+scpi_protocol: scpi@2e000000 {
+ compatible = "arm,scpi";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>, <1>, <2>;
+ clock-output-names = "vbig", "vlittle", "vgpu";
+ };
+ scpi_clk: scpi_clocks@3 {
+ compatible = "arm,scpi-variable-clocks";
+ #clock-cells = <1>;
+ clock-indices = <3>, <4>;
+ clock-output-names = "pxlclk0", "pxlclk1";
+ };
+ };
+};
+
+cpu@0 {
+ ...
+ reg = <0 0>;
+ clocks = <&scpi_dvfs 0>;
+ clock-names = "vbig";
+};
+
+hdlcd@7ff60000 {
+ ...
+ reg = <0 0x7ff60000 0 0x1000>;
+ clocks = <&scpi_clk 1>;
+ clock-names = "pxlclk";
+};
+
+In the above example, the #clock-cells is set to 1 as required.
+scpi_dvfs has 3 output clocks namely: vbig, vlittle and vgpu with 0, 1
+and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 and
+pxlclk1 with 3 and 4 as clock-indices.
+
+The first consumer in the example is cpu@0 and it has vbig as input clock.
+The index '0' in the clock specifier here points to the first entry in the
+output clocks of scpi_dvfs for which clock_id asrequired by the firmware
+is 0.
+
+Similarly the second example is hdlcd@7ff60000 and it has pxlclk0 as input
+clock. The index '1' in the clock specifier here points to the second entry
+in the output clocks of scpi_clocks for which clock_id as required by the
+firmware is 4.
--
1.9.1

2015-06-08 10:40:53

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 2/8] firmware: add support for ARM System Control and Power Interface(SCPI) protocol

This patch adds support for System Control and Power Interface (SCPI)
Message Protocol used between the Application Cores(AP) and the System
Control Processor(SCP). The MHU peripheral provides a mechanism for
inter-processor communication between SCP's M3 processor and AP.

SCP offers control and management of the core/cluster power states,
various power domain DVFS including the core/cluster, certain system
clocks configuration, thermal sensors and many others.

This protocol driver provides interface for all the client drivers using
SCPI to make use of the features offered by the SCP.

Cc: Jassi Brar <[email protected]>
Cc: Liviu Dudau <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Jon Medhurst (Tixy) <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
---
drivers/firmware/Kconfig | 19 ++
drivers/firmware/Makefile | 1 +
drivers/firmware/arm_scpi.c | 709 ++++++++++++++++++++++++++++++++++++++++++
include/linux/scpi_protocol.h | 62 ++++
4 files changed, 791 insertions(+)
create mode 100644 drivers/firmware/arm_scpi.c
create mode 100644 include/linux/scpi_protocol.h

diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 6517132e5d8b..855092d73266 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -136,6 +136,25 @@ config QCOM_SCM
bool
depends on ARM || ARM64

+config ARM_SCPI_PROTOCOL
+ tristate "ARM System Control and Power Interface (SCPI) Message Protocol"
+ depends on ARM_MHU
+ help
+ System Control and Power Interface (SCPI) Message Protocol is
+ defined for the purpose of communication between the Application
+ Cores(AP) and the System Control Processor(SCP). The MHU peripheral
+ provides a mechanism for inter-processor communication between SCP
+ and AP.
+
+ SCP controls most of the power managament on the Application
+ Processors. It offers control and management of: the core/cluster
+ power states, various power domain DVFS including the core/cluster,
+ certain system clocks configuration, thermal sensors and many
+ others.
+
+ This protocol library provides interface for all the client drivers
+ making use of the features offered by the SCP.
+
source "drivers/firmware/google/Kconfig"
source "drivers/firmware/efi/Kconfig"

diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd3912709a..a91e890423de 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -1,6 +1,7 @@
#
# Makefile for the linux kernel.
#
+obj-$(CONFIG_ARM_SCPI_PROTOCOL) += arm_scpi.o
obj-$(CONFIG_DMI) += dmi_scan.o
obj-$(CONFIG_DMI_SYSFS) += dmi-sysfs.o
obj-$(CONFIG_EDD) += edd.o
diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
new file mode 100644
index 000000000000..420a1b57d867
--- /dev/null
+++ b/drivers/firmware/arm_scpi.c
@@ -0,0 +1,709 @@
+/*
+ * System Control and Power Interface (SCPI) Message Protocol driver
+ *
+ * SCPI Message Protocol is used between the System Control Processor(SCP)
+ * and the Application Processors(AP). The Message Handling Unit(MHU)
+ * provides a mechanism for inter-processor communication between SCP's
+ * Cortex M3 and AP.
+ *
+ * SCP offers control and management of the core/cluster power states,
+ * various power domain DVFS including the core/cluster, certain system
+ * clocks configuration, thermal sensors and many others.
+ *
+ * Copyright (C) 2015 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/bitmap.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/mailbox_client.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/printk.h>
+#include <linux/scpi_protocol.h>
+#include <linux/slab.h>
+#include <linux/sort.h>
+#include <linux/spinlock.h>
+
+#define CMD_ID_SHIFT 0
+#define CMD_ID_MASK 0x7f
+#define CMD_TOKEN_ID_SHIFT 8
+#define CMD_TOKEN_ID_MASK 0xff
+#define CMD_DATA_SIZE_SHIFT 16
+#define CMD_DATA_SIZE_MASK 0x1ff
+#define PACK_SCPI_CMD(cmd_id, tx_sz) \
+ ((((cmd_id) & CMD_ID_MASK) << CMD_ID_SHIFT) | \
+ (((tx_sz) & CMD_DATA_SIZE_MASK) << CMD_DATA_SIZE_SHIFT))
+#define ADD_SCPI_TOKEN(cmd, token) \
+ ((cmd) |= (((token) & CMD_TOKEN_ID_MASK) << CMD_TOKEN_ID_SHIFT))
+
+#define CMD_SIZE(cmd) (((cmd) >> CMD_DATA_SIZE_SHIFT) & CMD_DATA_SIZE_MASK)
+#define CMD_UNIQ_MASK (CMD_TOKEN_ID_MASK << CMD_TOKEN_ID_SHIFT | CMD_ID_MASK)
+#define CMD_XTRACT_UNIQ(cmd) ((cmd) & CMD_UNIQ_MASK)
+
+#define SCPI_SLOT 0
+
+#define MAX_DVFS_DOMAINS 8
+#define MAX_DVFS_OPPS 8
+#define DVFS_LATENCY(hdr) (le32_to_cpu(hdr) >> 16)
+#define DVFS_OPP_COUNT(hdr) ((le32_to_cpu(hdr) >> 8) & 0xff)
+
+#define PROTOCOL_REV_MINOR_BITS 16
+#define PROTOCOL_REV_MINOR_MASK ((1U << PROTOCOL_REV_MINOR_BITS) - 1)
+#define PROTOCOL_REV_MAJOR(x) ((x) >> PROTOCOL_REV_MINOR_BITS)
+#define PROTOCOL_REV_MINOR(x) ((x) & PROTOCOL_REV_MINOR_MASK)
+
+#define FW_REV_MAJOR_BITS 24
+#define FW_REV_MINOR_BITS 16
+#define FW_REV_PATCH_MASK ((1U << FW_REV_MINOR_BITS) - 1)
+#define FW_REV_MINOR_MASK ((1U << FW_REV_MAJOR_BITS) - 1)
+#define FW_REV_MAJOR(x) ((x) >> FW_REV_MAJOR_BITS)
+#define FW_REV_MINOR(x) (((x) & FW_REV_MINOR_MASK) >> FW_REV_MINOR_BITS)
+#define FW_REV_PATCH(x) ((x) & FW_REV_PATCH_MASK)
+
+#define MAX_RX_TIMEOUT (msecs_to_jiffies(30))
+
+enum scpi_error_codes {
+ SCPI_SUCCESS = 0, /* Success */
+ SCPI_ERR_PARAM = 1, /* Invalid parameter(s) */
+ SCPI_ERR_ALIGN = 2, /* Invalid alignment */
+ SCPI_ERR_SIZE = 3, /* Invalid size */
+ SCPI_ERR_HANDLER = 4, /* Invalid handler/callback */
+ SCPI_ERR_ACCESS = 5, /* Invalid access/permission denied */
+ SCPI_ERR_RANGE = 6, /* Value out of range */
+ SCPI_ERR_TIMEOUT = 7, /* Timeout has occurred */
+ SCPI_ERR_NOMEM = 8, /* Invalid memory area or pointer */
+ SCPI_ERR_PWRSTATE = 9, /* Invalid power state */
+ SCPI_ERR_SUPPORT = 10, /* Not supported or disabled */
+ SCPI_ERR_DEVICE = 11, /* Device error */
+ SCPI_ERR_BUSY = 12, /* Device busy */
+ SCPI_ERR_MAX
+};
+
+enum scpi_std_cmd {
+ SCPI_CMD_INVALID = 0x00,
+ SCPI_CMD_SCPI_READY = 0x01,
+ SCPI_CMD_SCPI_CAPABILITIES = 0x02,
+ SCPI_CMD_SET_CSS_PWR_STATE = 0x03,
+ SCPI_CMD_GET_CSS_PWR_STATE = 0x04,
+ SCPI_CMD_SET_SYS_PWR_STATE = 0x05,
+ SCPI_CMD_SET_CPU_TIMER = 0x06,
+ SCPI_CMD_CANCEL_CPU_TIMER = 0x07,
+ SCPI_CMD_DVFS_CAPABILITIES = 0x08,
+ SCPI_CMD_GET_DVFS_INFO = 0x09,
+ SCPI_CMD_SET_DVFS = 0x0a,
+ SCPI_CMD_GET_DVFS = 0x0b,
+ SCPI_CMD_GET_DVFS_STAT = 0x0c,
+ SCPI_CMD_CLOCK_CAPABILITIES = 0x0d,
+ SCPI_CMD_GET_CLOCK_INFO = 0x0e,
+ SCPI_CMD_SET_CLOCK_VALUE = 0x0f,
+ SCPI_CMD_GET_CLOCK_VALUE = 0x10,
+ SCPI_CMD_PSU_CAPABILITIES = 0x11,
+ SCPI_CMD_GET_PSU_INFO = 0x12,
+ SCPI_CMD_SET_PSU = 0x13,
+ SCPI_CMD_GET_PSU = 0x14,
+ SCPI_CMD_SENSOR_CAPABILITIES = 0x15,
+ SCPI_CMD_SENSOR_INFO = 0x16,
+ SCPI_CMD_SENSOR_VALUE = 0x17,
+ SCPI_CMD_SENSOR_CFG_PERIODIC = 0x18,
+ SCPI_CMD_SENSOR_CFG_BOUNDS = 0x19,
+ SCPI_CMD_SENSOR_ASYNC_VALUE = 0x1a,
+ SCPI_CMD_SET_DEVICE_PWR_STATE = 0x1b,
+ SCPI_CMD_GET_DEVICE_PWR_STATE = 0x1c,
+ SCPI_CMD_COUNT
+};
+
+struct scpi_xfer {
+ u32 slot; /* has to be first element */
+ u32 cmd;
+ u32 status;
+ const void *tx_buf;
+ void *rx_buf;
+ unsigned int tx_len;
+ unsigned int rx_len;
+ struct list_head node;
+ struct completion done;
+};
+
+struct scpi_chan {
+ struct mbox_client cl;
+ struct mbox_chan *chan;
+ void __iomem *tx_payload;
+ void __iomem *rx_payload;
+ struct list_head rx_pending;
+ struct list_head xfers_list;
+ struct scpi_xfer *xfers;
+ spinlock_t rx_lock; /* locking for the rx pending list */
+ struct mutex xfers_lock;
+ u8 token;
+};
+
+struct scpi_drvinfo {
+ u32 protocol_version;
+ u32 firmware_version;
+ int num_chans;
+ atomic_t next_chan;
+ struct scpi_ops *scpi_ops;
+ struct scpi_chan *channels;
+ struct scpi_dvfs_info *dvfs[MAX_DVFS_DOMAINS];
+};
+
+/*
+ * The SCP firmware only executes in little-endian mode, so any buffers
+ * shared through SCPI should have their contents converted to little-endian
+ */
+struct scpi_shared_mem {
+ __le32 command;
+ __le32 status;
+ u8 payload[0];
+} __packed;
+
+struct scp_capabilities {
+ __le32 protocol_version;
+ __le32 event_version;
+ __le32 platform_version;
+ __le32 commands[4];
+} __packed;
+
+struct clk_get_info {
+ __le16 id;
+ __le16 flags;
+ __le32 min_rate;
+ __le32 max_rate;
+ u8 name[20];
+} __packed;
+
+struct clk_get_value {
+ __le32 rate;
+} __packed;
+
+struct clk_set_value {
+ __le16 id;
+ __le16 reserved;
+ __le32 rate;
+} __packed;
+
+struct dvfs_info {
+ __le32 header;
+ struct {
+ __le32 freq;
+ __le32 m_volt;
+ } opps[MAX_DVFS_OPPS];
+} __packed;
+
+struct dvfs_get {
+ u8 index;
+} __packed;
+
+struct dvfs_set {
+ u8 domain;
+ u8 index;
+} __packed;
+
+static struct scpi_drvinfo *scpi_info;
+
+static int scpi_linux_errmap[SCPI_ERR_MAX] = {
+ /* better than switch case as long as return value is continuous */
+ 0, /* SCPI_SUCCESS */
+ -EINVAL, /* SCPI_ERR_PARAM */
+ -ENOEXEC, /* SCPI_ERR_ALIGN */
+ -EMSGSIZE, /* SCPI_ERR_SIZE */
+ -EINVAL, /* SCPI_ERR_HANDLER */
+ -EACCES, /* SCPI_ERR_ACCESS */
+ -ERANGE, /* SCPI_ERR_RANGE */
+ -ETIMEDOUT, /* SCPI_ERR_TIMEOUT */
+ -ENOMEM, /* SCPI_ERR_NOMEM */
+ -EINVAL, /* SCPI_ERR_PWRSTATE */
+ -EOPNOTSUPP, /* SCPI_ERR_SUPPORT */
+ -EIO, /* SCPI_ERR_DEVICE */
+ -EBUSY, /* SCPI_ERR_BUSY */
+};
+
+static inline int scpi_to_linux_errno(int errno)
+{
+ if (errno >= SCPI_SUCCESS && errno < SCPI_ERR_MAX)
+ return scpi_linux_errmap[errno];
+ return -EIO;
+}
+
+static void scpi_process_cmd(struct scpi_chan *ch, u32 cmd)
+{
+ unsigned long flags;
+ struct scpi_xfer *t, *match = NULL;
+
+ spin_lock_irqsave(&ch->rx_lock, flags);
+ if (list_empty(&ch->rx_pending)) {
+ spin_unlock_irqrestore(&ch->rx_lock, flags);
+ return;
+ }
+
+ list_for_each_entry(t, &ch->rx_pending, node)
+ if (CMD_XTRACT_UNIQ(t->cmd) == CMD_XTRACT_UNIQ(cmd)) {
+ list_del(&t->node);
+ match = t;
+ break;
+ }
+ /* check if wait_for_completion is in progress or timed-out */
+ if (match && !completion_done(&match->done)) {
+ struct scpi_shared_mem *mem = ch->rx_payload;
+ unsigned int len = min(match->rx_len, CMD_SIZE(cmd));
+
+ match->status = le32_to_cpu(mem->status);
+ memcpy_fromio(match->rx_buf, mem->payload, len);
+ if (match->rx_len > len)
+ memset(match->rx_buf + len, 0, match->rx_len - len);
+ complete(&match->done);
+ }
+ spin_unlock_irqrestore(&ch->rx_lock, flags);
+}
+
+static void scpi_handle_remote_msg(struct mbox_client *c, void *msg)
+{
+ struct scpi_chan *ch = container_of(c, struct scpi_chan, cl);
+ struct scpi_shared_mem *mem = ch->rx_payload;
+ u32 cmd = le32_to_cpu(mem->command);
+
+ scpi_process_cmd(ch, cmd);
+}
+
+static void scpi_tx_prepare(struct mbox_client *c, void *msg)
+{
+ unsigned long flags;
+ struct scpi_xfer *t = msg;
+ struct scpi_chan *ch = container_of(c, struct scpi_chan, cl);
+ struct scpi_shared_mem *mem = (struct scpi_shared_mem *)ch->tx_payload;
+
+ if (t->tx_buf)
+ memcpy_toio(mem->payload, t->tx_buf, t->tx_len);
+ if (t->rx_buf) {
+ if (!(++ch->token))
+ ++ch->token;
+ ADD_SCPI_TOKEN(t->cmd, ch->token);
+ spin_lock_irqsave(&ch->rx_lock, flags);
+ list_add_tail(&t->node, &ch->rx_pending);
+ spin_unlock_irqrestore(&ch->rx_lock, flags);
+ }
+ mem->command = cpu_to_le32(t->cmd);
+}
+
+static struct scpi_xfer *get_scpi_xfer(struct scpi_chan *ch)
+{
+ struct scpi_xfer *t;
+
+ mutex_lock(&ch->xfers_lock);
+ if (list_empty(&ch->xfers_list)) {
+ mutex_unlock(&ch->xfers_lock);
+ return NULL;
+ }
+ t = list_first_entry(&ch->xfers_list, struct scpi_xfer, node);
+ list_del(&t->node);
+ mutex_unlock(&ch->xfers_lock);
+ return t;
+}
+
+static void put_scpi_xfer(struct scpi_xfer *t, struct scpi_chan *ch)
+{
+ mutex_lock(&ch->xfers_lock);
+ list_add_tail(&t->node, &ch->xfers_list);
+ mutex_unlock(&ch->xfers_lock);
+}
+
+static int scpi_send_message(u8 cmd, void *tx_buf, unsigned int tx_len,
+ void *rx_buf, unsigned int rx_len)
+{
+ int ret;
+ u8 chan;
+ struct scpi_xfer *msg;
+ struct scpi_chan *scpi_chan;
+
+ chan = atomic_inc_return(&scpi_info->next_chan) % scpi_info->num_chans;
+ scpi_chan = scpi_info->channels + chan;
+
+ msg = get_scpi_xfer(scpi_chan);
+ if (!msg)
+ return -ENOMEM;
+
+ msg->slot = BIT(SCPI_SLOT);
+ msg->cmd = PACK_SCPI_CMD(cmd, tx_len);
+ msg->tx_buf = tx_buf;
+ msg->tx_len = tx_len;
+ msg->rx_buf = rx_buf;
+ msg->rx_len = rx_len;
+ init_completion(&msg->done);
+
+ ret = mbox_send_message(scpi_chan->chan, msg);
+ if (ret < 0 || !rx_buf)
+ goto out;
+
+ if (!wait_for_completion_timeout(&msg->done, MAX_RX_TIMEOUT))
+ ret = -ETIMEDOUT;
+ else
+ /* first status word */
+ ret = le32_to_cpu(msg->status);
+out:
+ if (ret < 0 && rx_buf) /* remove entry from the list if timed-out */
+ scpi_process_cmd(scpi_chan, msg->cmd);
+
+ put_scpi_xfer(msg, scpi_chan);
+ /* SCPI error codes > 0, translate them to Linux scale*/
+ return ret > 0 ? scpi_to_linux_errno(ret) : ret;
+}
+
+static u32 scpi_get_version(void)
+{
+ return scpi_info->protocol_version;
+}
+
+static int
+scpi_clk_get_range(u16 clk_id, unsigned long *min, unsigned long *max)
+{
+ int ret;
+ struct clk_get_info clk;
+ __le16 le_clk_id = cpu_to_le16(clk_id);
+
+ ret = scpi_send_message(SCPI_CMD_GET_CLOCK_INFO, &le_clk_id,
+ sizeof(le_clk_id), &clk, sizeof(clk));
+ if (!ret) {
+ *min = le32_to_cpu(clk.min_rate);
+ *max = le32_to_cpu(clk.max_rate);
+ }
+ return ret;
+}
+
+static unsigned long scpi_clk_get_val(u16 clk_id)
+{
+ int ret;
+ struct clk_get_value clk;
+ __le16 le_clk_id = cpu_to_le16(clk_id);
+
+ ret = scpi_send_message(SCPI_CMD_GET_CLOCK_VALUE, &le_clk_id,
+ sizeof(le_clk_id), &clk, sizeof(clk));
+ return ret ? ret : le32_to_cpu(clk.rate);
+}
+
+static int scpi_clk_set_val(u16 clk_id, unsigned long rate)
+{
+ int stat;
+ struct clk_set_value clk = {
+ .id = cpu_to_le16(clk_id),
+ .rate = cpu_to_le32(rate)
+ };
+
+ return scpi_send_message(SCPI_CMD_SET_CLOCK_VALUE, &clk, sizeof(clk),
+ &stat, sizeof(stat));
+}
+
+static int scpi_dvfs_get_idx(u8 domain)
+{
+ int ret;
+ struct dvfs_get dvfs;
+
+ ret = scpi_send_message(SCPI_CMD_GET_DVFS, &domain, sizeof(domain),
+ &dvfs, sizeof(dvfs));
+ return ret ? ret : dvfs.index;
+}
+
+static int scpi_dvfs_set_idx(u8 domain, u8 index)
+{
+ int stat;
+ struct dvfs_set dvfs = {domain, index};
+
+ return scpi_send_message(SCPI_CMD_SET_DVFS, &dvfs, sizeof(dvfs),
+ &stat, sizeof(stat));
+}
+
+static int opp_cmp_func(const void *opp1, const void *opp2)
+{
+ const struct scpi_opp *t1 = opp1, *t2 = opp2;
+
+ return t1->freq - t2->freq;
+}
+
+static struct scpi_dvfs_info *scpi_dvfs_get_info(u8 domain)
+{
+ struct scpi_dvfs_info *info;
+ struct scpi_opp *opp;
+ struct dvfs_info buf;
+ int ret, i;
+
+ if (domain >= MAX_DVFS_DOMAINS)
+ return ERR_PTR(-EINVAL);
+
+ if (scpi_info->dvfs[domain]) /* data already populated */
+ return scpi_info->dvfs[domain];
+
+ ret = scpi_send_message(SCPI_CMD_GET_DVFS_INFO, &domain, sizeof(domain),
+ &buf, sizeof(buf));
+
+ if (ret)
+ return ERR_PTR(ret);
+
+ info = kmalloc(sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return ERR_PTR(-ENOMEM);
+
+ info->count = DVFS_OPP_COUNT(buf.header);
+ info->latency = DVFS_LATENCY(buf.header) * 1000; /* uS to nS */
+
+ info->opps = kcalloc(info->count, sizeof(*opp), GFP_KERNEL);
+ if (!info->opps) {
+ kfree(info);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ for (i = 0, opp = info->opps; i < info->count; i++, opp++) {
+ opp->freq = le32_to_cpu(buf.opps[i].freq);
+ opp->m_volt = le32_to_cpu(buf.opps[i].m_volt);
+ }
+
+ sort(info->opps, info->count, sizeof(*opp), opp_cmp_func, NULL);
+
+ scpi_info->dvfs[domain] = info;
+ return info;
+}
+
+static struct scpi_ops scpi_ops = {
+ .get_version = scpi_get_version,
+ .clk_get_range = scpi_clk_get_range,
+ .clk_get_val = scpi_clk_get_val,
+ .clk_set_val = scpi_clk_set_val,
+ .dvfs_get_idx = scpi_dvfs_get_idx,
+ .dvfs_set_idx = scpi_dvfs_set_idx,
+ .dvfs_get_info = scpi_dvfs_get_info,
+};
+
+struct scpi_ops *get_scpi_ops(void)
+{
+ return scpi_info ? scpi_info->scpi_ops : NULL;
+}
+EXPORT_SYMBOL_GPL(get_scpi_ops);
+
+static int scpi_init_versions(struct scpi_drvinfo *info)
+{
+ int ret;
+ struct scp_capabilities caps;
+
+ ret = scpi_send_message(SCPI_CMD_SCPI_CAPABILITIES, NULL, 0,
+ &caps, sizeof(caps));
+ if (!ret) {
+ info->protocol_version = le32_to_cpu(caps.protocol_version);
+ info->firmware_version = le32_to_cpu(caps.platform_version);
+ }
+ return ret;
+}
+
+static ssize_t protocol_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct scpi_drvinfo *scpi_info = dev_get_drvdata(dev);
+
+ return sprintf(buf, "%d.%d\n",
+ PROTOCOL_REV_MAJOR(scpi_info->protocol_version),
+ PROTOCOL_REV_MINOR(scpi_info->protocol_version));
+}
+static DEVICE_ATTR_RO(protocol_version);
+
+static ssize_t firmware_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct scpi_drvinfo *scpi_info = dev_get_drvdata(dev);
+
+ return sprintf(buf, "%d.%d.%d\n",
+ FW_REV_MAJOR(scpi_info->firmware_version),
+ FW_REV_MINOR(scpi_info->firmware_version),
+ FW_REV_PATCH(scpi_info->firmware_version));
+}
+static DEVICE_ATTR_RO(firmware_version);
+
+static struct attribute *versions_attrs[] = {
+ &dev_attr_firmware_version.attr,
+ &dev_attr_protocol_version.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(versions);
+
+static void
+scpi_free_channels(struct device *dev, struct scpi_chan *pchan, int count)
+{
+ int i;
+
+ for (i = 0; i < count && pchan->chan; i++, pchan++) {
+ mbox_free_channel(pchan->chan);
+ devm_kfree(dev, pchan->xfers);
+ devm_iounmap(dev, pchan->rx_payload);
+ }
+}
+
+static int scpi_remove(struct platform_device *pdev)
+{
+ int i;
+ struct device *dev = &pdev->dev;
+ struct scpi_drvinfo *info = platform_get_drvdata(pdev);
+
+ scpi_info = NULL; /* stop exporting SCPI ops through get_scpi_ops */
+
+ of_platform_depopulate(dev);
+ sysfs_remove_groups(&dev->kobj, versions_groups);
+ scpi_free_channels(dev, info->channels, info->num_chans);
+ platform_set_drvdata(pdev, NULL);
+
+ for (i = 0; i < MAX_DVFS_DOMAINS && info->dvfs[i]; i++) {
+ kfree(info->dvfs[i]->opps);
+ kfree(info->dvfs[i]);
+ }
+ devm_kfree(dev, info->channels);
+ devm_kfree(dev, info);
+
+ return 0;
+}
+
+#define MAX_SCPI_XFERS 10
+static int scpi_alloc_xfer_list(struct device *dev, struct scpi_chan *ch)
+{
+ int i;
+ struct scpi_xfer *xfers;
+
+ xfers = devm_kzalloc(dev, MAX_SCPI_XFERS * sizeof(*xfers), GFP_KERNEL);
+ if (!xfers)
+ return -ENOMEM;
+
+ ch->xfers = xfers;
+ for (i = 0; i < MAX_SCPI_XFERS; i++, xfers++)
+ list_add_tail(&xfers->node, &ch->xfers_list);
+ return 0;
+}
+
+static int scpi_probe(struct platform_device *pdev)
+{
+ int count, idx, ret;
+ struct resource res;
+ struct scpi_chan *scpi_chan;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+
+ scpi_info = devm_kzalloc(dev, sizeof(*scpi_info), GFP_KERNEL);
+ if (!scpi_info)
+ return -ENOMEM;
+
+ count = of_count_phandle_with_args(np, "mboxes", "#mbox-cells");
+ if (count < 0) {
+ dev_err(dev, "no mboxes property in '%s'\n", np->full_name);
+ return -ENODEV;
+ }
+
+ scpi_chan = devm_kcalloc(dev, count, sizeof(*scpi_chan), GFP_KERNEL);
+ if (!scpi_chan)
+ return -ENOMEM;
+
+ for (idx = 0; idx < count; idx++) {
+ resource_size_t size;
+ struct scpi_chan *pchan = scpi_chan + idx;
+ struct mbox_client *cl = &pchan->cl;
+ struct device_node *shmem = of_parse_phandle(np, "shmem", idx);
+
+ if (of_address_to_resource(shmem, 0, &res)) {
+ dev_err(dev, "failed to get SCPI payload mem resource\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ size = resource_size(&res);
+ pchan->rx_payload = devm_ioremap(dev, res.start, size);
+ if (!pchan->rx_payload) {
+ dev_err(dev, "failed to ioremap SCPI payload\n");
+ ret = -EADDRNOTAVAIL;
+ goto err;
+ }
+ pchan->tx_payload = pchan->rx_payload + (size >> 1);
+
+ cl->dev = dev;
+ cl->rx_callback = scpi_handle_remote_msg;
+ cl->tx_prepare = scpi_tx_prepare;
+ cl->tx_block = true;
+ cl->tx_tout = 50;
+ cl->knows_txdone = false; /* controller can ack */
+
+ INIT_LIST_HEAD(&pchan->rx_pending);
+ INIT_LIST_HEAD(&pchan->xfers_list);
+ spin_lock_init(&pchan->rx_lock);
+ mutex_init(&pchan->xfers_lock);
+
+ ret = scpi_alloc_xfer_list(dev, pchan);
+ if (!ret) {
+ pchan->chan = mbox_request_channel(cl, idx);
+ if (!IS_ERR(pchan->chan))
+ continue;
+ ret = -EPROBE_DEFER;
+ dev_err(dev, "failed to acquire channel#%d\n", idx);
+ }
+err:
+ scpi_free_channels(dev, scpi_chan, idx);
+ scpi_info = NULL;
+ return ret;
+ }
+
+ scpi_info->channels = scpi_chan;
+ scpi_info->num_chans = count;
+ platform_set_drvdata(pdev, scpi_info);
+
+ ret = scpi_init_versions(scpi_info);
+ if (ret) {
+ dev_err(dev, "incorrect or no SCP firmware found\n");
+ scpi_remove(pdev);
+ return ret;
+ }
+
+ _dev_info(dev, "SCP Protocol %d.%d Firmware %d.%d.%d version\n",
+ PROTOCOL_REV_MAJOR(scpi_info->protocol_version),
+ PROTOCOL_REV_MINOR(scpi_info->protocol_version),
+ FW_REV_MAJOR(scpi_info->firmware_version),
+ FW_REV_MINOR(scpi_info->firmware_version),
+ FW_REV_PATCH(scpi_info->firmware_version));
+ scpi_info->scpi_ops = &scpi_ops;
+
+ ret = sysfs_create_groups(&dev->kobj, versions_groups);
+ if (ret)
+ dev_err(dev, "unable to create sysfs version group\n");
+
+ return of_platform_populate(dev->of_node, NULL, NULL, dev);
+}
+
+static const struct of_device_id scpi_of_match[] = {
+ {.compatible = "arm,scpi"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, scpi_of_match);
+
+static struct platform_driver scpi_driver = {
+ .driver = {
+ .name = "scpi_protocol",
+ .of_match_table = scpi_of_match,
+ },
+ .probe = scpi_probe,
+ .remove = scpi_remove,
+};
+module_platform_driver(scpi_driver);
+
+MODULE_AUTHOR("Sudeep Holla <[email protected]>");
+MODULE_DESCRIPTION("ARM SCPI mailbox protocol driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/scpi_protocol.h b/include/linux/scpi_protocol.h
new file mode 100644
index 000000000000..da8631e59b79
--- /dev/null
+++ b/include/linux/scpi_protocol.h
@@ -0,0 +1,62 @@
+/*
+ * SCPI Message Protocol driver header
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/types.h>
+
+struct scpi_opp {
+ u32 freq;
+ u32 m_volt;
+} __packed;
+
+struct scpi_dvfs_info {
+ unsigned int count;
+ unsigned int latency; /* in nanoseconds */
+ struct scpi_opp *opps;
+};
+
+/**
+ * struct scpi_ops - represents the various operations provided
+ * by SCP through SCPI message protocol
+ * @get_version: returns the major and minor revision on the SCPI
+ * message protocol
+ * @clk_get_range: gets clock range limit(min - max in Hz)
+ * @clk_get_val: gets clock value(in Hz)
+ * @clk_set_val: sets the clock value, setting to 0 will disable the
+ * clock (if supported)
+ * @dvfs_get_idx: gets the Operating Point of the given power domain.
+ * OPP is an index to the list return by @dvfs_get_info
+ * @dvfs_set_idx: sets the Operating Point of the given power domain.
+ * OPP is an index to the list return by @dvfs_get_info
+ * @dvfs_get_info: returns the DVFS capabilities of the given power
+ * domain. It includes the OPP list and the latency information
+ */
+struct scpi_ops {
+ u32 (*get_version)(void);
+ int (*clk_get_range)(u16, unsigned long *, unsigned long *);
+ unsigned long (*clk_get_val)(u16);
+ int (*clk_set_val)(u16, unsigned long);
+ int (*dvfs_get_idx)(u8);
+ int (*dvfs_set_idx)(u8, u8);
+ struct scpi_dvfs_info *(*dvfs_get_info)(u8);
+};
+
+#if defined(CONFIG_ARM_SCPI_PROTOCOL) || \
+ defined(CONFIG_ARM_SCPI_PROTOCOL_MODULE)
+struct scpi_ops *get_scpi_ops(void);
+#else
+static inline struct scpi_ops *get_scpi_ops(void) { return NULL; }
+#endif
--
1.9.1

2015-06-08 10:40:33

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Power Interface(SCPI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

This patch adds support for the clocks provided by SCP using SCPI
protocol.

Signed-off-by: Sudeep Holla <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Liviu Dudau <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Jon Medhurst (Tixy) <[email protected]>
Cc: [email protected]
---
drivers/clk/Kconfig | 10 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-scpi.c | 286 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 297 insertions(+)
create mode 100644 drivers/clk/clk-scpi.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f353bf1a..0fe8daefc105 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -59,6 +59,16 @@ config COMMON_CLK_RK808
clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
by control register.

+config COMMON_CLK_SCPI
+ tristate "Clock driver controlled via SCPI interface"
+ depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
+ ---help---
+ This driver provides support for clocks that are controlled
+ by firmware that implements the SCPI interface.
+
+ This driver uses SCPI Message Protocol to interact with the
+ firmware providing all the clock controls.
+
config COMMON_CLK_SI5351
tristate "Clock driver for SiLabs 5351A/B/C"
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25382c5..442ab6ebd5b1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
+obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o
obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
new file mode 100644
index 000000000000..707b3430c55f
--- /dev/null
+++ b/drivers/clk/clk-scpi.c
@@ -0,0 +1,286 @@
+/*
+ * System Control and Power Interface (SCPI) Protocol based clock driver
+ *
+ * Copyright (C) 2015 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/scpi_protocol.h>
+
+struct scpi_clk {
+ u32 id;
+ const char *name;
+ struct clk_hw hw;
+ struct scpi_dvfs_info *info;
+ struct scpi_ops *scpi_ops;
+};
+
+#define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
+
+static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct scpi_clk *clk = to_scpi_clk(hw);
+
+ return clk->scpi_ops->clk_get_val(clk->id);
+}
+
+static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return rate;
+}
+
+static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct scpi_clk *clk = to_scpi_clk(hw);
+
+ return clk->scpi_ops->clk_set_val(clk->id, rate);
+}
+
+static void scpi_clk_disable(struct clk_hw *hw)
+{
+ scpi_clk_set_rate(hw, 0, 0);
+}
+
+static const struct clk_ops scpi_clk_ops = {
+ .recalc_rate = scpi_clk_recalc_rate,
+ .round_rate = scpi_clk_round_rate,
+ .set_rate = scpi_clk_set_rate,
+ .disable = scpi_clk_disable,
+};
+
+/* find closest match to given frequency in OPP table */
+static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
+{
+ int idx;
+ u32 fmin = 0, fmax = ~0, ftmp;
+ struct scpi_opp *opp = clk->info->opps;
+
+ for (idx = 0; idx < clk->info->count; idx++, opp++) {
+ ftmp = opp->freq;
+ if (ftmp >= (u32)rate) {
+ if (ftmp <= fmax)
+ fmax = ftmp;
+ break;
+ } else if (ftmp >= fmin) {
+ fmin = ftmp;
+ }
+ }
+ return fmax != ~0 ? fmax : fmin;
+}
+
+static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct scpi_clk *clk = to_scpi_clk(hw);
+ int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
+ struct scpi_opp *opp;
+
+ if (idx < 0)
+ return 0;
+
+ opp = clk->info->opps + idx;
+ return opp->freq;
+}
+
+static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct scpi_clk *clk = to_scpi_clk(hw);
+
+ return __scpi_dvfs_round_rate(clk, rate);
+}
+
+static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
+{
+ int idx, max_opp = clk->info->count;
+ struct scpi_opp *opp = clk->info->opps;
+
+ for (idx = 0; idx < max_opp; idx++, opp++)
+ if (opp->freq == rate)
+ return idx;
+ return -EINVAL;
+}
+
+static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct scpi_clk *clk = to_scpi_clk(hw);
+ int ret = __scpi_find_dvfs_index(clk, rate);
+
+ if (ret < 0)
+ return ret;
+ return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
+}
+
+static const struct clk_ops scpi_dvfs_ops = {
+ .recalc_rate = scpi_dvfs_recalc_rate,
+ .round_rate = scpi_dvfs_round_rate,
+ .set_rate = scpi_dvfs_set_rate,
+};
+
+static const struct of_device_id scpi_clk_match[] = {
+ { .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
+ { .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
+ {}
+};
+
+static struct clk *
+scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
+ struct scpi_clk *sclk)
+{
+ struct clk_init_data init;
+ struct clk *clk;
+ unsigned long min = 0, max = 0;
+
+ init.name = sclk->name;
+ init.flags = CLK_IS_ROOT;
+ init.num_parents = 0;
+ init.ops = match->data;
+ sclk->hw.init = &init;
+ sclk->scpi_ops = get_scpi_ops();
+
+ if (init.ops == &scpi_dvfs_ops) {
+ sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
+ if (IS_ERR(sclk->info))
+ return NULL;
+ } else if (init.ops == &scpi_clk_ops) {
+ if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
+ return NULL;
+ } else {
+ return NULL;
+ }
+
+ clk = devm_clk_register(dev, &sclk->hw);
+ if (!IS_ERR(clk) && max)
+ clk_set_rate_range(clk, min, max);
+ return clk;
+}
+
+static int scpi_clk_add(struct device *dev, struct device_node *np,
+ const struct of_device_id *match)
+{
+ struct clk **clks;
+ int idx, count;
+ struct clk_onecell_data *clk_data;
+
+ count = of_property_count_strings(np, "clock-output-names");
+ if (count < 0) {
+ dev_err(dev, "%s: invalid clock output count\n", np->name);
+ return -EINVAL;
+ }
+
+ clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ return -ENOMEM;
+
+ for (idx = 0; idx < count; idx++) {
+ struct scpi_clk *sclk;
+ u32 val;
+
+ sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
+ if (!sclk)
+ return -ENOMEM;
+
+ if (of_property_read_string_index(np, "clock-output-names",
+ idx, &sclk->name)) {
+ dev_err(dev, "invalid clock name @ %s\n", np->name);
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(np, "clock-indices",
+ idx, &val)) {
+ dev_err(dev, "invalid clock index @ %s\n", np->name);
+ return -EINVAL;
+ }
+
+ sclk->id = val;
+
+ clks[idx] = scpi_clk_ops_init(dev, match, sclk);
+ if (IS_ERR_OR_NULL(clks[idx]))
+ dev_err(dev, "failed to register clock '%s'\n",
+ sclk->name);
+ else
+ dev_dbg(dev, "Registered clock '%s'\n", sclk->name);
+ }
+
+ clk_data->clks = clks;
+ clk_data->clk_num = idx;
+
+ return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+}
+
+static int scpi_clocks_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *child, *np = dev->of_node;
+
+ for_each_available_child_of_node(np, child)
+ of_clk_del_provider(np);
+ return 0;
+}
+
+static int scpi_clocks_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+ struct device_node *child, *np = dev->of_node;
+ const struct of_device_id *match;
+
+ if (!get_scpi_ops())
+ return -ENXIO;
+
+ for_each_available_child_of_node(np, child) {
+ match = of_match_node(scpi_clk_match, child);
+ if (!match)
+ continue;
+ ret = scpi_clk_add(dev, child, match);
+ if (ret) {
+ scpi_clocks_remove(pdev);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id scpi_clocks_ids[] = {
+ { .compatible = "arm,scpi-clocks", },
+ {}
+};
+
+static struct platform_driver scpi_clocks_driver = {
+ .driver = {
+ .name = "scpi_clocks",
+ .of_match_table = scpi_clocks_ids,
+ },
+ .probe = scpi_clocks_probe,
+ .remove = scpi_clocks_remove,
+};
+module_platform_driver(scpi_clocks_driver);
+
+MODULE_AUTHOR("Sudeep Holla <[email protected]>");
+MODULE_DESCRIPTION("ARM SCPI clock driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1

2015-06-08 10:40:43

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 4/8] clk: scpi: add support for cpufreq virtual device

The clocks for the CPUs are provided by SCP and are managed by this
clock driver. So the cpufreq device needs to be added only after the
clock get registered and removed when this driver is unloaded.

This patch manages the cpufreq virtual device based on the clock
availability.

Signed-off-by: Sudeep Holla <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Liviu Dudau <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Jon Medhurst (Tixy) <[email protected]>
Cc: [email protected]
---
drivers/clk/clk-scpi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
index 707b3430c55f..2e056ac19c54 100644
--- a/drivers/clk/clk-scpi.c
+++ b/drivers/clk/clk-scpi.c
@@ -34,6 +34,8 @@ struct scpi_clk {

#define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)

+static struct platform_device *cpufreq_dev;
+
static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -238,6 +240,11 @@ static int scpi_clocks_remove(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev->of_node;

+ if (cpufreq_dev) {
+ platform_device_unregister(cpufreq_dev);
+ cpufreq_dev = NULL;
+ }
+
for_each_available_child_of_node(np, child)
of_clk_del_provider(np);
return 0;
@@ -263,6 +270,12 @@ static int scpi_clocks_probe(struct platform_device *pdev)
return ret;
}
}
+ /* Add the virtual cpufreq device */
+ cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
+ -1, NULL, 0);
+ if (!cpufreq_dev)
+ pr_warn("unable to register cpufreq device");
+
return 0;
}

--
1.9.1

2015-06-08 10:42:13

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 5/8] cpufreq: arm_big_little: add SCPI interface driver

On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control including CPU DVFS. SCPI Message Protocol is used to
communicate with the SCPI.

This patch adds a interface driver for adding OPPs and registering
the arm_big_little cpufreq driver for such systems.

Signed-off-by: Sudeep Holla <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Cc: Viresh Kumar <[email protected]>
Cc: "Rafael J. Wysocki" <[email protected]>
Cc: [email protected]
---
drivers/cpufreq/Kconfig.arm | 9 +++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/scpi-cpufreq.c | 124 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 134 insertions(+)
create mode 100644 drivers/cpufreq/scpi-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 611cb09239eb..6419b17b89dd 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -24,6 +24,15 @@ config ARM_VEXPRESS_SPC_CPUFREQ
This add the CPUfreq driver support for Versatile Express
big.LITTLE platforms using SPC for power management.

+config ARM_SCPI_CPUFREQ
+ tristate "SCPI based CPUfreq driver"
+ depends on ARM_BIG_LITTLE_CPUFREQ && ARM_SCPI_PROTOCOL
+ help
+ This adds the CPUfreq driver support for ARM big.LITTLE platforms
+ using SCPI protocol for CPU power management.
+
+ This driver uses SCPI Message Protocol driver to interact with the
+ firmware providing the CPU DVFS functionality.

config ARM_EXYNOS_CPUFREQ
tristate "SAMSUNG EXYNOS CPUfreq Driver"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index cdce92ae2e8b..02fc9f849d4b 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -79,6 +79,7 @@ obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o
obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
+obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o

##################################################################################
# PowerPC platform drivers
diff --git a/drivers/cpufreq/scpi-cpufreq.c b/drivers/cpufreq/scpi-cpufreq.c
new file mode 100644
index 000000000000..2c3b16fd3a01
--- /dev/null
+++ b/drivers/cpufreq/scpi-cpufreq.c
@@ -0,0 +1,124 @@
+/*
+ * System Control and Power Interface (SCPI) based CPUFreq Interface driver
+ *
+ * It provides necessary ops to arm_big_little cpufreq driver.
+ *
+ * Copyright (C) 2015 ARM Ltd.
+ * Sudeep Holla <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/scpi_protocol.h>
+#include <linux/types.h>
+
+#include "arm_big_little.h"
+
+static struct scpi_ops *scpi_ops;
+
+static struct scpi_dvfs_info *scpi_get_dvfs_info(struct device *cpu_dev)
+{
+ u8 domain = topology_physical_package_id(cpu_dev->id);
+
+ if (domain < 0)
+ return ERR_PTR(-EINVAL);
+ return scpi_ops->dvfs_get_info(domain);
+}
+
+static int scpi_opp_table_ops(struct device *cpu_dev, bool remove)
+{
+ int idx, ret = 0;
+ struct scpi_opp *opp;
+ struct scpi_dvfs_info *info = scpi_get_dvfs_info(cpu_dev);
+
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+
+ if (!info->opps)
+ return -EIO;
+
+ for (opp = info->opps, idx = 0; idx < info->count; idx++, opp++) {
+ if (remove)
+ dev_pm_opp_remove(cpu_dev, opp->freq);
+ else
+ ret = dev_pm_opp_add(cpu_dev, opp->freq,
+ opp->m_volt * 1000);
+ if (ret) {
+ dev_warn(cpu_dev, "failed to add opp %uHz %umV\n",
+ opp->freq, opp->m_volt);
+ while (idx-- > 0)
+ dev_pm_opp_remove(cpu_dev, (--opp)->freq);
+ return ret;
+ }
+ }
+ return ret;
+}
+
+static int scpi_get_transition_latency(struct device *cpu_dev)
+{
+ struct scpi_dvfs_info *info = scpi_get_dvfs_info(cpu_dev);
+
+ if (IS_ERR(info))
+ return PTR_ERR(info);
+ return info->latency;
+}
+
+static int scpi_init_opp_table(struct device *cpu_dev)
+{
+ return scpi_opp_table_ops(cpu_dev, false);
+}
+
+static void scpi_free_opp_table(struct device *cpu_dev)
+{
+ scpi_opp_table_ops(cpu_dev, true);
+}
+
+static struct cpufreq_arm_bL_ops scpi_cpufreq_ops = {
+ .name = "scpi",
+ .get_transition_latency = scpi_get_transition_latency,
+ .init_opp_table = scpi_init_opp_table,
+ .free_opp_table = scpi_free_opp_table,
+};
+
+static int scpi_cpufreq_probe(struct platform_device *pdev)
+{
+ scpi_ops = get_scpi_ops();
+ if (!scpi_ops)
+ return -EIO;
+
+ return bL_cpufreq_register(&scpi_cpufreq_ops);
+}
+
+static int scpi_cpufreq_remove(struct platform_device *pdev)
+{
+ bL_cpufreq_unregister(&scpi_cpufreq_ops);
+ scpi_ops = NULL;
+ return 0;
+}
+
+static struct platform_driver scpi_cpufreq_platdrv = {
+ .driver = {
+ .name = "scpi-cpufreq",
+ .owner = THIS_MODULE,
+ },
+ .probe = scpi_cpufreq_probe,
+ .remove = scpi_cpufreq_remove,
+};
+module_platform_driver(scpi_cpufreq_platdrv);
+
+MODULE_AUTHOR("Sudeep Holla <[email protected]>");
+MODULE_DESCRIPTION("ARM SCPI CPUFreq interface driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1

2015-06-08 10:41:57

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno

This patch adds support for the MHU mailbox peripheral used on Juno by
application processors to communicate with remote SCP handling most of
the CPU/system power management. It also adds the SRAM reserving the
shared memory and SCPI message protocol using that shared memory.

Cc: Liviu Dudau <[email protected]>
Cc: Jon Medhurst (Tixy) <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 31 +++++++++++++++++++++++++++++++
arch/arm64/boot/dts/arm/juno-clocks.dtsi | 23 +++++++++++++++++++++++
2 files changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index e3ee96036eca..f8069a98da25 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -17,6 +17,18 @@
};
};

+ mailbox: mhu@2b1f0000 {
+ compatible = "arm,mhu", "arm,primecell";
+ reg = <0x0 0x2b1f0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mhu_lpri_rx",
+ "mhu_hpri_rx";
+ #mbox-cells = <1>;
+ clocks = <&soc_refclk100mhz>;
+ clock-names = "apb_pclk";
+ };
+
gic: interrupt-controller@2c010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
reg = <0x0 0x2c010000 0 0x1000>,
@@ -44,6 +56,25 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};

+ sram: sram@2e000000 {
+ compatible = "arm,juno-sram-ns", "mmio-sram";
+ reg = <0x0 0x2e000000 0x0 0x8000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x2e000000 0x8000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+
/include/ "juno-clocks.dtsi"

dma@7ff00000 {
diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
index 25352ed943e6..64af7370815a 100644
--- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
@@ -42,3 +42,26 @@
clock-frequency = <400000000>;
clock-output-names = "faxi_clk";
};
+
+ scpi {
+ compatible = "arm,scpi";
+ mboxes = <&mailbox 1>;
+ shmem = <&cpu_scp_hpri>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>, <1>, <2>;
+ clock-output-names = "vbig", "vlittle", "vgpu";
+ };
+ scpi_clk: scpi_clocks@3 {
+ compatible = "arm,scpi-variable-clocks";
+ #clock-cells = <1>;
+ clock-indices = <3>, <4>;
+ clock-output-names = "pxlclk0", "pxlclk1";
+ };
+ };
+ };
--
1.9.1

2015-06-08 10:41:05

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 7/8] arm64: dts: add CPU topology on Juno

This patch adds CPU topology on Juno. It will be useful for ther other
IP blocks depending on this topology.

Cc: Liviu Dudau <[email protected]>
Cc: Jon Medhurst (Tixy) <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
---
arch/arm64/boot/dts/arm/juno-r1.dts | 26 ++++++++++++++++++++++++++
arch/arm64/boot/dts/arm/juno.dts | 26 ++++++++++++++++++++++++++
2 files changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index c62751153a4f..69130840c6cd 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -34,6 +34,32 @@
#address-cells = <2>;
#size-cells = <0>;

+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A57_0>;
+ };
+ core1 {
+ cpu = <&A57_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&A53_0>;
+ };
+ core1 {
+ cpu = <&A53_1>;
+ };
+ core2 {
+ cpu = <&A53_2>;
+ };
+ core3 {
+ cpu = <&A53_3>;
+ };
+ };
+ };
+
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x0>;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index d7cbdd482a61..ce1128a54c8d 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -34,6 +34,32 @@
#address-cells = <2>;
#size-cells = <0>;

+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A57_0>;
+ };
+ core1 {
+ cpu = <&A57_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&A53_0>;
+ };
+ core1 {
+ cpu = <&A53_1>;
+ };
+ core2 {
+ cpu = <&A53_2>;
+ };
+ core3 {
+ cpu = <&A53_3>;
+ };
+ };
+ };
+
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x0>;
--
1.9.1

2015-06-08 10:41:35

by Sudeep Holla

[permalink] [raw]
Subject: [PATCH v4 8/8] arm64: dts: add clock support for all the cpus

This patch adds the CPU clocks so that the CPU DVFS can be enabled.

Cc: Liviu Dudau <[email protected]>
Cc: Jon Medhurst (Tixy) <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
---
arch/arm64/boot/dts/arm/juno-r1.dts | 6 ++++++
arch/arm64/boot/dts/arm/juno.dts | 6 ++++++
2 files changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 69130840c6cd..5eef4aa0c532 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -66,6 +66,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};

A57_1: cpu@1 {
@@ -74,6 +75,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};

A53_0: cpu@100 {
@@ -82,6 +84,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A53_1: cpu@101 {
@@ -90,6 +93,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A53_2: cpu@102 {
@@ -98,6 +102,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A53_3: cpu@103 {
@@ -106,6 +111,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A57_L2: l2-cache0 {
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index ce1128a54c8d..c02f880584e8 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -66,6 +66,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};

A57_1: cpu@1 {
@@ -74,6 +75,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
+ clocks = <&scpi_dvfs 0>;
};

A53_0: cpu@100 {
@@ -82,6 +84,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A53_1: cpu@101 {
@@ -90,6 +93,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A53_2: cpu@102 {
@@ -98,6 +102,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A53_3: cpu@103 {
@@ -106,6 +111,7 @@
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ clocks = <&scpi_dvfs 1>;
};

A57_L2: l2-cache0 {
--
1.9.1

2015-06-08 13:51:37

by Jon Medhurst (Tixy)

[permalink] [raw]
Subject: Re: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno

On Mon, 2015-06-08 at 11:40 +0100, Sudeep Holla wrote:
[...]
> +
> + scpi {
> + compatible = "arm,scpi";
> + mboxes = <&mailbox 1>;
> + shmem = <&cpu_scp_hpri>;
> +
> + clocks {
> + compatible = "arm,scpi-clocks";
> +
> + scpi_dvfs: scpi_clocks@0 {
> + compatible = "arm,scpi-dvfs-clocks";
> + #clock-cells = <1>;
> + clock-indices = <0>, <1>, <2>;
> + clock-output-names = "vbig", "vlittle", "vgpu";

>From where do the clock names derive? They look more like names for
voltage domains rather than clocks. My (admittedly very old) Juno docs,
have the clocks as ATLCLK, APLCLK and GPUCLK.

> + };
> + scpi_clk: scpi_clocks@3 {
> + compatible = "arm,scpi-variable-clocks";
> + #clock-cells = <1>;
> + clock-indices = <3>, <4>;
> + clock-output-names = "pxlclk0", "pxlclk1";

Can we also have clock index 5, name 'i2s_clk', for used by audio?
(I don't know what other clocks the SCP currently supports, but audio is
one being currently used by the out-of-tree code).

Also, I believe that both display outputs share the same clock, and so
pxlclk0 and pxlclk1 can't be controlled independently. But I guess these
device-tree entries are for the interface to the SCP firmware, not the
hardware, and if that pretends the clocks are independent...

--
Tixy

2015-06-08 14:33:04

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno



On 08/06/15 14:51, Jon Medhurst (Tixy) wrote:
> On Mon, 2015-06-08 at 11:40 +0100, Sudeep Holla wrote:
> [...]
>> +
>> + scpi {
>> + compatible = "arm,scpi";
>> + mboxes = <&mailbox 1>;
>> + shmem = <&cpu_scp_hpri>;
>> +
>> + clocks {
>> + compatible = "arm,scpi-clocks";
>> +
>> + scpi_dvfs: scpi_clocks@0 {
>> + compatible = "arm,scpi-dvfs-clocks";
>> + #clock-cells = <1>;
>> + clock-indices = <0>, <1>, <2>;
>> + clock-output-names = "vbig", "vlittle", "vgpu";
>
> From where do the clock names derive? They look more like names for
> voltage domains rather than clocks. My (admittedly very old) Juno docs,
> have the clocks as ATLCLK, APLCLK and GPUCLK.
>

I agree, I just copied it from SCPI spec which just deals with power
domain names in the context of DVFS. I will update as per Juno doc.

>> + };
>> + scpi_clk: scpi_clocks@3 {
>> + compatible = "arm,scpi-variable-clocks";
>> + #clock-cells = <1>;
>> + clock-indices = <3>, <4>;
>> + clock-output-names = "pxlclk0", "pxlclk1";
>
> Can we also have clock index 5, name 'i2s_clk', for used by audio?
> (I don't know what other clocks the SCP currently supports, but audio is
> one being currently used by the out-of-tree code).
>

I will update.

> Also, I believe that both display outputs share the same clock, and so
> pxlclk0 and pxlclk1 can't be controlled independently. But I guess these
> device-tree entries are for the interface to the SCP firmware, not the
> hardware, and if that pretends the clocks are independent...
>

Yes, this is bit tricky, I will let Liviu answer this.

Regards,
Sudeep

2015-06-08 14:35:23

by Liviu Dudau

[permalink] [raw]
Subject: Re: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno

On Mon, Jun 08, 2015 at 02:51:19PM +0100, Jon Medhurst (Tixy) wrote:
> On Mon, 2015-06-08 at 11:40 +0100, Sudeep Holla wrote:
> [...]
> > +
> > + scpi {
> > + compatible = "arm,scpi";
> > + mboxes = <&mailbox 1>;
> > + shmem = <&cpu_scp_hpri>;
> > +
> > + clocks {
> > + compatible = "arm,scpi-clocks";
> > +
> > + scpi_dvfs: scpi_clocks@0 {
> > + compatible = "arm,scpi-dvfs-clocks";
> > + #clock-cells = <1>;
> > + clock-indices = <0>, <1>, <2>;
> > + clock-output-names = "vbig", "vlittle", "vgpu";
>
> From where do the clock names derive? They look more like names for
> voltage domains rather than clocks. My (admittedly very old) Juno docs,
> have the clocks as ATLCLK, APLCLK and GPUCLK.
>
> > + };
> > + scpi_clk: scpi_clocks@3 {
> > + compatible = "arm,scpi-variable-clocks";
> > + #clock-cells = <1>;
> > + clock-indices = <3>, <4>;
> > + clock-output-names = "pxlclk0", "pxlclk1";
>
> Can we also have clock index 5, name 'i2s_clk', for used by audio?
> (I don't know what other clocks the SCP currently supports, but audio is
> one being currently used by the out-of-tree code).
>
> Also, I believe that both display outputs share the same clock, and so
> pxlclk0 and pxlclk1 can't be controlled independently. But I guess these
> device-tree entries are for the interface to the SCP firmware, not the
> hardware, and if that pretends the clocks are independent...

Actually, they can be independent, but the other source for clock generation
can only be used to drive a VGA resolution.

We were just debating with Sudeep on how to expose this: at the moment the SCP
is configured so that the request for a clock frequency always succeeds even
if the other user of the clock is active. That means that if you have 2 monitors
connected that have different resolutions or pixel clocks then one of the
monitor will get out of sync (unless it is a VGA monitor). On the other hand the
HDLCD driver (or more corectly the DRM KMS one) will default to 640x480 if no
monitor is connected to an HDMI output, meaning the clock could already be used
but by a driver that should really be inactive. It is very hard to detect in
which situation we are, so the usual fix is "plug the monitor into the other
HDMI output if you have problems with single monitors".

Best regards,
Liviu

>
> --
> Tixy
>
>

--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯

2015-06-11 11:54:28

by Jassi Brar

[permalink] [raw]
Subject: Re: [PATCH v4 2/8] firmware: add support for ARM System Control and Power Interface(SCPI) protocol

On 8 June 2015 at 16:09, Sudeep Holla <[email protected]> wrote:
...
> +
> +static void scpi_process_cmd(struct scpi_chan *ch, u32 cmd)
> +{
> + unsigned long flags;
> + struct scpi_xfer *t, *match = NULL;
> +
> + spin_lock_irqsave(&ch->rx_lock, flags);
> + if (list_empty(&ch->rx_pending)) {
> + spin_unlock_irqrestore(&ch->rx_lock, flags);
> + return;
> + }
> +
> + list_for_each_entry(t, &ch->rx_pending, node)
> + if (CMD_XTRACT_UNIQ(t->cmd) == CMD_XTRACT_UNIQ(cmd)) {
> + list_del(&t->node);
> + match = t;
> + break;
> + }
> + /* check if wait_for_completion is in progress or timed-out */
> + if (match && !completion_done(&match->done)) {
> + struct scpi_shared_mem *mem = ch->rx_payload;
> + unsigned int len = min(match->rx_len, CMD_SIZE(cmd));
> +
> + match->status = le32_to_cpu(mem->status);
> + memcpy_fromio(match->rx_buf, mem->payload, len);
> + if (match->rx_len > len)
> + memset(match->rx_buf + len, 0, match->rx_len - len);
> + complete(&match->done);
> + }
> + spin_unlock_irqrestore(&ch->rx_lock, flags);
> +}
There doesn't seem to be support for commands sent by remote?
Something like when remote is the thermal master and it needs to send
sensor readings crossing thresholds.

2015-06-11 13:24:00

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 2/8] firmware: add support for ARM System Control and Power Interface(SCPI) protocol



On 11/06/15 12:54, Jassi Brar wrote:
> On 8 June 2015 at 16:09, Sudeep Holla <[email protected]> wrote:
> ...
>> +
>> +static void scpi_process_cmd(struct scpi_chan *ch, u32 cmd)
>> +{
>> + unsigned long flags;
>> + struct scpi_xfer *t, *match = NULL;
>> +
>> + spin_lock_irqsave(&ch->rx_lock, flags);
>> + if (list_empty(&ch->rx_pending)) {
>> + spin_unlock_irqrestore(&ch->rx_lock, flags);
>> + return;
>> + }
>> +
>> + list_for_each_entry(t, &ch->rx_pending, node)
>> + if (CMD_XTRACT_UNIQ(t->cmd) == CMD_XTRACT_UNIQ(cmd)) {
>> + list_del(&t->node);
>> + match = t;
>> + break;
>> + }
>> + /* check if wait_for_completion is in progress or timed-out */
>> + if (match && !completion_done(&match->done)) {
>> + struct scpi_shared_mem *mem = ch->rx_payload;
>> + unsigned int len = min(match->rx_len, CMD_SIZE(cmd));
>> +
>> + match->status = le32_to_cpu(mem->status);
>> + memcpy_fromio(match->rx_buf, mem->payload, len);
>> + if (match->rx_len > len)
>> + memset(match->rx_buf + len, 0, match->rx_len - len);
>> + complete(&match->done);
>> + }
>> + spin_unlock_irqrestore(&ch->rx_lock, flags);
>> +}
> There doesn't seem to be support for commands sent by remote?
> Something like when remote is the thermal master and it needs to send
> sensor readings crossing thresholds.
>

SCP firmware claims to support that but never tested on Juno platform.
So I would like to add it when there's first user for that.

Regards,
Sudeep

2015-07-02 17:23:23

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

On 06/08, Sudeep Holla wrote:
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 9897f353bf1a..0fe8daefc105 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -59,6 +59,16 @@ config COMMON_CLK_RK808
> clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
> by control register.
>
> +config COMMON_CLK_SCPI
> + tristate "Clock driver controlled via SCPI interface"
> + depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
> + ---help---
> + This driver provides support for clocks that are controlled
> + by firmware that implements the SCPI interface.
> +
> + This driver uses SCPI Message Protocol to interact with the
> + firmware providing all the clock controls.

The tabbing is weird here. Both paragraphs should have the same
alignment.

> diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
> new file mode 100644
> index 000000000000..707b3430c55f
> --- /dev/null
> +++ b/drivers/clk/clk-scpi.c
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/of.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/scpi_protocol.h>

Please include <linux/platform_device.h> as well.

> +
> +struct scpi_clk {
> + u32 id;
> + const char *name;

Do you need this? Or can you just use __clk_get_name() in places
where the name is used?

> + struct clk_hw hw;
> + struct scpi_dvfs_info *info;
> + struct scpi_ops *scpi_ops;
> +};
> +
> +#define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
> +
> +static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct scpi_clk *clk = to_scpi_clk(hw);
> +
> + return clk->scpi_ops->clk_get_val(clk->id);
> +}
> +
> +static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *parent_rate)
> +{

Maybe a comment here like:

/*
* We can't figure out what rate it will be, so just return the rate
* back to the caller. scpi_clk_recalc_rate() will be called
* after the rate is set and we'll know what rate the clock is
* running at then.
*/

> + return rate;
> +}
> +
> +static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct scpi_clk *clk = to_scpi_clk(hw);
> +
> + return clk->scpi_ops->clk_set_val(clk->id, rate);
> +}
> +
> +static void scpi_clk_disable(struct clk_hw *hw)
> +{
> + scpi_clk_set_rate(hw, 0, 0);

Does this mean you have to set a rate to enable the clock? Are
you relying on drivers to call clk_set_rate() to implicitly
enable the clock? If so, it would be better to cache the rate of
the clock in set_rate if the clock isn't enabled in software and
then send the cached rate during enable.

> +}
> +
[..]
> +/* find closest match to given frequency in OPP table */
> +static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
> +{
> + int idx;
> + u32 fmin = 0, fmax = ~0, ftmp;
> + struct scpi_opp *opp = clk->info->opps;
> +

const?

> + for (idx = 0; idx < clk->info->count; idx++, opp++) {
> + ftmp = opp->freq;
> + if (ftmp >= (u32)rate) {
> + if (ftmp <= fmax)
> + fmax = ftmp;
> + break;
> + } else if (ftmp >= fmin) {
> + fmin = ftmp;
> + }
> + }
> + return fmax != ~0 ? fmax : fmin;
> +}
> +
> +static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct scpi_clk *clk = to_scpi_clk(hw);
> + int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
> + struct scpi_opp *opp;

const?

> +
> + if (idx < 0)
> + return 0;
> +
> + opp = clk->info->opps + idx;
> + return opp->freq;
> +}
> +
> +static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *parent_rate)
> +{
> + struct scpi_clk *clk = to_scpi_clk(hw);
> +
> + return __scpi_dvfs_round_rate(clk, rate);
> +}
> +
> +static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
> +{
> + int idx, max_opp = clk->info->count;
> + struct scpi_opp *opp = clk->info->opps;

const?

> +
> + for (idx = 0; idx < max_opp; idx++, opp++)
> + if (opp->freq == rate)
> + return idx;
> + return -EINVAL;
> +}
> +
[..]
> +static struct clk *
> +scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
> + struct scpi_clk *sclk)
> +{
> + struct clk_init_data init;
> + struct clk *clk;
> + unsigned long min = 0, max = 0;
> +
> + init.name = sclk->name;
> + init.flags = CLK_IS_ROOT;
> + init.num_parents = 0;
> + init.ops = match->data;
> + sclk->hw.init = &init;
> + sclk->scpi_ops = get_scpi_ops();
> +
> + if (init.ops == &scpi_dvfs_ops) {
> + sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
> + if (IS_ERR(sclk->info))
> + return NULL;
> + } else if (init.ops == &scpi_clk_ops) {
> + if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
> + return NULL;
> + } else {
> + return NULL;
> + }
> +
> + clk = devm_clk_register(dev, &sclk->hw);
> + if (!IS_ERR(clk) && max)
> + clk_set_rate_range(clk, min, max);

Hm.. we're planning to make clk_register() return a struct
clk_hw, so this will block that. We need some sort of clk_hw API
that allows us to setup min/max limits on the clock from the
provider side. Care to add that?

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

2015-07-03 14:52:51

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

Hi Stephen,


Thanks for the review.

On 02/07/15 18:23, Stephen Boyd wrote:
> On 06/08, Sudeep Holla wrote:
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index 9897f353bf1a..0fe8daefc105 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -59,6 +59,16 @@ config COMMON_CLK_RK808
>> clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
>> by control register.
>>
>> +config COMMON_CLK_SCPI
>> + tristate "Clock driver controlled via SCPI interface"
>> + depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
>> + ---help---
>> + This driver provides support for clocks that are controlled
>> + by firmware that implements the SCPI interface.
>> +
>> + This driver uses SCPI Message Protocol to interact with the
>> + firmware providing all the clock controls.
>
> The tabbing is weird here. Both paragraphs should have the same
> alignment.
>

Indeed, sorry for that, fixed now.

>> diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
>> new file mode 100644
>> index 000000000000..707b3430c55f
>> --- /dev/null
>> +++ b/drivers/clk/clk-scpi.c
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/of.h>
>> +#include <linux/module.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/scpi_protocol.h>
>
> Please include <linux/platform_device.h> as well.
>

Added now, didn't bother as of_platform.h includes it.

>> +
>> +struct scpi_clk {
>> + u32 id;
>> + const char *name;
>
> Do you need this? Or can you just use __clk_get_name() in places
> where the name is used?
>

Not used, so removed it.


[...]

>> +static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long *parent_rate)
>> +{
>
> Maybe a comment here like:
>
> /*
> * We can't figure out what rate it will be, so just return the rate
> * back to the caller. scpi_clk_recalc_rate() will be called
> * after the rate is set and we'll know what rate the clock is
> * running at then.
> */
>

Done

>> + return rate;
>> +}
>> +
>> +static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct scpi_clk *clk = to_scpi_clk(hw);
>> +
>> + return clk->scpi_ops->clk_set_val(clk->id, rate);
>> +}
>> +
>> +static void scpi_clk_disable(struct clk_hw *hw)
>> +{
>> + scpi_clk_set_rate(hw, 0, 0);
>
> Does this mean you have to set a rate to enable the clock? Are
> you relying on drivers to call clk_set_rate() to implicitly
> enable the clock? If so, it would be better to cache the rate of
> the clock in set_rate if the clock isn't enabled in software and
> then send the cached rate during enable.
>

Agreed, I have asked the firmware/SCPI specification guys about
more details on what to expect from firmware. Once they get back,
will update the code considering your feedback.

[...]

>> +static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
>> +{
>> + int idx, max_opp = clk->info->count;
>> + struct scpi_opp *opp = clk->info->opps;
>
> const?
>

All the 3 above fixed now.

[...]

>> +
>> + clk = devm_clk_register(dev, &sclk->hw);
>> + if (!IS_ERR(clk) && max)
>> + clk_set_rate_range(clk, min, max);
>
> Hm.. we're planning to make clk_register() return a struct
> clk_hw, so this will block that. We need some sort of clk_hw API
> that allows us to setup min/max limits on the clock from the
> provider side. Care to add that?
>

Can you provide pointer to the patches or the tree containing those
changes ? Are they targeted for v4.3 ?

Regards,
Sudeep

2015-07-03 16:12:33

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)



On 03/07/15 15:52, Sudeep Holla wrote:

[...]

>>> +static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>>> + unsigned long parent_rate)
>>> +{
>>> + struct scpi_clk *clk = to_scpi_clk(hw);
>>> +
>>> + return clk->scpi_ops->clk_set_val(clk->id, rate);
>>> +}
>>> +
>>> +static void scpi_clk_disable(struct clk_hw *hw)
>>> +{
>>> + scpi_clk_set_rate(hw, 0, 0);
>>
>> Does this mean you have to set a rate to enable the clock? Are
>> you relying on drivers to call clk_set_rate() to implicitly
>> enable the clock? If so, it would be better to cache the rate of
>> the clock in set_rate if the clock isn't enabled in software and
>> then send the cached rate during enable.
>>
>
> Agreed, I have asked the firmware/SCPI specification guys about
> more details on what to expect from firmware. Once they get back,
> will update the code considering your feedback.
>

OK, I got feedback and looks like it was never planned to implement that
and even specification needs to be fixed. So I will drop the disable
callback support. For now, we don't support {en,dis}able
features. We need to amend the specification to fix that.

Regards,
Sudeep

2015-07-06 19:52:58

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

On 07/03/2015 07:52 AM, Sudeep Holla wrote:
> Hi Stephen,
>
>
> Thanks for the review.
>
> On 02/07/15 18:23, Stephen Boyd wrote:
>> On 06/08, Sudeep Holla wrote:
>>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>>> index 9897f353bf1a..0fe8daefc105 100644
>>> --- a/drivers/clk/Kconfig
>>> +++ b/drivers/clk/Kconfig
>>> @@ -59,6 +59,16 @@ config COMMON_CLK_RK808
>>> clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
>>> by control register.
>>>
>>> +config COMMON_CLK_SCPI
>>> + tristate "Clock driver controlled via SCPI interface"
>>> + depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
>>> + ---help---
>>> + This driver provides support for clocks that are controlled
>>> + by firmware that implements the SCPI interface.
>>> +
>>> + This driver uses SCPI Message Protocol to interact with the
>>> + firmware providing all the clock controls.
>>
>> The tabbing is weird here. Both paragraphs should have the same
>> alignment.
>>
>
> Indeed, sorry for that, fixed now.
>
>>> diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
>>> new file mode 100644
>>> index 000000000000..707b3430c55f
>>> --- /dev/null
>>> +++ b/drivers/clk/clk-scpi.c
>>> +
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/device.h>
>>> +#include <linux/err.h>
>>> +#include <linux/of.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_platform.h>
>>> +#include <linux/scpi_protocol.h>
>>
>> Please include <linux/platform_device.h> as well.
>>
>
> Added now, didn't bother as of_platform.h includes it.
>
>>> +
>>> +struct scpi_clk {
>>> + u32 id;
>>> + const char *name;
>>
>> Do you need this? Or can you just use __clk_get_name() in places
>> where the name is used?
>>
>
> Not used, so removed it.
>
>
> [...]
>
>>> +static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
>>> + unsigned long *parent_rate)
>>> +{
>>
>> Maybe a comment here like:
>>
>> /*
>> * We can't figure out what rate it will be, so just return the rate
>> * back to the caller. scpi_clk_recalc_rate() will be called
>> * after the rate is set and we'll know what rate the clock is
>> * running at then.
>> */
>>
>
> Done
>
>>> + return rate;
>>> +}
>>> +
>>> +static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>>> + unsigned long parent_rate)
>>> +{
>>> + struct scpi_clk *clk = to_scpi_clk(hw);
>>> +
>>> + return clk->scpi_ops->clk_set_val(clk->id, rate);
>>> +}
>>> +
>>> +static void scpi_clk_disable(struct clk_hw *hw)
>>> +{
>>> + scpi_clk_set_rate(hw, 0, 0);
>>
>> Does this mean you have to set a rate to enable the clock? Are
>> you relying on drivers to call clk_set_rate() to implicitly
>> enable the clock? If so, it would be better to cache the rate of
>> the clock in set_rate if the clock isn't enabled in software and
>> then send the cached rate during enable.
>>
>
> Agreed, I have asked the firmware/SCPI specification guys about
> more details on what to expect from firmware. Once they get back,
> will update the code considering your feedback.
>
> [...]
>
>>> +static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned
>>> long rate)
>>> +{
>>> + int idx, max_opp = clk->info->count;
>>> + struct scpi_opp *opp = clk->info->opps;
>>
>> const?
>>
>
> All the 3 above fixed now.
>
> [...]
>
>>> +
>>> + clk = devm_clk_register(dev, &sclk->hw);
>>> + if (!IS_ERR(clk) && max)
>>> + clk_set_rate_range(clk, min, max);
>>
>> Hm.. we're planning to make clk_register() return a struct
>> clk_hw, so this will block that. We need some sort of clk_hw API
>> that allows us to setup min/max limits on the clock from the
>> provider side. Care to add that?
>>
>
> Can you provide pointer to the patches or the tree containing those
> changes ? Are they targeted for v4.3 ?
>

If I have time I may try to start doing the clk_register() conversion,
but it will take a while so I doubt it will be in v4.3. I'm asking if
you can add a clk_hw based API that does something like
clk_set_rate_range() without requiring a struct clk pointer. i.e.
clk_hw_set_rate_range(struct clk_hw *hw, min, max) that constraints the
min/max rate of the clock. This way, the driver is only using clk
provider APIs and not clk consumer APIs.

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a Linux Foundation Collaborative Project

2015-07-07 16:03:48

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)



On 06/07/15 20:52, Stephen Boyd wrote:
> On 07/03/2015 07:52 AM, Sudeep Holla wrote:
>> Hi Stephen,
>>
>>
>> Thanks for the review.
>>
>> On 02/07/15 18:23, Stephen Boyd wrote:
>>> On 06/08, Sudeep Holla wrote:

[...]

>>>> +
>>>> + clk = devm_clk_register(dev, &sclk->hw);
>>>> + if (!IS_ERR(clk) && max)
>>>> + clk_set_rate_range(clk, min, max);
>>>
>>> Hm.. we're planning to make clk_register() return a struct
>>> clk_hw, so this will block that. We need some sort of clk_hw API
>>> that allows us to setup min/max limits on the clock from the
>>> provider side. Care to add that?
>>>
>>
>> Can you provide pointer to the patches or the tree containing those
>> changes ? Are they targeted for v4.3 ?
>>
>
> If I have time I may try to start doing the clk_register() conversion,
> but it will take a while so I doubt it will be in v4.3. I'm asking if
> you can add a clk_hw based API that does something like
> clk_set_rate_range() without requiring a struct clk pointer. i.e.
> clk_hw_set_rate_range(struct clk_hw *hw, min, max) that constraints the
> min/max rate of the clock. This way, the driver is only using clk
> provider APIs and not clk consumer APIs.
>

I understand the intention of separating clk provider helpers/APIs
and clk consumer APIs. Since {min,max}_rate are part of struct clk
itself, I was thinking that you would have moved it to struct clk_core
as part of the rework you mentioned and hence asked about the patches.

IIUC, if {min,max}_rate remain part of struct clk, then how are we
restricting that operation to just the clk providers ? clk consumer
can still directly modify or use clk_set_rate_range.

Do we continue to provide that feature for both provider and consumer ?
If so I assume {min,max}_rate range requested by consumer should be
within the limits set by provider and do we maintain both the limits ?

Sorry if I am missing something fundamental since I don't have much
knowledge of clk layer internals.

Regards,
Sudeep

2015-07-08 01:46:12

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

On 07/07, Sudeep Holla wrote:
>
>
> On 06/07/15 20:52, Stephen Boyd wrote:
> >>
> >
> >If I have time I may try to start doing the clk_register() conversion,
> >but it will take a while so I doubt it will be in v4.3. I'm asking if
> >you can add a clk_hw based API that does something like
> >clk_set_rate_range() without requiring a struct clk pointer. i.e.
> >clk_hw_set_rate_range(struct clk_hw *hw, min, max) that constraints the
> >min/max rate of the clock. This way, the driver is only using clk
> >provider APIs and not clk consumer APIs.
> >
>
> I understand the intention of separating clk provider helpers/APIs
> and clk consumer APIs. Since {min,max}_rate are part of struct clk
> itself, I was thinking that you would have moved it to struct clk_core
> as part of the rework you mentioned and hence asked about the patches.
>
> IIUC, if {min,max}_rate remain part of struct clk, then how are we
> restricting that operation to just the clk providers ? clk consumer
> can still directly modify or use clk_set_rate_range.
>
> Do we continue to provide that feature for both provider and consumer ?
> If so I assume {min,max}_rate range requested by consumer should be
> within the limits set by provider and do we maintain both the limits ?
>
> Sorry if I am missing something fundamental since I don't have much
> knowledge of clk layer internals.
>

Yes struct clk would have min/max, and struct clk_core would have
min/max. Then some sort of provider API (or possibly even
clk_init_data) would take the min/max fields and copy them over
to struct clk_core. Then during set_rate operations we would
aggregate the constraints from struct clk like we already do and
add in the constrains in struct clk_core.

One downside to adding new fields to clk_init_data is that there
are drivers out there that aren't initializing that structure to
0, and they're putting it on the stack, so stack junk can come
through. Furthermore, min/max would mean that every driver needs
to specify some large number for max or we have to special case
min == max == 0 and ignore it. Somehow it needs to be opt-in. If
we want to go down the clk_init_data route then perhaps we need
some sort of rate_constraint struct pointer in there that drivers
can optionally setup.

struct clk_rate_constraint {
unsigned long min;
unsigned long max;
};

struct clk_init_data {
...
struct clk_rate_constraint *rate_constraint;
};

I haven't thought it through completely, but I can probably write
up some patch tomorrow after I sleep on it.

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a Linux Foundation Collaborative Project

2015-07-08 13:59:31

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 1/8] Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol

Hi Mark,

On 08/06/15 11:39, Sudeep Holla wrote:
> This patch adds devicetree binding for System Control and Power
> Interface (SCPI) Message Protocol used between the Application Cores(AP)
> and the System Control Processor(SCP). The MHU peripheral provides a
> mechanism for inter-processor communication between SCP's M3 processor
> and AP.
>
> SCP offers control and management of the core/cluster power states,
> various power domain DVFS including the core/cluster, certain system
> clocks configuration, thermal sensors and many others.
>
> Signed-off-by: Sudeep Holla <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>

Can you review this version ?

Regards,
Sudeep

2015-07-16 16:11:14

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

Hi Stephen,

On 08/07/15 02:46, Stephen Boyd wrote:
> On 07/07, Sudeep Holla wrote:
>>
>>
>> On 06/07/15 20:52, Stephen Boyd wrote:
>>>>
>>>
>>> If I have time I may try to start doing the clk_register() conversion,
>>> but it will take a while so I doubt it will be in v4.3. I'm asking if
>>> you can add a clk_hw based API that does something like
>>> clk_set_rate_range() without requiring a struct clk pointer. i.e.
>>> clk_hw_set_rate_range(struct clk_hw *hw, min, max) that constraints the
>>> min/max rate of the clock. This way, the driver is only using clk
>>> provider APIs and not clk consumer APIs.
>>>
>>
>> I understand the intention of separating clk provider helpers/APIs
>> and clk consumer APIs. Since {min,max}_rate are part of struct clk
>> itself, I was thinking that you would have moved it to struct clk_core
>> as part of the rework you mentioned and hence asked about the patches.
>>
>> IIUC, if {min,max}_rate remain part of struct clk, then how are we
>> restricting that operation to just the clk providers ? clk consumer
>> can still directly modify or use clk_set_rate_range.
>>
>> Do we continue to provide that feature for both provider and consumer ?
>> If so I assume {min,max}_rate range requested by consumer should be
>> within the limits set by provider and do we maintain both the limits ?
>>
>> Sorry if I am missing something fundamental since I don't have much
>> knowledge of clk layer internals.
>>
>
> Yes struct clk would have min/max, and struct clk_core would have
> min/max. Then some sort of provider API (or possibly even
> clk_init_data) would take the min/max fields and copy them over
> to struct clk_core. Then during set_rate operations we would
> aggregate the constraints from struct clk like we already do and
> add in the constrains in struct clk_core.
>
> One downside to adding new fields to clk_init_data is that there
> are drivers out there that aren't initializing that structure to
> 0, and they're putting it on the stack, so stack junk can come
> through. Furthermore, min/max would mean that every driver needs
> to specify some large number for max or we have to special case
> min == max == 0 and ignore it. Somehow it needs to be opt-in. If
> we want to go down the clk_init_data route then perhaps we need
> some sort of rate_constraint struct pointer in there that drivers
> can optionally setup.
>
> struct clk_rate_constraint {
> unsigned long min;
> unsigned long max;
> };
>
> struct clk_init_data {
> ...
> struct clk_rate_constraint *rate_constraint;
> };
>
> I haven't thought it through completely, but I can probably write
> up some patch tomorrow after I sleep on it.
>

I am hoping to get this series for v4.3. In order to avoid using
consumer API, I can revert back to the min,max check I had in the
round_rate earlier if that's fine with you ? Let me know so that I can
post the next version based on that. All the other comments are already
addressed.

Also since this series depends on SCPI, I was thinking to get it merged
via ARM-SoC, but that might conflict with the round_rate prototype
change. Do do plan to share a stable base with arm-soc guys or you
expect all the changes to be contained in clk tree ?

Regards,
Sudeep

2015-07-16 19:31:18

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

On 07/16, Sudeep Holla wrote:
> On 08/07/15 02:46, Stephen Boyd wrote:
> >
> >Yes struct clk would have min/max, and struct clk_core would have
> >min/max. Then some sort of provider API (or possibly even
> >clk_init_data) would take the min/max fields and copy them over
> >to struct clk_core. Then during set_rate operations we would
> >aggregate the constraints from struct clk like we already do and
> >add in the constrains in struct clk_core.
> >
> >One downside to adding new fields to clk_init_data is that there
> >are drivers out there that aren't initializing that structure to
> >0, and they're putting it on the stack, so stack junk can come
> >through. Furthermore, min/max would mean that every driver needs
> >to specify some large number for max or we have to special case
> >min == max == 0 and ignore it. Somehow it needs to be opt-in. If
> >we want to go down the clk_init_data route then perhaps we need
> >some sort of rate_constraint struct pointer in there that drivers
> >can optionally setup.
> >
> > struct clk_rate_constraint {
> > unsigned long min;
> > unsigned long max;
> > };
> >
> > struct clk_init_data {
> > ...
> > struct clk_rate_constraint *rate_constraint;
> > };
> >
> >I haven't thought it through completely, but I can probably write
> >up some patch tomorrow after I sleep on it.
> >
>
> I am hoping to get this series for v4.3. In order to avoid using
> consumer API, I can revert back to the min,max check I had in the
> round_rate earlier if that's fine with you ? Let me know so that I can
> post the next version based on that. All the other comments are already
> addressed.

Ok. I'm fine with the consumer API being used, but it would be
nice if we didn't have to do so. Try out the patch below,
hopefully it's good enough for your purposes. It may need to be
more robust, and we may still want to use the init_data structure
to avoid races with providers and consumers, but we can leave
that for later after sweeping all the structure users.

>
> Also since this series depends on SCPI, I was thinking to get it merged
> via ARM-SoC, but that might conflict with the round_rate prototype
> change. Do do plan to share a stable base with arm-soc guys or you
> expect all the changes to be contained in clk tree ?
>

We can share a stable branch for the determine_rate change with
arm-soc. We already have it on a separate branch but haven't
published it so far because nobody has asked.

Signed-off-by: Stephen Boyd <[email protected]>

-----8<------
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index a1d34a2ed9c6..8760b743bb70 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -58,6 +58,8 @@ struct clk_core {
unsigned long flags;
unsigned int enable_count;
unsigned int prepare_count;
+ unsigned long min_rate;
+ unsigned long max_rate;
unsigned long accuracy;
int phase;
struct hlist_head children;
@@ -512,8 +514,8 @@ static void clk_core_get_boundaries(struct clk_core *core,
{
struct clk *clk_user;

- *min_rate = 0;
- *max_rate = ULONG_MAX;
+ *min_rate = core->min_rate;
+ *max_rate = core->max_rate;

hlist_for_each_entry(clk_user, &core->clks, clks_node)
*min_rate = max(*min_rate, clk_user->min_rate);
@@ -522,6 +524,13 @@ static void clk_core_get_boundaries(struct clk_core *core,
*max_rate = min(*max_rate, clk_user->max_rate);
}

+void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
+ unsigned long max_rate)
+{
+ hw->core->min_rate = min_rate;
+ hw->core->max_rate = max_rate;
+}
+
/*
* Helper for finding best parent to provide a given frequency. This can be used
* directly as a determine_rate callback (e.g. for a mux), or from a more
@@ -2496,6 +2505,8 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
core->hw = hw;
core->flags = hw->init->flags;
core->num_parents = hw->init->num_parents;
+ core->min_rate = 0;
+ core->max_rate = ULONG_MAX;
hw->core = core;

/* allocate local copy in case parent_names is __initdata */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 2116e2b8a5f2..d62e7eab1dbe 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -619,6 +619,8 @@ int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
int __clk_mux_determine_rate_closest(struct clk_hw *hw,
struct clk_rate_request *req);
void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
+void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
+ unsigned long max_rate);

static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
{

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2015-07-17 11:17:15

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)



On 16/07/15 20:31, Stephen Boyd wrote:
> On 07/16, Sudeep Holla wrote:
>> On 08/07/15 02:46, Stephen Boyd wrote:
>>>
>>> Yes struct clk would have min/max, and struct clk_core would have
>>> min/max. Then some sort of provider API (or possibly even
>>> clk_init_data) would take the min/max fields and copy them over
>>> to struct clk_core. Then during set_rate operations we would
>>> aggregate the constraints from struct clk like we already do and
>>> add in the constrains in struct clk_core.
>>>
>>> One downside to adding new fields to clk_init_data is that there
>>> are drivers out there that aren't initializing that structure to
>>> 0, and they're putting it on the stack, so stack junk can come
>>> through. Furthermore, min/max would mean that every driver needs
>>> to specify some large number for max or we have to special case
>>> min == max == 0 and ignore it. Somehow it needs to be opt-in. If
>>> we want to go down the clk_init_data route then perhaps we need
>>> some sort of rate_constraint struct pointer in there that drivers
>>> can optionally setup.
>>>
>>> struct clk_rate_constraint {
>>> unsigned long min;
>>> unsigned long max;
>>> };
>>>
>>> struct clk_init_data {
>>> ...
>>> struct clk_rate_constraint *rate_constraint;
>>> };
>>>
>>> I haven't thought it through completely, but I can probably write
>>> up some patch tomorrow after I sleep on it.
>>>
>>
>> I am hoping to get this series for v4.3. In order to avoid using
>> consumer API, I can revert back to the min,max check I had in the
>> round_rate earlier if that's fine with you ? Let me know so that I can
>> post the next version based on that. All the other comments are already
>> addressed.
>
> Ok. I'm fine with the consumer API being used, but it would be
> nice if we didn't have to do so. Try out the patch below,
> hopefully it's good enough for your purposes. It may need to be
> more robust, and we may still want to use the init_data structure
> to avoid races with providers and consumers, but we can leave
> that for later after sweeping all the structure users.
>

Agreed, I would avoid using clk consumer API or use it with TODO so that
I remember to remove it soon. Anyways, thanks for the patch, I tested it
and works fine to me. You can add Tested-by if you decide to push it.

>>
>> Also since this series depends on SCPI, I was thinking to get it merged
>> via ARM-SoC, but that might conflict with the round_rate prototype
>> change. Do do plan to share a stable base with arm-soc guys or you
>> expect all the changes to be contained in clk tree ?
>>
>
> We can share a stable branch for the determine_rate change with
> arm-soc. We already have it on a separate branch but haven't
> published it so far because nobody has asked.
>

determine_rate change shouldn't affect SCPI clock driver but I remember
seeing round_rate change too on the list which returns value using the
argument from Boris. Is that planned for v4.3 ? I would need the stable
branch from this clk_hw_set_rate_range if you decide to push. Let me
know your preferences. I will post the updated version of the patch
accordingly.

Regards,
Sudeep

2015-07-17 18:13:57

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

On 07/17/2015 04:17 AM, Sudeep Holla wrote:
>
>
> On 16/07/15 20:31, Stephen Boyd wrote:
>> On 07/16, Sudeep Holla wrote:
>>> On 08/07/15 02:46, Stephen Boyd wrote:
>>>>
>>>> Yes struct clk would have min/max, and struct clk_core would have
>>>> min/max. Then some sort of provider API (or possibly even
>>>> clk_init_data) would take the min/max fields and copy them over
>>>> to struct clk_core. Then during set_rate operations we would
>>>> aggregate the constraints from struct clk like we already do and
>>>> add in the constrains in struct clk_core.
>>>>
>>>> One downside to adding new fields to clk_init_data is that there
>>>> are drivers out there that aren't initializing that structure to
>>>> 0, and they're putting it on the stack, so stack junk can come
>>>> through. Furthermore, min/max would mean that every driver needs
>>>> to specify some large number for max or we have to special case
>>>> min == max == 0 and ignore it. Somehow it needs to be opt-in. If
>>>> we want to go down the clk_init_data route then perhaps we need
>>>> some sort of rate_constraint struct pointer in there that drivers
>>>> can optionally setup.
>>>>
>>>> struct clk_rate_constraint {
>>>> unsigned long min;
>>>> unsigned long max;
>>>> };
>>>>
>>>> struct clk_init_data {
>>>> ...
>>>> struct clk_rate_constraint *rate_constraint;
>>>> };
>>>>
>>>> I haven't thought it through completely, but I can probably write
>>>> up some patch tomorrow after I sleep on it.
>>>>
>>>
>>> I am hoping to get this series for v4.3. In order to avoid using
>>> consumer API, I can revert back to the min,max check I had in the
>>> round_rate earlier if that's fine with you ? Let me know so that I can
>>> post the next version based on that. All the other comments are already
>>> addressed.
>>
>> Ok. I'm fine with the consumer API being used, but it would be
>> nice if we didn't have to do so. Try out the patch below,
>> hopefully it's good enough for your purposes. It may need to be
>> more robust, and we may still want to use the init_data structure
>> to avoid races with providers and consumers, but we can leave
>> that for later after sweeping all the structure users.
>>
>
> Agreed, I would avoid using clk consumer API or use it with TODO so that
> I remember to remove it soon. Anyways, thanks for the patch, I tested it
> and works fine to me. You can add Tested-by if you decide to push it.

Thanks. I pushed it to -next last night but it probably hasn't shown up yet.

>
>>>
>>> Also since this series depends on SCPI, I was thinking to get it merged
>>> via ARM-SoC, but that might conflict with the round_rate prototype
>>> change. Do do plan to share a stable base with arm-soc guys or you
>>> expect all the changes to be contained in clk tree ?
>>>
>>
>> We can share a stable branch for the determine_rate change with
>> arm-soc. We already have it on a separate branch but haven't
>> published it so far because nobody has asked.
>>
>
> determine_rate change shouldn't affect SCPI clock driver but I remember
> seeing round_rate change too on the list which returns value using the
> argument from Boris. Is that planned for v4.3 ? I would need the stable
> branch from this clk_hw_set_rate_range if you decide to push. Let me
> know your preferences. I will post the updated version of the patch
> accordingly.
>

We're not going to change round_rate() so it sounds like you don't need
a stable branch. But you would need this new consumer API. So you still
need a branch right?

--
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a Linux Foundation Collaborative Project

2015-07-20 08:54:17

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)



On 17/07/15 19:13, Stephen Boyd wrote:
> On 07/17/2015 04:17 AM, Sudeep Holla wrote:

[...]

>>
>> determine_rate change shouldn't affect SCPI clock driver but I remember
>> seeing round_rate change too on the list which returns value using the
>> argument from Boris. Is that planned for v4.3 ? I would need the stable
>> branch from this clk_hw_set_rate_range if you decide to push. Let me
>> know your preferences. I will post the updated version of the patch
>> accordingly.
>>
>
> We're not going to change round_rate() so it sounds like you don't need
> a stable branch. But you would need this new consumer API. So you still
> need a branch right?
>

I am fine either way. If no one else need the stable branch to be shared
with arm-soc, I prefer to use clock consumer API for now to avoid all
the troubles to you guys and switch to provider API later. I will post
it once the both this driver and that provider API is merged, if that's
fine with you ?

Regards,
Sudeep

2015-07-21 18:05:59

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)

On 07/20/2015 01:54 AM, Sudeep Holla wrote:
>
>
> On 17/07/15 19:13, Stephen Boyd wrote:
>> On 07/17/2015 04:17 AM, Sudeep Holla wrote:
>
> [...]
>
>>>
>>> determine_rate change shouldn't affect SCPI clock driver but I remember
>>> seeing round_rate change too on the list which returns value using the
>>> argument from Boris. Is that planned for v4.3 ? I would need the stable
>>> branch from this clk_hw_set_rate_range if you decide to push. Let me
>>> know your preferences. I will post the updated version of the patch
>>> accordingly.
>>>
>>
>> We're not going to change round_rate() so it sounds like you don't need
>> a stable branch. But you would need this new consumer API. So you still
>> need a branch right?
>>
>
> I am fine either way. If no one else need the stable branch to be shared
> with arm-soc, I prefer to use clock consumer API for now to avoid all
> the troubles to you guys and switch to provider API later. I will post
> it once the both this driver and that provider API is merged, if that's
> fine with you ?

Ok. Sounds fine as long as we don't forget.

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

2015-07-22 08:43:20

by Liviu Dudau

[permalink] [raw]
Subject: Re: [PATCH v4 1/8] Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol

Hi Sudeep,

Minor spelling/phrasing corrections:

On Mon, Jun 08, 2015 at 11:39:55AM +0100, Sudeep Holla wrote:
> This patch adds devicetree binding for System Control and Power
> Interface (SCPI) Message Protocol used between the Application Cores(AP)
> and the System Control Processor(SCP). The MHU peripheral provides a
> mechanism for inter-processor communication between SCP's M3 processor
> and AP.
>
> SCP offers control and management of the core/cluster power states,
> various power domain DVFS including the core/cluster, certain system
> clocks configuration, thermal sensors and many others.
>
> Signed-off-by: Sudeep Holla <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> CC: Jassi Brar <[email protected]>
> Cc: Liviu Dudau <[email protected]>
> Cc: Lorenzo Pieralisi <[email protected]>
> Cc: Jon Medhurst (Tixy) <[email protected]>
> Cc: [email protected]
> ---
> Documentation/devicetree/bindings/arm/arm,scpi.txt | 156 +++++++++++++++++++++
> 1 file changed, 156 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt
> new file mode 100644
> index 000000000000..f5f9684e23b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt
> @@ -0,0 +1,156 @@
> +System Control and Power Interface (SCPI) Message Protocol
> +----------------------------------------------------------
> +
> +Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
> +("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
> +by Linux to initiate various system control and power operations.
> +
> +Required properties:
> +
> +- compatible : should be "arm,scpi"
> +- mboxes: List of phandle and mailbox channel specifiers
> + All the channels reserved by remote SCP firmware for use by
> + SCPI message protocol should be specified in any order
> +- shmem : List of phandle pointing to the shared memory(SHM) area between the
> + processors using these mailboxes for IPC, one for each mailbox
> + SHM can be any memory reserved for the purpose of this communication
> + between the processors.
> +
> +See Documentation/devicetree/bindings/mailbox/mailbox.txt
> +for more details about the generic mailbox controller and
> +client driver bindings.
> +
> +Clock bindings for the clocks based on SCPI Message Protocol
> +------------------------------------------------------------
> +
> +This binding uses the common clock binding[1].
> +
> +Container Node
> +==============
> +Required properties:
> +- compatible : should be "arm,scpi-clocks"
> + All the clocks provided by SCP firmware via SCPI message
> + protocol much be listed as sub-nodes under this node.
> +
> +Sub-nodes
> +=========
> +Required properties:
> +- compatible : shall include one of the following
> + "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
> + These clocks don't provide the full range between the limits
... don't provide an entire range of values between the limits
> + but only discrete points within the range. The firmware
> + provides the mapping for each such operating frequency and the
> + index associated with it. The firmware also manages the
> + voltage scaling appropriately with the clock scaling.
> + "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
> + range within the specified range. The firmware provides the
range of values within a specified range. .....
> + supported range for each clock.
> +
> +Other required properties for all clocks(all from common clock binding):
> +- #clock-cells : should be set to 1 as each of the SCPI clocks have multiple
> + outputs. The clock specifier will be the index to an entry in the list
> + of output clocks.
> +- clock-output-names : shall be the corresponding names of the outputs.
> +- clock-indices: The identifyng number for the clocks(clock_id) in the node as

s/identifyng/identifying/

> + expected by the firmware. It can be non linear and hence provide the
> + mapping of identifiers into the clock-output-names array.
> +
> +SRAM and Shared Memory for SCPI
> +-------------------------------
> +
> +A small area of SRAM is reserved for SCPI communication between application
> +processors and SCP.
> +
> +Required properties:
> +- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
> +
> +The rest of the properties should follow the generic mmio-sram discription

s/discription/description/

> +found in ../../misc/sysram.txt
> +
> +Each sub-node represents the reserved area for SCPI.
> +
> +Required sub-node properties:
> +- reg : The base offset and size of the reserved area with the SRAM
> +- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
> + shared memory on Juno platforms
> +
> +[0] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Example:
> +
> +sram: sram@50000000 {
> + compatible = "arm,juno-sram-ns", "mmio-sram";
> + reg = <0x0 0x50000000 0x0 0x10000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x50000000 0x10000>;
> +
> + cpu_scp_lpri: scp-shmem@0 {
> + compatible = "arm,juno-scp-shmem";
> + reg = <0x0 0x200>;
> + };
> +
> + cpu_scp_hpri: scp-shmem@200 {
> + compatible = "arm,juno-scp-shmem";
> + reg = <0x200 0x200>;
> + };
> +};
> +
> +mailbox: mailbox0@40000000 {
> + ....
> + #mbox-cells = <1>;
> +};
> +
> +scpi_protocol: scpi@2e000000 {
> + compatible = "arm,scpi";
> + mboxes = <&mailbox 0 &mailbox 1>;
> + shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
> +
> + clocks {
> + compatible = "arm,scpi-clocks";
> +
> + scpi_dvfs: scpi_clocks@0 {
> + compatible = "arm,scpi-dvfs-clocks";
> + #clock-cells = <1>;
> + clock-indices = <0>, <1>, <2>;
> + clock-output-names = "vbig", "vlittle", "vgpu";
> + };
> + scpi_clk: scpi_clocks@3 {
> + compatible = "arm,scpi-variable-clocks";
> + #clock-cells = <1>;
> + clock-indices = <3>, <4>;
> + clock-output-names = "pxlclk0", "pxlclk1";
> + };
> + };
> +};
> +
> +cpu@0 {
> + ...
> + reg = <0 0>;
> + clocks = <&scpi_dvfs 0>;
> + clock-names = "vbig";
> +};
> +
> +hdlcd@7ff60000 {
> + ...
> + reg = <0 0x7ff60000 0 0x1000>;
> + clocks = <&scpi_clk 1>;
> + clock-names = "pxlclk";
> +};
> +
> +In the above example, the #clock-cells is set to 1 as required.
> +scpi_dvfs has 3 output clocks namely: vbig, vlittle and vgpu with 0, 1
> +and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 and
> +pxlclk1 with 3 and 4 as clock-indices.
> +
> +The first consumer in the example is cpu@0 and it has vbig as input clock.
> +The index '0' in the clock specifier here points to the first entry in the
> +output clocks of scpi_dvfs for which clock_id asrequired by the firmware

s/asrequired/as required/

> +is 0.
> +
> +Similarly the second example is hdlcd@7ff60000 and it has pxlclk0 as input
> +clock. The index '1' in the clock specifier here points to the second entry
> +in the output clocks of scpi_clocks for which clock_id as required by the
> +firmware is 4.

This paragraph doesn't match the example. pxlclk0 is index '0'.

Best regards,
Liviu

> --
> 1.9.1
>

--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯

2015-07-22 09:25:17

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 1/8] Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol

Hi Liviu,

On 22/07/15 09:43, Liviu Dudau wrote:
> Hi Sudeep,
>
> Minor spelling/phrasing corrections:
>

Thanks for the review, all fixed locally now. I will soon post new
version. Can you provide ACKs on the Juno DTS files if you are happy
with it ?

Hi Mark,

Sorry for the nag, but I would like to get feedback(if any) before I
post new version.

Regards,
Sudeep

2015-07-22 09:55:48

by Mark Rutland

[permalink] [raw]
Subject: Re: [PATCH v4 1/8] Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol

Hi,

This generally looks fine, but I believe you've misunderstood the usage
of clock-indices, and I think that your usage of clock-specifiers is
somewhat confusing.

More on that below.

On Mon, Jun 08, 2015 at 11:39:55AM +0100, Sudeep Holla wrote:
> This patch adds devicetree binding for System Control and Power
> Interface (SCPI) Message Protocol used between the Application Cores(AP)
> and the System Control Processor(SCP). The MHU peripheral provides a
> mechanism for inter-processor communication between SCP's M3 processor
> and AP.
>
> SCP offers control and management of the core/cluster power states,
> various power domain DVFS including the core/cluster, certain system
> clocks configuration, thermal sensors and many others.
>
> Signed-off-by: Sudeep Holla <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> CC: Jassi Brar <[email protected]>
> Cc: Liviu Dudau <[email protected]>
> Cc: Lorenzo Pieralisi <[email protected]>
> Cc: Jon Medhurst (Tixy) <[email protected]>
> Cc: [email protected]
> ---
> Documentation/devicetree/bindings/arm/arm,scpi.txt | 156 +++++++++++++++++++++
> 1 file changed, 156 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt
> new file mode 100644
> index 000000000000..f5f9684e23b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt
> @@ -0,0 +1,156 @@
> +System Control and Power Interface (SCPI) Message Protocol
> +----------------------------------------------------------
> +
> +Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
> +("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
> +by Linux to initiate various system control and power operations.
> +
> +Required properties:
> +
> +- compatible : should be "arm,scpi"
> +- mboxes: List of phandle and mailbox channel specifiers
> + All the channels reserved by remote SCP firmware for use by
> + SCPI message protocol should be specified in any order
> +- shmem : List of phandle pointing to the shared memory(SHM) area between the
> + processors using these mailboxes for IPC, one for each mailbox
> + SHM can be any memory reserved for the purpose of this communication
> + between the processors.
> +
> +See Documentation/devicetree/bindings/mailbox/mailbox.txt
> +for more details about the generic mailbox controller and
> +client driver bindings.
> +
> +Clock bindings for the clocks based on SCPI Message Protocol
> +------------------------------------------------------------
> +
> +This binding uses the common clock binding[1].
> +
> +Container Node
> +==============
> +Required properties:
> +- compatible : should be "arm,scpi-clocks"
> + All the clocks provided by SCP firmware via SCPI message
> + protocol much be listed as sub-nodes under this node.
> +
> +Sub-nodes
> +=========
> +Required properties:
> +- compatible : shall include one of the following
> + "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
> + These clocks don't provide the full range between the limits
> + but only discrete points within the range. The firmware
> + provides the mapping for each such operating frequency and the
> + index associated with it. The firmware also manages the
> + voltage scaling appropriately with the clock scaling.
> + "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
> + range within the specified range. The firmware provides the
> + supported range for each clock.
> +
> +Other required properties for all clocks(all from common clock binding):
> +- #clock-cells : should be set to 1 as each of the SCPI clocks have multiple
> + outputs. The clock specifier will be the index to an entry in the list
> + of output clocks.

Huh? That's somewhat a circular definition.

What does that number correspond to in the HW? If it's just the number
that the FW expects, that's a reasonable definition.

> +- clock-output-names : shall be the corresponding names of the outputs.

This is mandatory? What is it used for?

> +- clock-indices: The identifyng number for the clocks(clock_id) in the node as

s/identifyng/identifying/

> + expected by the firmware. It can be non linear and hence provide the
> + mapping of identifiers into the clock-output-names array.
> +
> +SRAM and Shared Memory for SCPI
> +-------------------------------
> +
> +A small area of SRAM is reserved for SCPI communication between application
> +processors and SCP.
> +
> +Required properties:
> +- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
> +
> +The rest of the properties should follow the generic mmio-sram discription
> +found in ../../misc/sysram.txt
> +
> +Each sub-node represents the reserved area for SCPI.
> +
> +Required sub-node properties:
> +- reg : The base offset and size of the reserved area with the SRAM
> +- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
> + shared memory on Juno platforms
> +
> +[0] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Example:
> +
> +sram: sram@50000000 {
> + compatible = "arm,juno-sram-ns", "mmio-sram";
> + reg = <0x0 0x50000000 0x0 0x10000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x50000000 0x10000>;
> +
> + cpu_scp_lpri: scp-shmem@0 {
> + compatible = "arm,juno-scp-shmem";
> + reg = <0x0 0x200>;
> + };
> +
> + cpu_scp_hpri: scp-shmem@200 {
> + compatible = "arm,juno-scp-shmem";
> + reg = <0x200 0x200>;
> + };
> +};
> +
> +mailbox: mailbox0@40000000 {
> + ....
> + #mbox-cells = <1>;
> +};
> +
> +scpi_protocol: scpi@2e000000 {
> + compatible = "arm,scpi";
> + mboxes = <&mailbox 0 &mailbox 1>;
> + shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
> +
> + clocks {
> + compatible = "arm,scpi-clocks";
> +
> + scpi_dvfs: scpi_clocks@0 {
> + compatible = "arm,scpi-dvfs-clocks";
> + #clock-cells = <1>;
> + clock-indices = <0>, <1>, <2>;
> + clock-output-names = "vbig", "vlittle", "vgpu";
> + };
> + scpi_clk: scpi_clocks@3 {
> + compatible = "arm,scpi-variable-clocks";
> + #clock-cells = <1>;
> + clock-indices = <3>, <4>;
> + clock-output-names = "pxlclk0", "pxlclk1";
> + };
> + };
> +};
> +
> +cpu@0 {
> + ...
> + reg = <0 0>;
> + clocks = <&scpi_dvfs 0>;
> + clock-names = "vbig";
> +};
> +
> +hdlcd@7ff60000 {
> + ...
> + reg = <0 0x7ff60000 0 0x1000>;
> + clocks = <&scpi_clk 1>;
> + clock-names = "pxlclk";
> +};
> +
> +In the above example, the #clock-cells is set to 1 as required.
> +scpi_dvfs has 3 output clocks namely: vbig, vlittle and vgpu with 0, 1
> +and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 and
> +pxlclk1 with 3 and 4 as clock-indices.
> +
> +The first consumer in the example is cpu@0 and it has vbig as input clock.
> +The index '0' in the clock specifier here points to the first entry in the
> +output clocks of scpi_dvfs for which clock_id asrequired by the firmware
> +is 0.
> +
> +Similarly the second example is hdlcd@7ff60000 and it has pxlclk0 as input
> +clock. The index '1' in the clock specifier here points to the second entry
> +in the output clocks of scpi_clocks for which clock_id as required by the
> +firmware is 4.

To the best of my knowledge, this is wrong. Per the example in
Documentation/devicetree/bindings/clock/clock-bindings.txt, the
clock-indices apply to the logical value in the clock-specifier.

So <&scpi_clk 3>, <&scpi_clk 4> exist, (and are named "pxlclk0",
"pxlclk1" respectively), but <&scpi_clk 0>, <&scpi_clk 1> do not (or at
least don't have names).

Thanks,
Mark.

2015-07-22 13:28:16

by Liviu Dudau

[permalink] [raw]
Subject: Re: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno

On Mon, Jun 08, 2015 at 11:40:00AM +0100, Sudeep Holla wrote:
> This patch adds support for the MHU mailbox peripheral used on Juno by
> application processors to communicate with remote SCP handling most of
> the CPU/system power management. It also adds the SRAM reserving the
> shared memory and SCPI message protocol using that shared memory.
>
> Cc: Liviu Dudau <[email protected]>
> Cc: Jon Medhurst (Tixy) <[email protected]>
> Signed-off-by: Sudeep Holla <[email protected]>
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 31 +++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/arm/juno-clocks.dtsi | 23 +++++++++++++++++++++++
> 2 files changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index e3ee96036eca..f8069a98da25 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -17,6 +17,18 @@
> };
> };
>
> + mailbox: mhu@2b1f0000 {
> + compatible = "arm,mhu", "arm,primecell";
> + reg = <0x0 0x2b1f0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "mhu_lpri_rx",
> + "mhu_hpri_rx";
> + #mbox-cells = <1>;
> + clocks = <&soc_refclk100mhz>;
> + clock-names = "apb_pclk";
> + };
> +
> gic: interrupt-controller@2c010000 {
> compatible = "arm,gic-400", "arm,cortex-a15-gic";
> reg = <0x0 0x2c010000 0 0x1000>,
> @@ -44,6 +56,25 @@
> <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + sram: sram@2e000000 {
> + compatible = "arm,juno-sram-ns", "mmio-sram";
> + reg = <0x0 0x2e000000 0x0 0x8000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x2e000000 0x8000>;
> +
> + cpu_scp_lpri: scp-shmem@0 {
> + compatible = "arm,juno-scp-shmem";
> + reg = <0x0 0x200>;
> + };
> +
> + cpu_scp_hpri: scp-shmem@200 {
> + compatible = "arm,juno-scp-shmem";
> + reg = <0x200 0x200>;
> + };
> + };
> +
> /include/ "juno-clocks.dtsi"
>
> dma@7ff00000 {
> diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
> index 25352ed943e6..64af7370815a 100644
> --- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
> @@ -42,3 +42,26 @@
> clock-frequency = <400000000>;
> clock-output-names = "faxi_clk";
> };
> +
> + scpi {
> + compatible = "arm,scpi";
> + mboxes = <&mailbox 1>;
> + shmem = <&cpu_scp_hpri>;
> +
> + clocks {
> + compatible = "arm,scpi-clocks";
> +
> + scpi_dvfs: scpi_clocks@0 {
> + compatible = "arm,scpi-dvfs-clocks";
> + #clock-cells = <1>;
> + clock-indices = <0>, <1>, <2>;
> + clock-output-names = "vbig", "vlittle", "vgpu";
> + };
> + scpi_clk: scpi_clocks@3 {
> + compatible = "arm,scpi-variable-clocks";
> + #clock-cells = <1>;
> + clock-indices = <3>, <4>;

Subject to you addressing Mark's comments regarding the indices values (maybe choose
a different property to show the fact that the index is actually an SCPI index
rather than the clock's), you can add my

Acked-by: Liviu Dudau <[email protected]>

Best regards,
Liviu


> + clock-output-names = "pxlclk0", "pxlclk1";
> + };
> + };
> + };
> --
> 1.9.1
>

--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯

2015-07-22 13:31:42

by Liviu Dudau

[permalink] [raw]
Subject: Re: [PATCH v4 7/8] arm64: dts: add CPU topology on Juno

On Mon, Jun 08, 2015 at 11:40:01AM +0100, Sudeep Holla wrote:
> This patch adds CPU topology on Juno. It will be useful for ther other
> IP blocks depending on this topology.
>
> Cc: Liviu Dudau <[email protected]>
> Cc: Jon Medhurst (Tixy) <[email protected]>
> Signed-off-by: Sudeep Holla <[email protected]>
> ---
> arch/arm64/boot/dts/arm/juno-r1.dts | 26 ++++++++++++++++++++++++++
> arch/arm64/boot/dts/arm/juno.dts | 26 ++++++++++++++++++++++++++
> 2 files changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
> index c62751153a4f..69130840c6cd 100644
> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
> @@ -34,6 +34,32 @@
> #address-cells = <2>;
> #size-cells = <0>;
>
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&A57_0>;
> + };
> + core1 {
> + cpu = <&A57_1>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&A53_0>;
> + };
> + core1 {
> + cpu = <&A53_1>;
> + };
> + core2 {
> + cpu = <&A53_2>;
> + };
> + core3 {
> + cpu = <&A53_3>;
> + };
> + };
> + };
> +
> A57_0: cpu@0 {
> compatible = "arm,cortex-a57","arm,armv8";
> reg = <0x0 0x0>;
> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> index d7cbdd482a61..ce1128a54c8d 100644
> --- a/arch/arm64/boot/dts/arm/juno.dts
> +++ b/arch/arm64/boot/dts/arm/juno.dts
> @@ -34,6 +34,32 @@
> #address-cells = <2>;
> #size-cells = <0>;
>
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&A57_0>;
> + };
> + core1 {
> + cpu = <&A57_1>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&A53_0>;
> + };
> + core1 {
> + cpu = <&A53_1>;
> + };
> + core2 {
> + cpu = <&A53_2>;
> + };
> + core3 {
> + cpu = <&A53_3>;
> + };
> + };
> + };
> +

Acked-by: Liviu Dudau <[email protected]>

> A57_0: cpu@0 {
> compatible = "arm,cortex-a57","arm,armv8";
> reg = <0x0 0x0>;
> --
> 1.9.1
>

--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯

2015-07-22 13:32:28

by Liviu Dudau

[permalink] [raw]
Subject: Re: [PATCH v4 8/8] arm64: dts: add clock support for all the cpus

On Mon, Jun 08, 2015 at 11:40:02AM +0100, Sudeep Holla wrote:
> This patch adds the CPU clocks so that the CPU DVFS can be enabled.
>
> Cc: Liviu Dudau <[email protected]>
> Cc: Jon Medhurst (Tixy) <[email protected]>
> Signed-off-by: Sudeep Holla <[email protected]>
> ---
> arch/arm64/boot/dts/arm/juno-r1.dts | 6 ++++++
> arch/arm64/boot/dts/arm/juno.dts | 6 ++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
> index 69130840c6cd..5eef4aa0c532 100644
> --- a/arch/arm64/boot/dts/arm/juno-r1.dts
> +++ b/arch/arm64/boot/dts/arm/juno-r1.dts
> @@ -66,6 +66,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A57_L2>;
> + clocks = <&scpi_dvfs 0>;
> };
>
> A57_1: cpu@1 {
> @@ -74,6 +75,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A57_L2>;
> + clocks = <&scpi_dvfs 0>;
> };
>
> A53_0: cpu@100 {
> @@ -82,6 +84,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A53_1: cpu@101 {
> @@ -90,6 +93,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A53_2: cpu@102 {
> @@ -98,6 +102,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A53_3: cpu@103 {
> @@ -106,6 +111,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A57_L2: l2-cache0 {
> diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> index ce1128a54c8d..c02f880584e8 100644
> --- a/arch/arm64/boot/dts/arm/juno.dts
> +++ b/arch/arm64/boot/dts/arm/juno.dts
> @@ -66,6 +66,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A57_L2>;
> + clocks = <&scpi_dvfs 0>;
> };
>
> A57_1: cpu@1 {
> @@ -74,6 +75,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A57_L2>;
> + clocks = <&scpi_dvfs 0>;
> };
>
> A53_0: cpu@100 {
> @@ -82,6 +84,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A53_1: cpu@101 {
> @@ -90,6 +93,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A53_2: cpu@102 {
> @@ -98,6 +102,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A53_3: cpu@103 {
> @@ -106,6 +111,7 @@
> device_type = "cpu";
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + clocks = <&scpi_dvfs 1>;
> };
>
> A57_L2: l2-cache0 {
> --
> 1.9.1
>

Acked-by: Liviu Dudau <[email protected]>

--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯

2015-07-22 14:19:22

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 3/8] clk: add support for clocks provided by SCP(System Control Processor)



On 21/07/15 19:05, Stephen Boyd wrote:
> On 07/20/2015 01:54 AM, Sudeep Holla wrote:
>>
>>
>> On 17/07/15 19:13, Stephen Boyd wrote:
>>> On 07/17/2015 04:17 AM, Sudeep Holla wrote:
>>
>> [...]
>>
>>>>
>>>> determine_rate change shouldn't affect SCPI clock driver but I remember
>>>> seeing round_rate change too on the list which returns value using the
>>>> argument from Boris. Is that planned for v4.3 ? I would need the stable
>>>> branch from this clk_hw_set_rate_range if you decide to push. Let me
>>>> know your preferences. I will post the updated version of the patch
>>>> accordingly.
>>>>
>>>
>>> We're not going to change round_rate() so it sounds like you don't need
>>> a stable branch. But you would need this new consumer API. So you still
>>> need a branch right?
>>>
>>
>> I am fine either way. If no one else need the stable branch to be shared
>> with arm-soc, I prefer to use clock consumer API for now to avoid all
>> the troubles to you guys and switch to provider API later. I will post
>> it once the both this driver and that provider API is merged, if that's
>> fine with you ?
>
> Ok. Sounds fine as long as we don't forget.
>

It's ready indeed :), will post it when everything is in place.

Regards,
Sudeep

--->8

From 3ddf7fe5b1286efa712d4f2ba8108ce1855f3e74 Mon Sep 17 00:00:00 2001
From: Sudeep Holla <[email protected]>
Date: Fri, 17 Jul 2015 12:19:54 +0100
Subject: [PATCH] clk: scpi: use provider clk_hw_set_rate_range API
instead of
consumer API

SCPI clock provider uses the consumer API clk_set_rate_range to set
min/max rate constraints on the clocks it provides.

Commit c87c640f915a ("clk: Allow providers to configure min/max rates")
added a separate provider API clk_hw_set_rate_range to set the min/max
rate of a clock.

This patch switches away from clk_set_rate_range consumer API to
clk_hw_set_rate_range provider API.

Cc: Stephen Boyd <[email protected]>
Signed-off-by: Sudeep Holla <[email protected]>
---
drivers/clk/clk-scpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
index 06d0558e8f46..f7c8b7a03cfe 100644
--- a/drivers/clk/clk-scpi.c
+++ b/drivers/clk/clk-scpi.c
@@ -174,7 +174,7 @@ scpi_clk_ops_init(struct device *dev, const struct
of_device_id *match,

clk = devm_clk_register(dev, &sclk->hw);
if (!IS_ERR(clk) && max)
- clk_set_rate_range(clk, min, max);
+ clk_hw_set_rate_range(&sclk->hw, min, max);
return clk;
}

--
1.9.1

2015-07-22 15:40:35

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno



On 22/07/15 14:28, Liviu Dudau wrote:
> On Mon, Jun 08, 2015 at 11:40:00AM +0100, Sudeep Holla wrote:
>> This patch adds support for the MHU mailbox peripheral used on Juno by
>> application processors to communicate with remote SCP handling most of
>> the CPU/system power management. It also adds the SRAM reserving the
>> shared memory and SCPI message protocol using that shared memory.
>>
>> Cc: Liviu Dudau <[email protected]>
>> Cc: Jon Medhurst (Tixy) <[email protected]>
>> Signed-off-by: Sudeep Holla <[email protected]>
>> ---
>> arch/arm64/boot/dts/arm/juno-base.dtsi | 31 +++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/arm/juno-clocks.dtsi | 23 +++++++++++++++++++++++
>> 2 files changed, 54 insertions(+)
>>

[..]

>> diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
>> index 25352ed943e6..64af7370815a 100644
>> --- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi
>> +++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
>> @@ -42,3 +42,26 @@
>> clock-frequency = <400000000>;
>> clock-output-names = "faxi_clk";
>> };
>> +
>> + scpi {
>> + compatible = "arm,scpi";
>> + mboxes = <&mailbox 1>;
>> + shmem = <&cpu_scp_hpri>;
>> +
>> + clocks {
>> + compatible = "arm,scpi-clocks";
>> +
>> + scpi_dvfs: scpi_clocks@0 {
>> + compatible = "arm,scpi-dvfs-clocks";
>> + #clock-cells = <1>;
>> + clock-indices = <0>, <1>, <2>;
>> + clock-output-names = "vbig", "vlittle", "vgpu";
>> + };
>> + scpi_clk: scpi_clocks@3 {
>> + compatible = "arm,scpi-variable-clocks";
>> + #clock-cells = <1>;
>> + clock-indices = <3>, <4>;
>
> Subject to you addressing Mark's comments regarding the indices values (maybe choose
> a different property to show the fact that the index is actually an SCPI index
> rather than the clock's), you can add my
>

I don't understand why we need to do that. I will anyway follow up on
that thread.

> Acked-by: Liviu Dudau <[email protected]>

Thanks for all the ACKs.

Regards,
Sudeep

2015-07-22 15:56:29

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 1/8] Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol

Hi Mark,

On 22/07/15 10:55, Mark Rutland wrote:
> Hi,
>
> This generally looks fine, but I believe you've misunderstood the usage
> of clock-indices, and I think that your usage of clock-specifiers is
> somewhat confusing.
>

Thanks for the review.

> More on that below.
>
> On Mon, Jun 08, 2015 at 11:39:55AM +0100, Sudeep Holla wrote:
>> This patch adds devicetree binding for System Control and Power
>> Interface (SCPI) Message Protocol used between the Application Cores(AP)
>> and the System Control Processor(SCP). The MHU peripheral provides a
>> mechanism for inter-processor communication between SCP's M3 processor
>> and AP.
>>
>> SCP offers control and management of the core/cluster power states,
>> various power domain DVFS including the core/cluster, certain system
>> clocks configuration, thermal sensors and many others.
>>
>> Signed-off-by: Sudeep Holla <[email protected]>
>> Cc: Rob Herring <[email protected]>
>> Cc: Mark Rutland <[email protected]>
>> CC: Jassi Brar <[email protected]>
>> Cc: Liviu Dudau <[email protected]>
>> Cc: Lorenzo Pieralisi <[email protected]>
>> Cc: Jon Medhurst (Tixy) <[email protected]>
>> Cc: [email protected]
>> ---
>> Documentation/devicetree/bindings/arm/arm,scpi.txt | 156 +++++++++++++++++++++
>> 1 file changed, 156 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt
>> new file mode 100644
>> index 000000000000..f5f9684e23b3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt
>> @@ -0,0 +1,156 @@
>> +System Control and Power Interface (SCPI) Message Protocol
>> +----------------------------------------------------------
>> +
>> +Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
>> +("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
>> +by Linux to initiate various system control and power operations.
>> +
>> +Required properties:
>> +
>> +- compatible : should be "arm,scpi"
>> +- mboxes: List of phandle and mailbox channel specifiers
>> + All the channels reserved by remote SCP firmware for use by
>> + SCPI message protocol should be specified in any order
>> +- shmem : List of phandle pointing to the shared memory(SHM) area between the
>> + processors using these mailboxes for IPC, one for each mailbox
>> + SHM can be any memory reserved for the purpose of this communication
>> + between the processors.
>> +
>> +See Documentation/devicetree/bindings/mailbox/mailbox.txt
>> +for more details about the generic mailbox controller and
>> +client driver bindings.
>> +
>> +Clock bindings for the clocks based on SCPI Message Protocol
>> +------------------------------------------------------------
>> +
>> +This binding uses the common clock binding[1].
>> +
>> +Container Node
>> +==============
>> +Required properties:
>> +- compatible : should be "arm,scpi-clocks"
>> + All the clocks provided by SCP firmware via SCPI message
>> + protocol much be listed as sub-nodes under this node.
>> +
>> +Sub-nodes
>> +=========
>> +Required properties:
>> +- compatible : shall include one of the following
>> + "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
>> + These clocks don't provide the full range between the limits
>> + but only discrete points within the range. The firmware
>> + provides the mapping for each such operating frequency and the
>> + index associated with it. The firmware also manages the
>> + voltage scaling appropriately with the clock scaling.
>> + "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
>> + range within the specified range. The firmware provides the
>> + supported range for each clock.
>> +
>> +Other required properties for all clocks(all from common clock binding):
>> +- #clock-cells : should be set to 1 as each of the SCPI clocks have multiple
>> + outputs. The clock specifier will be the index to an entry in the list
>> + of output clocks.
>
> Huh? That's somewhat a circular definition.
>
> What does that number correspond to in the HW? If it's just the number
> that the FW expects, that's a reasonable definition.
>

Not exactly. The clock specifier are used by the consumers and they just
indicate the index into the list of clock outputs provided by the clock
provider. The consumers need not know the exact identifier used by the
provider to identify the clock(either via H/W or F/W)

Also since we are using standard definition and method
(of_clk_src_onecell_get) to decode the clock specifier, it's fine IMO.

>> +- clock-output-names : shall be the corresponding names of the outputs.
>
> This is mandatory? What is it used for?
>

Yes it is used while registering the clocks. I can make it optional and
register the clock name may be using compatible and index. I thought it
would be good to mandate meaning full names.

>> +- clock-indices: The identifyng number for the clocks(clock_id) in the node as
>
> s/identifyng/identifying/
>
>> + expected by the firmware. It can be non linear and hence provide the
>> + mapping of identifiers into the clock-output-names array.
>> +
>> +SRAM and Shared Memory for SCPI
>> +-------------------------------
>> +
>> +A small area of SRAM is reserved for SCPI communication between application
>> +processors and SCP.
>> +
>> +Required properties:
>> +- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
>> +
>> +The rest of the properties should follow the generic mmio-sram discription
>> +found in ../../misc/sysram.txt
>> +
>> +Each sub-node represents the reserved area for SCPI.
>> +
>> +Required sub-node properties:
>> +- reg : The base offset and size of the reserved area with the SRAM
>> +- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
>> + shared memory on Juno platforms
>> +
>> +[0] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +Example:
>> +
>> +sram: sram@50000000 {
>> + compatible = "arm,juno-sram-ns", "mmio-sram";
>> + reg = <0x0 0x50000000 0x0 0x10000>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x0 0x50000000 0x10000>;
>> +
>> + cpu_scp_lpri: scp-shmem@0 {
>> + compatible = "arm,juno-scp-shmem";
>> + reg = <0x0 0x200>;
>> + };
>> +
>> + cpu_scp_hpri: scp-shmem@200 {
>> + compatible = "arm,juno-scp-shmem";
>> + reg = <0x200 0x200>;
>> + };
>> +};
>> +
>> +mailbox: mailbox0@40000000 {
>> + ....
>> + #mbox-cells = <1>;
>> +};
>> +
>> +scpi_protocol: scpi@2e000000 {
>> + compatible = "arm,scpi";
>> + mboxes = <&mailbox 0 &mailbox 1>;
>> + shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
>> +
>> + clocks {
>> + compatible = "arm,scpi-clocks";
>> +
>> + scpi_dvfs: scpi_clocks@0 {
>> + compatible = "arm,scpi-dvfs-clocks";
>> + #clock-cells = <1>;
>> + clock-indices = <0>, <1>, <2>;
>> + clock-output-names = "vbig", "vlittle", "vgpu";
>> + };
>> + scpi_clk: scpi_clocks@3 {
>> + compatible = "arm,scpi-variable-clocks";
>> + #clock-cells = <1>;
>> + clock-indices = <3>, <4>;
>> + clock-output-names = "pxlclk0", "pxlclk1";
>> + };
>> + };
>> +};
>> +
>> +cpu@0 {
>> + ...
>> + reg = <0 0>;
>> + clocks = <&scpi_dvfs 0>;
>> + clock-names = "vbig";
>> +};
>> +
>> +hdlcd@7ff60000 {
>> + ...
>> + reg = <0 0x7ff60000 0 0x1000>;
>> + clocks = <&scpi_clk 1>;
>> + clock-names = "pxlclk";
>> +};
>> +
>> +In the above example, the #clock-cells is set to 1 as required.
>> +scpi_dvfs has 3 output clocks namely: vbig, vlittle and vgpu with 0, 1
>> +and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 and
>> +pxlclk1 with 3 and 4 as clock-indices.
>> +
>> +The first consumer in the example is cpu@0 and it has vbig as input clock.
>> +The index '0' in the clock specifier here points to the first entry in the
>> +output clocks of scpi_dvfs for which clock_id asrequired by the firmware
>> +is 0.
>> +
>> +Similarly the second example is hdlcd@7ff60000 and it has pxlclk0 as input
>> +clock. The index '1' in the clock specifier here points to the second entry
>> +in the output clocks of scpi_clocks for which clock_id as required by the
>> +firmware is 4.
>
> To the best of my knowledge, this is wrong. Per the example in
> Documentation/devicetree/bindings/clock/clock-bindings.txt, the
> clock-indices apply to the logical value in the clock-specifier.
>
> So <&scpi_clk 3>, <&scpi_clk 4> exist, (and are named "pxlclk0",
> "pxlclk1" respectively), but <&scpi_clk 0>, <&scpi_clk 1> do not (or at
> least don't have names).
>

That depends, if your clock provider provides a callback for decoding
clock and does this translation, then they can exist. Since SCPI is
using standard/default callback(of_clk_src_onecell_get), only
<&scpi_clk 0>, <&scpi_clk 1> in above example. For any value >=2,
of_clk_src_onecell_get will bail out as we have only 2 clocks registered
from that provider.

Regards,
Sudeep

2015-07-22 16:06:30

by Liviu Dudau

[permalink] [raw]
Subject: Re: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno

On Wed, Jul 22, 2015 at 04:40:30PM +0100, Sudeep Holla wrote:
>
>
> On 22/07/15 14:28, Liviu Dudau wrote:
> > On Mon, Jun 08, 2015 at 11:40:00AM +0100, Sudeep Holla wrote:
> >> This patch adds support for the MHU mailbox peripheral used on Juno by
> >> application processors to communicate with remote SCP handling most of
> >> the CPU/system power management. It also adds the SRAM reserving the
> >> shared memory and SCPI message protocol using that shared memory.
> >>
> >> Cc: Liviu Dudau <[email protected]>
> >> Cc: Jon Medhurst (Tixy) <[email protected]>
> >> Signed-off-by: Sudeep Holla <[email protected]>
> >> ---
> >> arch/arm64/boot/dts/arm/juno-base.dtsi | 31 +++++++++++++++++++++++++++++++
> >> arch/arm64/boot/dts/arm/juno-clocks.dtsi | 23 +++++++++++++++++++++++
> >> 2 files changed, 54 insertions(+)
> >>
>
> [..]
>
> >> diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
> >> index 25352ed943e6..64af7370815a 100644
> >> --- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi
> >> +++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
> >> @@ -42,3 +42,26 @@
> >> clock-frequency = <400000000>;
> >> clock-output-names = "faxi_clk";
> >> };
> >> +
> >> + scpi {
> >> + compatible = "arm,scpi";
> >> + mboxes = <&mailbox 1>;
> >> + shmem = <&cpu_scp_hpri>;
> >> +
> >> + clocks {
> >> + compatible = "arm,scpi-clocks";
> >> +
> >> + scpi_dvfs: scpi_clocks@0 {
> >> + compatible = "arm,scpi-dvfs-clocks";
> >> + #clock-cells = <1>;
> >> + clock-indices = <0>, <1>, <2>;
> >> + clock-output-names = "vbig", "vlittle", "vgpu";
> >> + };
> >> + scpi_clk: scpi_clocks@3 {
> >> + compatible = "arm,scpi-variable-clocks";
> >> + #clock-cells = <1>;
> >> + clock-indices = <3>, <4>;
> >
> > Subject to you addressing Mark's comments regarding the indices values (maybe choose
> > a different property to show the fact that the index is actually an SCPI index
> > rather than the clock's), you can add my
> >
>
> I don't understand why we need to do that. I will anyway follow up on
> that thread.

Because indices are per clock node, i.e. spi_clk should have clock-indices = <0>, <1>.
Of course, you could have a gap in the indices, but that is both awkard and not clearly
explained in this documentation.

The index that you declare here is actually what you pass to SCPI. But the way the device
tree is presented it declares that there are two clock blocks, one for DVFS and one for
PXLCLK. As far as SCPI is concerned there is only one block of clocks, with 3 of them
having a discrete set of values, so we are at the intersection of two concepts.

BTW, for what is worth, the PXLCLK is not really that smooth in its coverage of the range.
It might have more accepted frequency values, but the way it is implemented it tends to
favour VESA clock values and falls back to a really slow algorithm to generate all other
values. Even so, it can fail to find the correct parameters for the PLLs so it will generate
a frequency that is different from the requested one.

Best regards,
Liviu


>
> > Acked-by: Liviu Dudau <[email protected]>
>
> Thanks for all the ACKs.
>
> Regards,
> Sudeep
>

--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯

2015-07-22 16:16:54

by Sudeep Holla

[permalink] [raw]
Subject: Re: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno



On 22/07/15 17:06, Liviu Dudau wrote:
> On Wed, Jul 22, 2015 at 04:40:30PM +0100, Sudeep Holla wrote:
>>
>>
>> On 22/07/15 14:28, Liviu Dudau wrote:
>>> On Mon, Jun 08, 2015 at 11:40:00AM +0100, Sudeep Holla wrote:
>>>> This patch adds support for the MHU mailbox peripheral used on Juno by
>>>> application processors to communicate with remote SCP handling most of
>>>> the CPU/system power management. It also adds the SRAM reserving the
>>>> shared memory and SCPI message protocol using that shared memory.
>>>>
>>>> Cc: Liviu Dudau <[email protected]>
>>>> Cc: Jon Medhurst (Tixy) <[email protected]>
>>>> Signed-off-by: Sudeep Holla <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/arm/juno-base.dtsi | 31 +++++++++++++++++++++++++++++++
>>>> arch/arm64/boot/dts/arm/juno-clocks.dtsi | 23 +++++++++++++++++++++++
>>>> 2 files changed, 54 insertions(+)
>>>>
>>
>> [..]
>>
>>>> diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
>>>> index 25352ed943e6..64af7370815a 100644
>>>> --- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi
>>>> +++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
>>>> @@ -42,3 +42,26 @@
>>>> clock-frequency = <400000000>;
>>>> clock-output-names = "faxi_clk";
>>>> };
>>>> +
>>>> + scpi {
>>>> + compatible = "arm,scpi";
>>>> + mboxes = <&mailbox 1>;
>>>> + shmem = <&cpu_scp_hpri>;
>>>> +
>>>> + clocks {
>>>> + compatible = "arm,scpi-clocks";
>>>> +
>>>> + scpi_dvfs: scpi_clocks@0 {
>>>> + compatible = "arm,scpi-dvfs-clocks";
>>>> + #clock-cells = <1>;
>>>> + clock-indices = <0>, <1>, <2>;
>>>> + clock-output-names = "vbig", "vlittle", "vgpu";
>>>> + };
>>>> + scpi_clk: scpi_clocks@3 {
>>>> + compatible = "arm,scpi-variable-clocks";
>>>> + #clock-cells = <1>;
>>>> + clock-indices = <3>, <4>;
>>>
>>> Subject to you addressing Mark's comments regarding the indices values (maybe choose
>>> a different property to show the fact that the index is actually an SCPI index
>>> rather than the clock's), you can add my
>>>
>>
>> I don't understand why we need to do that. I will anyway follow up on
>> that thread.
>
> Because indices are per clock node, i.e. spi_clk should have clock-indices = <0>, <1>.
> Of course, you could have a gap in the indices, but that is both awkard and not clearly
> explained in this documentation.
>

Hmm, is it not clear ? I am fine to reword it.

clock-indices: The *identifying number* for the clocks(clock_id) in the
node as *expected by the firmware*. It can be non linear and hence
provide the mapping of identifiers into the clock-output-names array.

> The index that you declare here is actually what you pass to SCPI. But the way the device
> tree is presented it declares that there are two clock blocks, one for DVFS and one for
> PXLCLK. As far as SCPI is concerned there is only one block of clocks, with 3 of them
> having a discrete set of values, so we are at the intersection of two concepts.
>

Agreed. The clock-indices is associated with the clock provider which in
this case is SCPI.

The clock specifier is associated with the clock consumer and all it
needs to know is which one in the list of clock output am I referring
to(i.e. the standard definition decoded using of_clk_src_onecell_get

> BTW, for what is worth, the PXLCLK is not really that smooth in its coverage of the range.
> It might have more accepted frequency values, but the way it is implemented it tends to
> favour VESA clock values and falls back to a really slow algorithm to generate all other
> values. Even so, it can fail to find the correct parameters for the PLLs so it will generate
> a frequency that is different from the requested one.

I don't quite get the context of this info here, but thanks for that :).
I think most of the clock providers have this limitation and round_rate
will handle it. Since SCPI specification doesn't provide a mechanism to
query that, we can't handle it. Hopefully we get that in newer versions
of the specification ;)

Regards,
Sudeep

2015-07-22 16:23:29

by Mark Rutland

[permalink] [raw]
Subject: Re: [PATCH v4 1/8] Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol

> >> +Other required properties for all clocks(all from common clock binding):
> >> +- #clock-cells : should be set to 1 as each of the SCPI clocks have multiple
> >> + outputs. The clock specifier will be the index to an entry in the list
> >> + of output clocks.
> >
> > Huh? That's somewhat a circular definition.
> >
> > What does that number correspond to in the HW? If it's just the number
> > that the FW expects, that's a reasonable definition.
> >
>
> Not exactly. The clock specifier are used by the consumers and they just
> indicate the index into the list of clock outputs provided by the clock
> provider. The consumers need not know the exact identifier used by the
> provider to identify the clock(either via H/W or F/W)

Currently the definition is circular because clock-indices is misued. If
you sort that out then this should become grounded and well-defined.

[...]

> >> +scpi_protocol: scpi@2e000000 {
> >> + compatible = "arm,scpi";
> >> + mboxes = <&mailbox 0 &mailbox 1>;
> >> + shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
> >> +
> >> + clocks {
> >> + compatible = "arm,scpi-clocks";
> >> +
> >> + scpi_dvfs: scpi_clocks@0 {
> >> + compatible = "arm,scpi-dvfs-clocks";
> >> + #clock-cells = <1>;
> >> + clock-indices = <0>, <1>, <2>;
> >> + clock-output-names = "vbig", "vlittle", "vgpu";
> >> + };
> >> + scpi_clk: scpi_clocks@3 {
> >> + compatible = "arm,scpi-variable-clocks";
> >> + #clock-cells = <1>;
> >> + clock-indices = <3>, <4>;
> >> + clock-output-names = "pxlclk0", "pxlclk1";
> >> + };
> >> + };
> >> +};
> >> +
> >> +cpu@0 {
> >> + ...
> >> + reg = <0 0>;
> >> + clocks = <&scpi_dvfs 0>;
> >> + clock-names = "vbig";
> >> +};
> >> +
> >> +hdlcd@7ff60000 {
> >> + ...
> >> + reg = <0 0x7ff60000 0 0x1000>;
> >> + clocks = <&scpi_clk 1>;
> >> + clock-names = "pxlclk";
> >> +};
> >> +
> >> +In the above example, the #clock-cells is set to 1 as required.
> >> +scpi_dvfs has 3 output clocks namely: vbig, vlittle and vgpu with 0, 1
> >> +and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 and
> >> +pxlclk1 with 3 and 4 as clock-indices.
> >> +
> >> +The first consumer in the example is cpu@0 and it has vbig as input clock.
> >> +The index '0' in the clock specifier here points to the first entry in the
> >> +output clocks of scpi_dvfs for which clock_id asrequired by the firmware
> >> +is 0.
> >> +
> >> +Similarly the second example is hdlcd@7ff60000 and it has pxlclk0 as input
> >> +clock. The index '1' in the clock specifier here points to the second entry
> >> +in the output clocks of scpi_clocks for which clock_id as required by the
> >> +firmware is 4.
> >
> > To the best of my knowledge, this is wrong. Per the example in
> > Documentation/devicetree/bindings/clock/clock-bindings.txt, the
> > clock-indices apply to the logical value in the clock-specifier.
> >
> > So <&scpi_clk 3>, <&scpi_clk 4> exist, (and are named "pxlclk0",
> > "pxlclk1" respectively), but <&scpi_clk 0>, <&scpi_clk 1> do not (or at
> > least don't have names).
> >
>
> That depends, if your clock provider provides a callback for decoding
> clock and does this translation, then they can exist.

Sure, hence the "(or at least don't have names)".

> Since SCPI is using standard/default callback(of_clk_src_onecell_get),
> only <&scpi_clk 0>, <&scpi_clk 1> in above example. For any value >=2,
> of_clk_src_onecell_get will bail out as we have only 2 clocks
> registered from that provider.

That's in violation of the semantics of clock-indices, which was added
to map from a non-contiguous set of clock-specifier values to a list of
strings. Take a look at of_clk_get_parent_name (which this won't work
with).

Also see Documentation/devicetree/bindings/clock/clock-bindings.txt
(relevant portion duplicated below):

----
clock-indices: If the identifying number for the clocks in the node
is not linear from zero, then this allows the mapping of
identifiers into the clock-output-names array.

For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:

oscillator {
compatible = "myclocktype";
#clock-cells = <1>;
clock-indices = <1>, <3>;
clock-output-names = "clka", "clkb";
}

This ensures we do not have any empty strings in clock-output-names
----

Note that the indices are the clock-specifier values, not the raw HW/FW
values.

Either you should be using <&scpi_clk 3> and <&scpi_clk 4>, or you need
a different property to map your logical indices to raw HW values.

Thanks,
Mark.