Add support for orion5x PCIe controller.
There is Orion-specific errata that config space via CF8/CFC registers
is broken. Workaround documented in errata documented (linked from above
documentation) does not work when DMA is used and instead other
undocumented workaround is needed which maps config space to memory
(and therefore avoids usage of broken CF8/CFC memory mapped registers).
Signed-off-by: Mauri Sandberg <[email protected]>
Cc: Pali Rohár <[email protected]>
---
arch/arm/mach-orion5x/common.c | 13 -------
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pci-mvebu.c | 59 ++++++++++++++++++++++++++++++
3 files changed, 60 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 7bcb41137bbf..9d8be5ce1266 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -231,19 +231,6 @@ void __init orion5x_init_early(void)
void orion5x_setup_wins(void)
{
- /*
- * The PCIe windows will no longer be statically allocated
- * here once Orion5x is migrated to the pci-mvebu driver.
- */
- mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
- ORION_MBUS_PCIE_IO_ATTR,
- ORION5X_PCIE_IO_PHYS_BASE,
- ORION5X_PCIE_IO_SIZE,
- ORION5X_PCIE_IO_BUS_BASE);
- mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
- ORION_MBUS_PCIE_MEM_ATTR,
- ORION5X_PCIE_MEM_PHYS_BASE,
- ORION5X_PCIE_MEM_SIZE);
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
ORION_MBUS_PCI_IO_ATTR,
ORION5X_PCI_IO_PHYS_BASE,
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index b8d96d38064d..a249375837f0 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -5,7 +5,7 @@ menu "PCI controller drivers"
config PCI_MVEBU
tristate "Marvell EBU PCIe controller"
- depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
+ depends on ARCH_MVEBU || ARCH_DOVE || ARCH_ORION5X || COMPILE_TEST
depends on MVEBU_MBUS
depends on ARM
depends on OF
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index c1ffdb06c971..1d3052aa7e49 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -1487,6 +1487,54 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
return 0;
}
+static int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val)
+{
+ *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
+ PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+ PCIE_CONF_REG(where)));
+
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/* Relevant only for Orion-1/Orion-NAS */
+#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
+#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
+#define ORION5X_PCIE_WA_SIZE SZ_16M
+#define ORION_MBUS_PCIE_WA_TARGET 0x04
+#define ORION_MBUS_PCIE_WA_ATTR 0x79
+
+static int mvebu_pcie_child_rd_conf_wa(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val)
+{
+ struct mvebu_pcie *pcie = bus->sysdata;
+ struct mvebu_pcie_port *port;
+
+ port = mvebu_pcie_find_port(pcie, bus, devfn);
+ if (!port)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (!mvebu_pcie_link_up(port))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /*
+ * We only support access to the non-extended configuration
+ * space when using the WA access method (or we would have to
+ * sacrifice 256M of CPU virtual address space.)
+ */
+ if (where >= 0x100) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ return orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val);
+}
+
static int mvebu_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1663,6 +1711,16 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
bridge->align_resource = mvebu_pcie_align_resource;
bridge->map_irq = mvebu_pcie_map_irq;
+ if (of_machine_is_compatible("marvell,orion5x-88f5181")) {
+ dev_info(dev, "Applying Orion-1/Orion-NAS PCIe config read transaction workaround\n");
+
+ mvebu_pcie_child_ops.read = mvebu_pcie_child_rd_conf_wa;
+ mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
+ ORION_MBUS_PCIE_WA_ATTR,
+ ORION5X_PCIE_WA_PHYS_BASE,
+ ORION5X_PCIE_WA_SIZE);
+ }
+
return pci_host_probe(bridge);
}
@@ -1733,6 +1791,7 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = {
{ .compatible = "marvell,armada-370-pcie", },
{ .compatible = "marvell,dove-pcie", },
{ .compatible = "marvell,kirkwood-pcie", },
+ { .compatible = "marvell,orion5x-pcie", },
{},
};
--
2.25.1
On Mon, Jul 18, 2022 at 10:28 PM Mauri Sandberg <[email protected]> wrote:
>
> Add support for orion5x PCIe controller.
>
> There is Orion-specific errata that config space via CF8/CFC registers
> is broken. Workaround documented in errata documented (linked from above
> documentation) does not work when DMA is used and instead other
> undocumented workaround is needed which maps config space to memory
> (and therefore avoids usage of broken CF8/CFC memory mapped registers).
>
> Signed-off-by: Mauri Sandberg <[email protected]>
> Cc: Pali Rohár <[email protected]>
Nice job, glad you managed to figure this out!
> diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
> index 7bcb41137bbf..9d8be5ce1266 100644
> --- a/arch/arm/mach-orion5x/common.c
> +++ b/arch/arm/mach-orion5x/common.c
> @@ -231,19 +231,6 @@ void __init orion5x_init_early(void)
>
> void orion5x_setup_wins(void)
> {
> - /*
> - * The PCIe windows will no longer be statically allocated
> - * here once Orion5x is migrated to the pci-mvebu driver.
> - */
> - mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
> - ORION_MBUS_PCIE_IO_ATTR,
> - ORION5X_PCIE_IO_PHYS_BASE,
> - ORION5X_PCIE_IO_SIZE,
> - ORION5X_PCIE_IO_BUS_BASE);
> - mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
> - ORION_MBUS_PCIE_MEM_ATTR,
> - ORION5X_PCIE_MEM_PHYS_BASE,
> - ORION5X_PCIE_MEM_SIZE);
> mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
> ORION_MBUS_PCI_IO_ATTR,
> ORION5X_PCI_IO_PHYS_BASE,
If the idea is to have the PCI_MVEBU driver only used for the DT based orion5x
machines, but not the legacy board files, I suspect this breaks the legacy
pci driver, unless you move the mbus configuration into the pcie_setup()
function.
> +/* Relevant only for Orion-1/Orion-NAS */
> +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
> +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
You should not need to hardcode these here. The ORION5X_PCIE_WA_PHYS_BASE
should already be part of the DT binding. There is little practical difference
here, but I see no value in taking the shortcut here either.
For the ORION5X_PCIE_WA_VIRT_BASE, you rely on this to match the
definition in arch/arm/mach-orion5x/common.c, and this is rather fragile.
Instead, please use ioremap() to create a mapping at runtime. The ioremap()
implementation on ARM is smart enough to reuse the address from the static
mapping in common.c, but will also keep working if that should go away.
> +#define ORION5X_PCIE_WA_SIZE SZ_16M
> +#define ORION_MBUS_PCIE_WA_TARGET 0x04
> +#define ORION_MBUS_PCIE_WA_ATTR 0x79
> +
> +static int mvebu_pcie_child_rd_conf_wa(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val)
> +{
> + struct mvebu_pcie *pcie = bus->sysdata;
> + struct mvebu_pcie_port *port;
> +
> + port = mvebu_pcie_find_port(pcie, bus, devfn);
> + if (!port)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + if (!mvebu_pcie_link_up(port))
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + /*
> + * We only support access to the non-extended configuration
> + * space when using the WA access method (or we would have to
> + * sacrifice 256M of CPU virtual address space.)
> + */
> + if (where >= 0x100) {
> + *val = 0xffffffff;
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + }
> +
> + return orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val);
> +}
> +
This is probably good enough here, though I think you could also use
the trick from drivers/pci/ecam.c and map each bus at a time.
Arnd
Hello!
On Tuesday 19 July 2022 10:05:28 Arnd Bergmann wrote:
> On Mon, Jul 18, 2022 at 10:28 PM Mauri Sandberg <[email protected]> wrote:
> >
> > Add support for orion5x PCIe controller.
> >
> > There is Orion-specific errata that config space via CF8/CFC registers
> > is broken. Workaround documented in errata documented (linked from above
> > documentation) does not work when DMA is used and instead other
> > undocumented workaround is needed which maps config space to memory
> > (and therefore avoids usage of broken CF8/CFC memory mapped registers).
> >
> > Signed-off-by: Mauri Sandberg <[email protected]>
> > Cc: Pali Rohár <[email protected]>
>
> Nice job, glad you managed to figure this out!
>
> > diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
> > index 7bcb41137bbf..9d8be5ce1266 100644
> > --- a/arch/arm/mach-orion5x/common.c
> > +++ b/arch/arm/mach-orion5x/common.c
> > @@ -231,19 +231,6 @@ void __init orion5x_init_early(void)
> >
> > void orion5x_setup_wins(void)
> > {
> > - /*
> > - * The PCIe windows will no longer be statically allocated
> > - * here once Orion5x is migrated to the pci-mvebu driver.
> > - */
> > - mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
> > - ORION_MBUS_PCIE_IO_ATTR,
> > - ORION5X_PCIE_IO_PHYS_BASE,
> > - ORION5X_PCIE_IO_SIZE,
> > - ORION5X_PCIE_IO_BUS_BASE);
> > - mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
> > - ORION_MBUS_PCIE_MEM_ATTR,
> > - ORION5X_PCIE_MEM_PHYS_BASE,
> > - ORION5X_PCIE_MEM_SIZE);
> > mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
> > ORION_MBUS_PCI_IO_ATTR,
> > ORION5X_PCI_IO_PHYS_BASE,
>
> If the idea is to have the PCI_MVEBU driver only used for the DT based orion5x
> machines, but not the legacy board files, I suspect this breaks the legacy
> pci driver, unless you move the mbus configuration into the pcie_setup()
> function.
>
> > +/* Relevant only for Orion-1/Orion-NAS */
> > +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
> > +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
>
> You should not need to hardcode these here. The ORION5X_PCIE_WA_PHYS_BASE
> should already be part of the DT binding.
Of course! But the issue is that we do not know how to do this DT
binding. I have already wrote email with asking for help in which
property and which format should be this config range defined, but no
answer yet: https://lore.kernel.org/linux-pci/20220710225108.bgedria6igtqpz5l@pali/
> There is little practical difference
> here, but I see no value in taking the shortcut here either.
>
> For the ORION5X_PCIE_WA_VIRT_BASE, you rely on this to match the
> definition in arch/arm/mach-orion5x/common.c, and this is rather fragile.
>
> Instead, please use ioremap() to create a mapping at runtime. The ioremap()
> implementation on ARM is smart enough to reuse the address from the static
> mapping in common.c, but will also keep working if that should go away.
I'm planning to work with Mauri on this, but current blocker is DT.
> > +#define ORION5X_PCIE_WA_SIZE SZ_16M
> > +#define ORION_MBUS_PCIE_WA_TARGET 0x04
> > +#define ORION_MBUS_PCIE_WA_ATTR 0x79
> > +
> > +static int mvebu_pcie_child_rd_conf_wa(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val)
> > +{
> > + struct mvebu_pcie *pcie = bus->sysdata;
> > + struct mvebu_pcie_port *port;
> > +
> > + port = mvebu_pcie_find_port(pcie, bus, devfn);
> > + if (!port)
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > + if (!mvebu_pcie_link_up(port))
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > + /*
> > + * We only support access to the non-extended configuration
> > + * space when using the WA access method (or we would have to
> > + * sacrifice 256M of CPU virtual address space.)
> > + */
> > + if (where >= 0x100) {
> > + *val = 0xffffffff;
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > + }
> > +
> > + return orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val);
> > +}
> > +
>
> This is probably good enough here, though I think you could also use
> the trick from drivers/pci/ecam.c and map each bus at a time.
>
> Arnd
Yes, there are also helper functions like map bus and etc. which could
simplify this code. I'm planning to do cleanups once we have fully
working driver for Orion.
On Tue, Jul 19, 2022 at 11:46 AM Pali Rohár <[email protected]> wrote:
> On Tuesday 19 July 2022 10:05:28 Arnd Bergmann wrote:
> > > +/* Relevant only for Orion-1/Orion-NAS */
> > > +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
> > > +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
> >
> > You should not need to hardcode these here. The ORION5X_PCIE_WA_PHYS_BASE
> > should already be part of the DT binding.
>
> Of course! But the issue is that we do not know how to do this DT
> binding. I have already wrote email with asking for help in which
> property and which format should be this config range defined, but no
> answer yet: https://lore.kernel.org/linux-pci/20220710225108.bgedria6igtqpz5l@pali/
Ah, I had not seen that email. Quoting from there:
> So my question is: How to properly define config space range in device
> tree file? In which device tree property and in which format? Please
> note that this memory range of config space is PCIe root port specific
> and it requires its own MBUS_ID() like memory range of PCIe MEM and PCIe
> IO mapping. Please look e.g. at armada-385.dtsi how are MBUS_ID() used:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-385.dtsi
This is probably a question for Rob as the mvebu driver is a rather special
case. Normally this would just be a 'reg' property of the host bridge,
but I think
in your case the root device is imaginary, and the ports under it are the
actual hardware devices, so you'll probably have to do the same thing as
the armada-385, translating the mbus ranges for the config space in the
"ranges" property of the parent, and then referring to them by PCI
MMIO addresses using the assigned-addresses property to pass the
config-space registers as a second set of registers in addition to the
first set.
> > There is little practical difference
> > here, but I see no value in taking the shortcut here either.
> >
> > For the ORION5X_PCIE_WA_VIRT_BASE, you rely on this to match the
> > definition in arch/arm/mach-orion5x/common.c, and this is rather fragile.
> >
> > Instead, please use ioremap() to create a mapping at runtime. The ioremap()
> > implementation on ARM is smart enough to reuse the address from the static
> > mapping in common.c, but will also keep working if that should go away.
>
> I'm planning to work with Mauri on this, but current blocker is DT.
Ok. It should not be hard to do this first, as you just need to pass the
same physical address that you pass in the mbus setup, but I agree
it's easier to do this afterwards to avoid having to rewrite it again.
> > This is probably good enough here, though I think you could also use
> > the trick from drivers/pci/ecam.c and map each bus at a time.
> >
> Yes, there are also helper functions like map bus and etc. which could
> simplify this code. I'm planning to do cleanups once we have fully
> working driver for Orion.
Ok. This is probably not worth the effort if the old driver doesn't already
do provide access to the high registers.
Arnd
On Tuesday 19 July 2022 12:16:34 Arnd Bergmann wrote:
> On Tue, Jul 19, 2022 at 11:46 AM Pali Rohár <[email protected]> wrote:
> > On Tuesday 19 July 2022 10:05:28 Arnd Bergmann wrote:
> > > > +/* Relevant only for Orion-1/Orion-NAS */
> > > > +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
> > > > +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
> > >
> > > You should not need to hardcode these here. The ORION5X_PCIE_WA_PHYS_BASE
> > > should already be part of the DT binding.
> >
> > Of course! But the issue is that we do not know how to do this DT
> > binding. I have already wrote email with asking for help in which
> > property and which format should be this config range defined, but no
> > answer yet: https://lore.kernel.org/linux-pci/20220710225108.bgedria6igtqpz5l@pali/
>
> Ah, I had not seen that email. Quoting from there:
>
> > So my question is: How to properly define config space range in device
> > tree file? In which device tree property and in which format? Please
> > note that this memory range of config space is PCIe root port specific
> > and it requires its own MBUS_ID() like memory range of PCIe MEM and PCIe
> > IO mapping. Please look e.g. at armada-385.dtsi how are MBUS_ID() used:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-385.dtsi
>
> This is probably a question for Rob as the mvebu driver is a rather special
> case. Normally this would just be a 'reg' property of the host bridge,
> but I think
> in your case the root device is imaginary, and the ports under it are the
> actual hardware devices
yes
> so you'll probably have to do the same thing as
> the armada-385, translating the mbus ranges for the config space in the
> "ranges" property of the parent
Problem is that "ranges" in PCIe are used for specifying MEM and IO
mappings and kernel PCI code does not allow any other type.
> and then referring to them by PCI
> MMIO addresses using the assigned-addresses property to pass the
> config-space registers as a second set of registers in addition to the
> first set.
It is more complicated. PCIe MEM and IO memory ranges are defined in
"soc" node in "pcie-mem-aperture" and "pcie-io-aperture" properties.
These ranges are shared across all PCIe controllers and assigning slices
of these ranges to specific devices is done later by dynamic allocation.
"soc" node is bind to mbus driver (which parse these properties) and
provides API for other kernel drivers for dynamic allocation of memory
from pcie aperture. In pcie node is just indirect reference to PCIe MEM
and IO via MBUS_ID() macro and it is pci-mvebu.c driver who ask mbus
driver for PCIe MEM and IO dynamic allocation.
So because PCIe config space is not of type PCIe MEM nor PCIe IO
(obviously) it cannot use "ranges" property. Because DT pcie nodes use
"reg" property for specifying BDF address, we cannot use neither "reg"
property for specifying memory range of PCIe config space.
And here I'm lost.
My guess is that proper way is to define "pcie-cfg-aperture" in "soc"
node where would be defined physical address range without any binding
to controller, then extend mbus driver to export API also for PCIe CFG
and add code which dynamically assign slice of this range to some
controller. And then use this new API by pci-mvebu.c to access config
space. But pci-mvebu.c needs to know MBUS_ID() attributes which needs to
be defined somewhere in pcie DT node...
> > > There is little practical difference
> > > here, but I see no value in taking the shortcut here either.
> > >
> > > For the ORION5X_PCIE_WA_VIRT_BASE, you rely on this to match the
> > > definition in arch/arm/mach-orion5x/common.c, and this is rather fragile.
> > >
> > > Instead, please use ioremap() to create a mapping at runtime. The ioremap()
> > > implementation on ARM is smart enough to reuse the address from the static
> > > mapping in common.c, but will also keep working if that should go away.
> >
> > I'm planning to work with Mauri on this, but current blocker is DT.
>
> Ok. It should not be hard to do this first, as you just need to pass the
> same physical address that you pass in the mbus setup, but I agree
> it's easier to do this afterwards to avoid having to rewrite it again.
>
> > > This is probably good enough here, though I think you could also use
> > > the trick from drivers/pci/ecam.c and map each bus at a time.
> > >
> > Yes, there are also helper functions like map bus and etc. which could
> > simplify this code. I'm planning to do cleanups once we have fully
> > working driver for Orion.
>
> Ok. This is probably not worth the effort if the old driver doesn't already
> do provide access to the high registers.
>
> Arnd
If we have free 256MB in physical address space, then we can implement
it easily. It is just changing _size_ argument. I'm not sure how much
DDR RAM has Orion, but if only 2GB then we should be fine (remaining 2GB
should be enough for all peripherals + 256MB for PCIe config space).
Main issue is that there is no Orion documentation which would describe
how direct mapping of PCIe config space is working.
(see also https://lore.kernel.org/linux-doc/[email protected]/)
So we can only set "size" of the physical config space mapping and if we
choose smaller size then we cannot access upper registers. I do not see
any option how to specify "offset" for physical config space to allow
mapping just one PCI bus.
What we have under full control is virtual address space mapping, so we
can just map only one PCI bus to virtual address space from large 256MB
physical config address space.
> If we have free 256MB in physical address space, then we can implement
> it easily. It is just changing _size_ argument. I'm not sure how much
> DDR RAM has Orion, but if only 2GB then we should be fine (remaining 2GB
> should be enough for all peripherals + 256MB for PCIe config space).
All the Orion5x devices i've seen have had small amounts of RAM, 64MB,
maybe 128M. It seems very unlikely there are any with 2GB for RAM. So
i don't see a problem with taking 256MB of physical addresses for PCI.
Andrew
On Wed, Jul 20, 2022 at 10:13 AM Pali Rohár <[email protected]> wrote:
>
> On Tuesday 19 July 2022 12:16:34 Arnd Bergmann wrote:
> > On Tue, Jul 19, 2022 at 11:46 AM Pali Rohár <[email protected]> wrote:
> > > On Tuesday 19 July 2022 10:05:28 Arnd Bergmann wrote:
> > > > > +/* Relevant only for Orion-1/Orion-NAS */
> > > > > +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
> > > > > +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
> > > >
> > > > You should not need to hardcode these here. The ORION5X_PCIE_WA_PHYS_BASE
> > > > should already be part of the DT binding.
> > >
> > > Of course! But the issue is that we do not know how to do this DT
> > > binding. I have already wrote email with asking for help in which
> > > property and which format should be this config range defined, but no
> > > answer yet: https://lore.kernel.org/linux-pci/20220710225108.bgedria6igtqpz5l@pali/
> >
> > Ah, I had not seen that email. Quoting from there:
> >
> > > So my question is: How to properly define config space range in device
> > > tree file? In which device tree property and in which format? Please
> > > note that this memory range of config space is PCIe root port specific
> > > and it requires its own MBUS_ID() like memory range of PCIe MEM and PCIe
> > > IO mapping. Please look e.g. at armada-385.dtsi how are MBUS_ID() used:
> > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-385.dtsi
> >
> > This is probably a question for Rob as the mvebu driver is a rather special
> > case. Normally this would just be a 'reg' property of the host bridge,
> > but I think
> > in your case the root device is imaginary, and the ports under it are the
> > actual hardware devices
>
> yes
>
> > so you'll probably have to do the same thing as
> > the armada-385, translating the mbus ranges for the config space in the
> > "ranges" property of the parent
>
> Problem is that "ranges" in PCIe are used for specifying MEM and IO
> mappings and kernel PCI code does not allow any other type.
The kernel does not, but the binding does (well, the original OF PCI
bus supplement does, but the schema currently does not). If there's a
real need to support config space in ranges, then we can relax the
constraints.
Rob
On Wednesday 20 July 2022 11:40:40 Rob Herring wrote:
> On Wed, Jul 20, 2022 at 10:13 AM Pali Rohár <[email protected]> wrote:
> >
> > On Tuesday 19 July 2022 12:16:34 Arnd Bergmann wrote:
> > > On Tue, Jul 19, 2022 at 11:46 AM Pali Rohár <[email protected]> wrote:
> > > > On Tuesday 19 July 2022 10:05:28 Arnd Bergmann wrote:
> > > > > > +/* Relevant only for Orion-1/Orion-NAS */
> > > > > > +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
> > > > > > +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
> > > > >
> > > > > You should not need to hardcode these here. The ORION5X_PCIE_WA_PHYS_BASE
> > > > > should already be part of the DT binding.
> > > >
> > > > Of course! But the issue is that we do not know how to do this DT
> > > > binding. I have already wrote email with asking for help in which
> > > > property and which format should be this config range defined, but no
> > > > answer yet: https://lore.kernel.org/linux-pci/20220710225108.bgedria6igtqpz5l@pali/
> > >
> > > Ah, I had not seen that email. Quoting from there:
> > >
> > > > So my question is: How to properly define config space range in device
> > > > tree file? In which device tree property and in which format? Please
> > > > note that this memory range of config space is PCIe root port specific
> > > > and it requires its own MBUS_ID() like memory range of PCIe MEM and PCIe
> > > > IO mapping. Please look e.g. at armada-385.dtsi how are MBUS_ID() used:
> > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-385.dtsi
> > >
> > > This is probably a question for Rob as the mvebu driver is a rather special
> > > case. Normally this would just be a 'reg' property of the host bridge,
> > > but I think
> > > in your case the root device is imaginary, and the ports under it are the
> > > actual hardware devices
> >
> > yes
> >
> > > so you'll probably have to do the same thing as
> > > the armada-385, translating the mbus ranges for the config space in the
> > > "ranges" property of the parent
> >
> > Problem is that "ranges" in PCIe are used for specifying MEM and IO
> > mappings and kernel PCI code does not allow any other type.
>
> The kernel does not, but the binding does (well, the original OF PCI
> bus supplement does, but the schema currently does not). If there's a
> real need to support config space in ranges, then we can relax the
> constraints.
>
> Rob
Personally, I do not care where definition of address range for config
space would be defined. Just I need to know where to put it and in which
format, so it would be fine for schema checkers, kernel pci core, etc...
https://lore.kernel.org/linux-pci/20220710225108.bgedria6igtqpz5l@pali/
On Wed, Jul 20, 2022 at 6:13 PM Pali Rohár <[email protected]> wrote:
>
> On Tuesday 19 July 2022 12:16:34 Arnd Bergmann wrote:
> > On Tue, Jul 19, 2022 at 11:46 AM Pali Rohár <[email protected]> wrote:
> > so you'll probably have to do the same thing as
> > the armada-385, translating the mbus ranges for the config space in the
> > "ranges" property of the parent
>
> Problem is that "ranges" in PCIe are used for specifying MEM and IO
> mappings and kernel PCI code does not allow any other type.
>
> > and then referring to them by PCI
> > MMIO addresses using the assigned-addresses property to pass the
> > config-space registers as a second set of registers in addition to the
> > first set.
>
> It is more complicated. PCIe MEM and IO memory ranges are defined in
> "soc" node in "pcie-mem-aperture" and "pcie-io-aperture" properties.
> These ranges are shared across all PCIe controllers and assigning slices
> of these ranges to specific devices is done later by dynamic allocation.
> "soc" node is bind to mbus driver (which parse these properties) and
> provides API for other kernel drivers for dynamic allocation of memory
> from pcie aperture. In pcie node is just indirect reference to PCIe MEM
> and IO via MBUS_ID() macro and it is pci-mvebu.c driver who ask mbus
> driver for PCIe MEM and IO dynamic allocation.
>
> So because PCIe config space is not of type PCIe MEM nor PCIe IO
> (obviously) it cannot use "ranges" property. Because DT pcie nodes use
> "reg" property for specifying BDF address, we cannot use neither "reg"
> property for specifying memory range of PCIe config space.
>
> And here I'm lost.
>
> My guess is that proper way is to define "pcie-cfg-aperture" in "soc"
> node where would be defined physical address range without any binding
> to controller, then extend mbus driver to export API also for PCIe CFG
> and add code which dynamically assign slice of this range to some
> controller. And then use this new API by pci-mvebu.c to access config
> space. But pci-mvebu.c needs to know MBUS_ID() attributes which needs to
> be defined somewhere in pcie DT node...
I think you can define a "ranges" property in the parent node that
converts the MBUS address into a fake PCI MEM space address,
and this is what the Armada 385 example does with
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000>
In the child you can refer to this using the "assigned-addresses"
property and then use the "ranges" to ensure that only the actual
IO and MEM space addresses are translated.
The alternative would be to do away with the indirection and make
the orion5x variant be more like a single hostbridge, and getting
rid of the fake parent. This is closer to what orion5x does at the
moment with the old driver, but might be harder to integrate into
the new one.
> > > > There is little practical difference
> > > > here, but I see no value in taking the shortcut here either.
> > > >
> > > > For the ORION5X_PCIE_WA_VIRT_BASE, you rely on this to match the
> > > > definition in arch/arm/mach-orion5x/common.c, and this is rather fragile.
> > > >
> > > > Instead, please use ioremap() to create a mapping at runtime. The ioremap()
> > > > implementation on ARM is smart enough to reuse the address from the static
> > > > mapping in common.c, but will also keep working if that should go away.
> > >
> > > I'm planning to work with Mauri on this, but current blocker is DT.
> >
> > Ok. It should not be hard to do this first, as you just need to pass the
> > same physical address that you pass in the mbus setup, but I agree
> > it's easier to do this afterwards to avoid having to rewrite it again.
> >
> > > > This is probably good enough here, though I think you could also use
> > > > the trick from drivers/pci/ecam.c and map each bus at a time.
> > > >
> > > Yes, there are also helper functions like map bus and etc. which could
> > > simplify this code. I'm planning to do cleanups once we have fully
> > > working driver for Orion.
> >
> > Ok. This is probably not worth the effort if the old driver doesn't already
> > do provide access to the high registers.
> >
> > Arnd
>
> If we have free 256MB in physical address space, then we can implement
> it easily. It is just changing _size_ argument. I'm not sure how much
> DDR RAM has Orion, but if only 2GB then we should be fine (remaining 2GB
> should be enough for all peripherals + 256MB for PCIe config space).
I recently checked the sizes as I was researching which boards are actually
still usable, and I can confirm what Andrew also said. The only one with
256MB is TS409, everything else has 32MB to 128MB.
As I said before, I also see no problem with leaving the smaller mapping,
as we know that nobody has ever used the extended config space on
orion5x with mainline kernels, and we are not trying to support new
hardware.
> So we can only set "size" of the physical config space mapping and if we
> choose smaller size then we cannot access upper registers. I do not see
> any option how to specify "offset" for physical config space to allow
> mapping just one PCI bus.
>
> What we have under full control is virtual address space mapping, so we
> can just map only one PCI bus to virtual address space from large 256MB
> physical config address space.
Right.
Arnd