This series fixes the blanking pack size and the PMS calculation. It then
adds support to allows the DSIM to dynamically DPHY clocks, and support
non-burst mode while allowing the removal of the hard-coded clock values
for the PLL for imx8m mini/nano/plus, and it allows the removal of the
burst-clock device tree entry when burst-mode isn't supported by connected
devices like an HDMI brige. In that event, the HS clock is set to the
value requested by the bridge chip.
This has been tested on both an i.MX8M Nano and i.MX8M Plus, and should
work on i.MX8M Mini as well. Marek Szyprowski has tested it on various
Exynos boards.
Adam Ford (5):
drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]
drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically
drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY
drm: bridge: samsung-dsim: Dynamically configure DPHY timing
drm: bridge: samsung-dsim: Support non-burst mode
Lucas Stach (1):
drm: bridge: samsung-dsim: fix blanking packet size calculation
drivers/gpu/drm/bridge/Kconfig | 1 +
drivers/gpu/drm/bridge/samsung-dsim.c | 143 +++++++++++++++++++++-----
include/drm/bridge/samsung-dsim.h | 4 +
3 files changed, 125 insertions(+), 23 deletions(-)
V6: Squash-in an additional error fix from Lucas Stach regarding the
DPHY calcuations. Remove the dynamic_dphy variable and let
everyone use the new calculations. Move the hs_clock caching
from patch 6 to patch 5 to go along with the DPHY calcuations
since they are now based on the recorded hs_clock rate.
V5: Update error message to dev_info and change them to indicate
what is happening without sounding like an error when optional
device tree entries are missing.
V4: Undo some accidental whitespace changes, rename PS_TO_CYCLE
variables to ps and hz from PS and MHz. Remove if check
before the samsung_dsim_set_phy_ctrl call since it's
unnecessary.
Added additional tested-by and reviewed-by comments.
Squash patches 6 and 7 together since the supporting
non-burst (patch 6) mode doesn't really work until
patch 7 was applied.
V3: When checking if the bust-clock is present, only check for it
in the device tree, and don't check the presence of the
MIPI_DSI_MODE_VIDEO_BURST flag as it breaks an existing Exynos
board.
Add a new patch to the series to select GENERIC_PHY_MIPI_DPHY in
Kconfig otherwise the build breaks on the 32-bit Exynos.
Change vco_min variable name to min_freq
Added tested-by from Chen-Yu Tsai
V2: Instead of using my packet blanking calculation, this integrates
on from Lucas Stach which gets modified later in the series to
cache the value of the HS-clock instead of having to do the
calucations again.
Instead of completely eliminating the PLL clock frequency from
the device tree, this makes it optional to avoid breaking some
Samsung devices. When the samsung,pll-clock-frequency is not
found, it reads the value of the clock named "sclk_mipi"
This also maintains backwards compatibility with older device
trees.
This also changes the DPHY calcuation from a Look-up table,
a reverse engineered algorithm which uses
phy_mipi_dphy_get_default_config to determine the standard
nominal values and calculates the cycles necessary to update
the DPHY timings accordingly.
--
2.39.2
From: Lucas Stach <[email protected]>
Scale the blanking packet sizes to match the ratio between HS clock
and DPI interface clock. The controller seems to do internal scaling
to the number of active lanes, so we don't take those into account.
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Adam Ford <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Tested-by: Frieder Schrempf <[email protected]>
---
drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..2be3b58624c3 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -874,17 +874,29 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
u32 reg;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+ int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8;
+ int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
+ int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
+ int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock;
+
+ /* remove packet overhead when possible */
+ hfp = max(hfp - 6, 0);
+ hbp = max(hbp - 6, 0);
+ hsa = max(hsa - 6, 0);
+
+ dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
+ hfp, hbp, hsa);
+
reg = DSIM_CMD_ALLOW(0xf)
| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
- reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
- | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
+ reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
- | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
+ | DSIM_MAIN_HSA(hsa);
samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
}
reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
--
2.39.2
Make the pll-clock-frequency optional. If it's present, use it
to maintain backwards compatibility with existing hardware. If it
is absent, read clock rate of "sclk_mipi" to determine the rate.
Since it can be optional, change the message from an error to
dev_info.
Signed-off-by: Adam Ford <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Tested-by: Frieder Schrempf <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
---
drivers/gpu/drm/bridge/samsung-dsim.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index bf4b33d2de76..08266303c261 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1712,11 +1712,11 @@ static const struct mipi_dsi_host_ops samsung_dsim_ops = {
};
static int samsung_dsim_of_read_u32(const struct device_node *np,
- const char *propname, u32 *out_value)
+ const char *propname, u32 *out_value, bool optional)
{
int ret = of_property_read_u32(np, propname, out_value);
- if (ret < 0)
+ if (ret < 0 && !optional)
pr_err("%pOF: failed to get '%s' property\n", np, propname);
return ret;
@@ -1726,20 +1726,29 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
+ struct clk *pll_clk;
int ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
- &dsi->pll_clk_rate);
- if (ret < 0)
- return ret;
+ &dsi->pll_clk_rate, 1);
+
+ /* If it doesn't exist, read it from the clock instead of failing */
+ if (ret < 0) {
+ dev_info(dev, "Using sclk_mipi for pll clock frequency\n");
+ pll_clk = devm_clk_get(dev, "sclk_mipi");
+ if (!IS_ERR(pll_clk))
+ dsi->pll_clk_rate = clk_get_rate(pll_clk);
+ else
+ return PTR_ERR(pll_clk);
+ }
ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
- &dsi->burst_clk_rate);
+ &dsi->burst_clk_rate, 0);
if (ret < 0)
return ret;
ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
- &dsi->esc_clk_rate);
+ &dsi->esc_clk_rate, 0);
if (ret < 0)
return ret;
--
2.39.2
On 16.05.2023 01:57, Adam Ford wrote:
> This series fixes the blanking pack size and the PMS calculation. It then
> adds support to allows the DSIM to dynamically DPHY clocks, and support
> non-burst mode while allowing the removal of the hard-coded clock values
> for the PLL for imx8m mini/nano/plus, and it allows the removal of the
> burst-clock device tree entry when burst-mode isn't supported by connected
> devices like an HDMI brige. In that event, the HS clock is set to the
> value requested by the bridge chip.
>
> This has been tested on both an i.MX8M Nano and i.MX8M Plus, and should
> work on i.MX8M Mini as well. Marek Szyprowski has tested it on various
> Exynos boards.
>
> Adam Ford (5):
> drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]
> drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically
> drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY
> drm: bridge: samsung-dsim: Dynamically configure DPHY timing
> drm: bridge: samsung-dsim: Support non-burst mode
>
> Lucas Stach (1):
> drm: bridge: samsung-dsim: fix blanking packet size calculation
>
> drivers/gpu/drm/bridge/Kconfig | 1 +
> drivers/gpu/drm/bridge/samsung-dsim.c | 143 +++++++++++++++++++++-----
> include/drm/bridge/samsung-dsim.h | 4 +
> 3 files changed, 125 insertions(+), 23 deletions(-)
Feel free to add to all patches:
Tested-by: Marek Szyprowski <[email protected]>
> V6: Squash-in an additional error fix from Lucas Stach regarding the
> DPHY calcuations. Remove the dynamic_dphy variable and let
> everyone use the new calculations. Move the hs_clock caching
> from patch 6 to patch 5 to go along with the DPHY calcuations
> since they are now based on the recorded hs_clock rate.
>
> V5: Update error message to dev_info and change them to indicate
> what is happening without sounding like an error when optional
> device tree entries are missing.
>
> V4: Undo some accidental whitespace changes, rename PS_TO_CYCLE
> variables to ps and hz from PS and MHz. Remove if check
> before the samsung_dsim_set_phy_ctrl call since it's
> unnecessary.
> Added additional tested-by and reviewed-by comments.
> Squash patches 6 and 7 together since the supporting
> non-burst (patch 6) mode doesn't really work until
> patch 7 was applied.
>
> V3: When checking if the bust-clock is present, only check for it
> in the device tree, and don't check the presence of the
> MIPI_DSI_MODE_VIDEO_BURST flag as it breaks an existing Exynos
> board.
>
> Add a new patch to the series to select GENERIC_PHY_MIPI_DPHY in
> Kconfig otherwise the build breaks on the 32-bit Exynos.
>
> Change vco_min variable name to min_freq
>
> Added tested-by from Chen-Yu Tsai
>
> V2: Instead of using my packet blanking calculation, this integrates
> on from Lucas Stach which gets modified later in the series to
> cache the value of the HS-clock instead of having to do the
> calucations again.
>
> Instead of completely eliminating the PLL clock frequency from
> the device tree, this makes it optional to avoid breaking some
> Samsung devices. When the samsung,pll-clock-frequency is not
> found, it reads the value of the clock named "sclk_mipi"
> This also maintains backwards compatibility with older device
> trees.
>
> This also changes the DPHY calcuation from a Look-up table,
> a reverse engineered algorithm which uses
> phy_mipi_dphy_get_default_config to determine the standard
> nominal values and calculates the cycles necessary to update
> the DPHY timings accordingly.
>
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
On Tue, May 16, 2023 at 5:57 PM Marek Szyprowski
<[email protected]> wrote:
>
> On 16.05.2023 01:57, Adam Ford wrote:
> > This series fixes the blanking pack size and the PMS calculation. It then
> > adds support to allows the DSIM to dynamically DPHY clocks, and support
> > non-burst mode while allowing the removal of the hard-coded clock values
> > for the PLL for imx8m mini/nano/plus, and it allows the removal of the
> > burst-clock device tree entry when burst-mode isn't supported by connected
> > devices like an HDMI brige. In that event, the HS clock is set to the
> > value requested by the bridge chip.
> >
> > This has been tested on both an i.MX8M Nano and i.MX8M Plus, and should
> > work on i.MX8M Mini as well. Marek Szyprowski has tested it on various
> > Exynos boards.
> >
> > Adam Ford (5):
> > drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]
> > drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically
> > drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY
> > drm: bridge: samsung-dsim: Dynamically configure DPHY timing
> > drm: bridge: samsung-dsim: Support non-burst mode
> >
> > Lucas Stach (1):
> > drm: bridge: samsung-dsim: fix blanking packet size calculation
> >
> > drivers/gpu/drm/bridge/Kconfig | 1 +
> > drivers/gpu/drm/bridge/samsung-dsim.c | 143 +++++++++++++++++++++-----
> > include/drm/bridge/samsung-dsim.h | 4 +
> > 3 files changed, 125 insertions(+), 23 deletions(-)
>
> Feel free to add to all patches:
>
> Tested-by: Marek Szyprowski <[email protected]>
Thanks for all your help testing. I hope the V7 will be the last
attempt. I've fixed the repeated declaration in patch 6, and added
your t-b statements to each of the patches with code changes.
I'm hoping to push V7 in a day or two pending any more feedback.
adam
>
>
> > V6: Squash-in an additional error fix from Lucas Stach regarding the
> > DPHY calcuations. Remove the dynamic_dphy variable and let
> > everyone use the new calculations. Move the hs_clock caching
> > from patch 6 to patch 5 to go along with the DPHY calcuations
> > since they are now based on the recorded hs_clock rate.
> >
> > V5: Update error message to dev_info and change them to indicate
> > what is happening without sounding like an error when optional
> > device tree entries are missing.
> >
> > V4: Undo some accidental whitespace changes, rename PS_TO_CYCLE
> > variables to ps and hz from PS and MHz. Remove if check
> > before the samsung_dsim_set_phy_ctrl call since it's
> > unnecessary.
> > Added additional tested-by and reviewed-by comments.
> > Squash patches 6 and 7 together since the supporting
> > non-burst (patch 6) mode doesn't really work until
> > patch 7 was applied.
> >
> > V3: When checking if the bust-clock is present, only check for it
> > in the device tree, and don't check the presence of the
> > MIPI_DSI_MODE_VIDEO_BURST flag as it breaks an existing Exynos
> > board.
> >
> > Add a new patch to the series to select GENERIC_PHY_MIPI_DPHY in
> > Kconfig otherwise the build breaks on the 32-bit Exynos.
> >
> > Change vco_min variable name to min_freq
> >
> > Added tested-by from Chen-Yu Tsai
> >
> > V2: Instead of using my packet blanking calculation, this integrates
> > on from Lucas Stach which gets modified later in the series to
> > cache the value of the HS-clock instead of having to do the
> > calucations again.
> >
> > Instead of completely eliminating the PLL clock frequency from
> > the device tree, this makes it optional to avoid breaking some
> > Samsung devices. When the samsung,pll-clock-frequency is not
> > found, it reads the value of the clock named "sclk_mipi"
> > This also maintains backwards compatibility with older device
> > trees.
> >
> > This also changes the DPHY calcuation from a Look-up table,
> > a reverse engineered algorithm which uses
> > phy_mipi_dphy_get_default_config to determine the standard
> > nominal values and calculates the cycles necessary to update
> > the DPHY timings accordingly.
> >
>
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>
Hi Adam,
Am Montag, dem 15.05.2023 um 18:57 -0500 schrieb Adam Ford:
> Make the pll-clock-frequency optional. If it's present, use it
> to maintain backwards compatibility with existing hardware. If it
> is absent, read clock rate of "sclk_mipi" to determine the rate.
> Since it can be optional, change the message from an error to
> dev_info.
>
> Signed-off-by: Adam Ford <[email protected]>
> Tested-by: Chen-Yu Tsai <[email protected]>
> Tested-by: Frieder Schrempf <[email protected]>
> Reviewed-by: Frieder Schrempf <[email protected]>
> ---
> drivers/gpu/drm/bridge/samsung-dsim.c | 23 ++++++++++++++++-------
> 1 file changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index bf4b33d2de76..08266303c261 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -1712,11 +1712,11 @@ static const struct mipi_dsi_host_ops samsung_dsim_ops = {
> };
>
> static int samsung_dsim_of_read_u32(const struct device_node *np,
> - const char *propname, u32 *out_value)
> + const char *propname, u32 *out_value, bool optional)
> {
> int ret = of_property_read_u32(np, propname, out_value);
>
> - if (ret < 0)
> + if (ret < 0 && !optional)
> pr_err("%pOF: failed to get '%s' property\n", np, propname);
>
> return ret;
> @@ -1726,20 +1726,29 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
> {
> struct device *dev = dsi->dev;
> struct device_node *node = dev->of_node;
> + struct clk *pll_clk;
> int ret;
>
> ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
> - &dsi->pll_clk_rate);
> - if (ret < 0)
> - return ret;
> + &dsi->pll_clk_rate, 1);
> +
> + /* If it doesn't exist, read it from the clock instead of failing */
> + if (ret < 0) {
> + dev_info(dev, "Using sclk_mipi for pll clock frequency\n");
While this is certainly helpful while debugging the driver, I don't
think it warrants a info print. Remove or downgrade to dev_dbg?
On the other hand the changed driver behavior should be documented in
the devicetree binding by moving "samsung,pll-clock-frequency" into the
optional properties and spelling out which clock rate is used when the
property is absent.
Regards,
Lucas
> + pll_clk = devm_clk_get(dev, "sclk_mipi");
> + if (!IS_ERR(pll_clk))
> + dsi->pll_clk_rate = clk_get_rate(pll_clk);
> + else
> + return PTR_ERR(pll_clk);
> + }
>
> ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
> - &dsi->burst_clk_rate);
> + &dsi->burst_clk_rate, 0);
> if (ret < 0)
> return ret;
>
> ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
> - &dsi->esc_clk_rate);
> + &dsi->esc_clk_rate, 0);
> if (ret < 0)
> return ret;
>
On Wed, May 17, 2023 at 7:56 AM Lucas Stach <[email protected]> wrote:
>
> Hi Adam,
>
> Am Montag, dem 15.05.2023 um 18:57 -0500 schrieb Adam Ford:
> > Make the pll-clock-frequency optional. If it's present, use it
> > to maintain backwards compatibility with existing hardware. If it
> > is absent, read clock rate of "sclk_mipi" to determine the rate.
> > Since it can be optional, change the message from an error to
> > dev_info.
> >
> > Signed-off-by: Adam Ford <[email protected]>
> > Tested-by: Chen-Yu Tsai <[email protected]>
> > Tested-by: Frieder Schrempf <[email protected]>
> > Reviewed-by: Frieder Schrempf <[email protected]>
> > ---
> > drivers/gpu/drm/bridge/samsung-dsim.c | 23 ++++++++++++++++-------
> > 1 file changed, 16 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> > index bf4b33d2de76..08266303c261 100644
> > --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> > @@ -1712,11 +1712,11 @@ static const struct mipi_dsi_host_ops samsung_dsim_ops = {
> > };
> >
> > static int samsung_dsim_of_read_u32(const struct device_node *np,
> > - const char *propname, u32 *out_value)
> > + const char *propname, u32 *out_value, bool optional)
> > {
> > int ret = of_property_read_u32(np, propname, out_value);
> >
> > - if (ret < 0)
> > + if (ret < 0 && !optional)
> > pr_err("%pOF: failed to get '%s' property\n", np, propname);
> >
> > return ret;
> > @@ -1726,20 +1726,29 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
> > {
> > struct device *dev = dsi->dev;
> > struct device_node *node = dev->of_node;
> > + struct clk *pll_clk;
> > int ret;
> >
> > ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
> > - &dsi->pll_clk_rate);
> > - if (ret < 0)
> > - return ret;
> > + &dsi->pll_clk_rate, 1);
> > +
> > + /* If it doesn't exist, read it from the clock instead of failing */
> > + if (ret < 0) {
> > + dev_info(dev, "Using sclk_mipi for pll clock frequency\n");
>
> While this is certainly helpful while debugging the driver, I don't
> think it warrants a info print. Remove or downgrade to dev_dbg?
I can move to dbg.
>
> On the other hand the changed driver behavior should be documented in
> the devicetree binding by moving "samsung,pll-clock-frequency" into the
> optional properties and spelling out which clock rate is used when the
> property is absent.
Once this series is accepted, I was planning on doing a binding patch
which describes the items that are now optional followed by a patch to
add DSI->HDMI for the Beacon boards. I can see the value in putting
the bindings patch in this series instead. I'll add it to the next
revision to cover both items that are now optional.
adam
>
> Regards,
> Lucas
>
> > + pll_clk = devm_clk_get(dev, "sclk_mipi");
> > + if (!IS_ERR(pll_clk))
> > + dsi->pll_clk_rate = clk_get_rate(pll_clk);
> > + else
> > + return PTR_ERR(pll_clk);
> > + }
> >
> > ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
> > - &dsi->burst_clk_rate);
> > + &dsi->burst_clk_rate, 0);
> > if (ret < 0)
> > return ret;
> >
> > ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
> > - &dsi->esc_clk_rate);
> > + &dsi->esc_clk_rate, 0);
> > if (ret < 0)
> > return ret;
> >
>
On Tue, May 16, 2023 at 5:27 AM Adam Ford <[email protected]> wrote:
>
> From: Lucas Stach <[email protected]>
>
> Scale the blanking packet sizes to match the ratio between HS clock
> and DPI interface clock. The controller seems to do internal scaling
> to the number of active lanes, so we don't take those into account.
>
> Signed-off-by: Lucas Stach <[email protected]>
> Signed-off-by: Adam Ford <[email protected]>
> Tested-by: Chen-Yu Tsai <[email protected]>
> Tested-by: Frieder Schrempf <[email protected]>
> ---
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]> # imx8mm-icore
On Tue, May 16, 2023 at 5:27 AM Adam Ford <[email protected]> wrote:
>
> Make the pll-clock-frequency optional. If it's present, use it
> to maintain backwards compatibility with existing hardware. If it
> is absent, read clock rate of "sclk_mipi" to determine the rate.
> Since it can be optional, change the message from an error to
> dev_info.
>
> Signed-off-by: Adam Ford <[email protected]>
> Tested-by: Chen-Yu Tsai <[email protected]>
> Tested-by: Frieder Schrempf <[email protected]>
> Reviewed-by: Frieder Schrempf <[email protected]>
> ---
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]> # imx8mm-icore