From: Claudiu Beznea <[email protected]>
Add basic support for RZ/G3S to be able to boot from SD card, have a
running console port and use GPIOs. RZ/G3S has 82 general-purpose IO
ports. Support for the remaining pin functions (e.g. Ethernet, XSPI)
will be added along with controller specific support.
Signed-off-by: Claudiu Beznea <[email protected]>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 128 +++++++++++++++++++++++-
1 file changed, 126 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index cf2092d9229d..e6389c946f06 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -58,13 +58,19 @@
#define PIN_CFG_IOLH_C BIT(13)
#define PIN_CFG_SOFT_PS BIT(14)
-#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
- PIN_CFG_SR | \
+#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
+ (PIN_CFG_IOLH_##group | \
PIN_CFG_PUPD | \
PIN_CFG_FILONOFF | \
PIN_CFG_FILNUM | \
PIN_CFG_FILCLKSEL)
+#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
+ PIN_CFG_SR)
+
+#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
+ PIN_CFG_SOFT_PS)
+
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
PIN_CFG_FILONOFF | \
PIN_CFG_FILNUM | \
@@ -1330,6 +1336,36 @@ static const u32 r9a07g043_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
};
+static const u32 r9a08g045_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
+ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P1 */
+ RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P2 */
+ RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P3 */
+ RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P4 */
+ RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
+ RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
+ RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P7 */
+ RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P8 */
+ RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P9 */
+ RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P10 */
+ RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
+ RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
+ RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
+ RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
+ RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
+ RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
+ RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
+ RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
+};
+
static const struct {
struct rzg2l_dedicated_configs common[35];
struct rzg2l_dedicated_configs rzg2l_pins[7];
@@ -1416,6 +1452,46 @@ static const struct {
}
};
+static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
+ PIN_CFG_FILCLKSEL)) },
+ { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
+ PIN_CFG_SOFT_PS)) },
+ { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
+ { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
+ { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+};
+
static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
{
unsigned int gpioint;
@@ -1823,6 +1899,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
.iolh_groupb_oi = { 100, 66, 50, 33, },
};
+static const struct rzg2l_hwcfg rzg3s_hwcfg = {
+ .regs = {
+ .pwpr = 0x3000,
+ .sd_ch = 0x3004,
+ },
+ .iolh_groupa_ua = {
+ /* 1v8 power source */
+ [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
+ /* 2v5 power source */
+ [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
+ /* 3v3 power source */
+ [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
+ },
+ .iolh_groupb_ua = {
+ /* 1v8 power source */
+ [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
+ /* 2v5 power source */
+ [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
+ /* 3v3 power source */
+ [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
+ },
+ .iolh_groupc_ua = {
+ /* 1v8 power source */
+ [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
+ /* 2v5 source */
+ [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
+ /* 3v3 power source */
+ [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
+ },
+ .drive_strength_ua = true,
+ .iolh_groupb_oi = { [0 ... 3] = RZG2L_INVALID_IOLH_VAL, },
+ .func_base = 1,
+};
+
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
@@ -1844,6 +1954,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.hwcfg = &rzg2l_hwcfg,
};
+static struct rzg2l_pinctrl_data r9a08g045_data = {
+ .port_pins = rzg2l_gpio_names,
+ .port_pin_configs = r9a08g045_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
+ .dedicated_pins = rzg3s_dedicated_pins,
+ .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
+ .hwcfg = &rzg3s_hwcfg,
+};
+
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
{
.compatible = "renesas,r9a07g043-pinctrl",
@@ -1853,6 +1973,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
.compatible = "renesas,r9a07g044-pinctrl",
.data = &r9a07g044_data,
},
+ {
+ .compatible = "renesas,r9a08g045-pinctrl",
+ .data = &r9a08g045_data,
+ },
{ /* sentinel */ }
};
--
2.39.2
Hi Claudiu,
On Tue, Sep 12, 2023 at 6:53 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> Add basic support for RZ/G3S to be able to boot from SD card, have a
> running console port and use GPIOs. RZ/G3S has 82 general-purpose IO
> ports. Support for the remaining pin functions (e.g. Ethernet, XSPI)
> will be added along with controller specific support.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -1330,6 +1336,36 @@ static const u32 r9a07g043_gpio_configs[] = {
> RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> };
>
> +static const u32 r9a08g045_gpio_configs[] = {
> + RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
> + RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH0)), /* P1 */
P1_0 and P7_0 have IEN functionality.
I don't know how to represent that...
> + RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH0)), /* P2 */
> + RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH0)), /* P3 */
> + RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH0)), /* P4 */
> + RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
> + RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
> + RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH1)), /* P7 */
> + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH1)), /* P8 */
> + RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH1)), /* P9 */
> + RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> + PIN_CFG_IO_VMC_ETH1)), /* P10 */
> + RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
P11_0 does not have IEN functionality.
I don't know how to represent that...
> + RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
> + RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
> + RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
> + RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
> + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
> + RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
> + RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
> +};
> +
> static const struct {
> struct rzg2l_dedicated_configs common[35];
> struct rzg2l_dedicated_configs rzg2l_pins[7];
> @@ -1416,6 +1452,46 @@ static const struct {
> }
> };
>
> +static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
> + { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
> + PIN_CFG_FILCLKSEL)) },
> + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
> + PIN_CFG_SOFT_PS)) },
> + { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
> + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
> + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD0)) },
> + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
> + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD1)) },
> + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD1)) },
> + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD1)) },
> + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD1)) },
> + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
> + PIN_CFG_IO_VMC_SD1)) },
Is there any specific reason you left out the XSPI, Audio clock, and I3C pins?
> +};
> +
> static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
> {
> unsigned int gpioint;
> @@ -1823,6 +1899,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
> .iolh_groupb_oi = { 100, 66, 50, 33, },
> };
>
> +static const struct rzg2l_hwcfg rzg3s_hwcfg = {
> + .regs = {
> + .pwpr = 0x3000,
> + .sd_ch = 0x3004,
> + },
> + .iolh_groupa_ua = {
> + /* 1v8 power source */
> + [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
> + /* 2v5 power source */
> + [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
Can be dropped once zero means invalid.
> + /* 3v3 power source */
> + [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
> + },
> + .iolh_groupb_ua = {
> + /* 1v8 power source */
> + [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
> + /* 2v5 power source */
> + [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
Can be dropped once zero means invalid.
> + /* 3v3 power source */
> + [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
> + },
> + .iolh_groupc_ua = {
> + /* 1v8 power source */
> + [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
> + /* 2v5 source */
> + [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
> + /* 3v3 power source */
> + [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
> + },
> + .drive_strength_ua = true,
> + .iolh_groupb_oi = { [0 ... 3] = RZG2L_INVALID_IOLH_VAL, },
> + .func_base = 1,
> +};
> +
> static struct rzg2l_pinctrl_data r9a07g043_data = {
> .port_pins = rzg2l_gpio_names,
> .port_pin_configs = r9a07g043_gpio_configs,
> @@ -1844,6 +1954,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
> .hwcfg = &rzg2l_hwcfg,
> };
>
> +static struct rzg2l_pinctrl_data r9a08g045_data = {
> + .port_pins = rzg2l_gpio_names,
> + .port_pin_configs = r9a08g045_gpio_configs,
> + .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
> + .dedicated_pins = rzg3s_dedicated_pins,
> + .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
> + .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
> + .hwcfg = &rzg3s_hwcfg,
> +};
> +
> static const struct of_device_id rzg2l_pinctrl_of_table[] = {
> {
> .compatible = "renesas,r9a07g043-pinctrl",
Please add a BUILD_BUG_ON() check for RZ/G3S to the
rzg2l_pinctrl_probe() function, as is done for the other SoCs in
the family.
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Claudiu,
On Tue, Sep 26, 2023 at 12:58 PM claudiu beznea
<[email protected]> wrote:
> On 21.09.2023 17:58, Geert Uytterhoeven wrote:
> > On Tue, Sep 12, 2023 at 6:53 AM Claudiu <[email protected]> wrote:
> >> From: Claudiu Beznea <[email protected]>
> >>
> >> Add basic support for RZ/G3S to be able to boot from SD card, have a
> >> running console port and use GPIOs. RZ/G3S has 82 general-purpose IO
> >> ports. Support for the remaining pin functions (e.g. Ethernet, XSPI)
> >> will be added along with controller specific support.
> >>
> >> Signed-off-by: Claudiu Beznea <[email protected]>
> >
> > Thanks for your patch!
> >
> >> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> @@ -1330,6 +1336,36 @@ static const u32 r9a07g043_gpio_configs[] = {
> >> RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> >> };
> >>
> >> +static const u32 r9a08g045_gpio_configs[] = {
> >> + RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
> >> + RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> >> + PIN_CFG_IO_VMC_ETH0)), /* P1 */
> >
> > P1_0 and P7_0 have IEN functionality.
> > I don't know how to represent that...
>
> I think Prabhakar's series at [1] may help (or make a step forward) in
> supporting this. I have in mind to wait for it and adapt RZ/G3S afterwards.
OK.
> [1]
> https://lore.kernel.org/all/[email protected]/
> > Is there any specific reason you left out the XSPI, Audio clock, and I3C pins?
>
> I kept only the necessary support for booting and having SDs, GPIO
> functional as a way of proving that all that has been added has been tested
> (similar to clock support). Thus, with e.g. XSPI support I will add at the
> same time clocks and pinctrl.
IC. I all fairness, you did write in your patch description that support
for e.g. XSPI will be added later, so I'm to blame here.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi, Geert,
On 21.09.2023 17:58, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Tue, Sep 12, 2023 at 6:53 AM Claudiu <[email protected]> wrote:
>> From: Claudiu Beznea <[email protected]>
>>
>> Add basic support for RZ/G3S to be able to boot from SD card, have a
>> running console port and use GPIOs. RZ/G3S has 82 general-purpose IO
>> ports. Support for the remaining pin functions (e.g. Ethernet, XSPI)
>> will be added along with controller specific support.
>>
>> Signed-off-by: Claudiu Beznea <[email protected]>
>
> Thanks for your patch!
>
>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> @@ -1330,6 +1336,36 @@ static const u32 r9a07g043_gpio_configs[] = {
>> RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
>> };
>>
>> +static const u32 r9a08g045_gpio_configs[] = {
>> + RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P1 */
>
> P1_0 and P7_0 have IEN functionality.
> I don't know how to represent that...
I think Prabhakar's series at [1] may help (or make a step forward) in
supporting this. I have in mind to wait for it and adapt RZ/G3S afterwards.
[1]
https://lore.kernel.org/all/[email protected]/
>
>> + RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P2 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P3 */
>> + RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH0)), /* P4 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P7 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P8 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P9 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
>> + PIN_CFG_IO_VMC_ETH1)), /* P10 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
>
> P11_0 does not have IEN functionality.
> I don't know how to represent that...
Same here.
>
>> + RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
>> + RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
>> + RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
>> + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
>> + RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
>> + RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
>> +};
>> +
>> static const struct {
>> struct rzg2l_dedicated_configs common[35];
>> struct rzg2l_dedicated_configs rzg2l_pins[7];
>> @@ -1416,6 +1452,46 @@ static const struct {
>> }
>> };
>>
>> +static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
>> + { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
>> + PIN_CFG_FILCLKSEL)) },
>> + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
>> + PIN_CFG_SOFT_PS)) },
>> + { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
>> + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
>> + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD0)) },
>> + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>> + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>> + PIN_CFG_IO_VMC_SD1)) },
>
> Is there any specific reason you left out the XSPI, Audio clock, and I3C pins?
I kept only the necessary support for booting and having SDs, GPIO
functional as a way of proving that all that has been added has been tested
(similar to clock support). Thus, with e.g. XSPI support I will add at the
same time clocks and pinctrl.
>
>> +};
>> +
>> static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
>> {
>> unsigned int gpioint;
>> @@ -1823,6 +1899,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
>> .iolh_groupb_oi = { 100, 66, 50, 33, },
>> };
>>
>> +static const struct rzg2l_hwcfg rzg3s_hwcfg = {
>> + .regs = {
>> + .pwpr = 0x3000,
>> + .sd_ch = 0x3004,
>> + },
>> + .iolh_groupa_ua = {
>> + /* 1v8 power source */
>> + [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
>> + /* 2v5 power source */
>> + [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
>
> Can be dropped once zero means invalid.
>
>> + /* 3v3 power source */
>> + [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
>> + },
>> + .iolh_groupb_ua = {
>> + /* 1v8 power source */
>> + [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
>> + /* 2v5 power source */
>> + [RZG2L_IOLH_IDX_2V5 ... RZG2L_IOLH_IDX_3V3 - 1] = RZG2L_INVALID_IOLH_VAL,
>
> Can be dropped once zero means invalid.
>
>> + /* 3v3 power source */
>> + [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
>> + },
>> + .iolh_groupc_ua = {
>> + /* 1v8 power source */
>> + [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
>> + /* 2v5 source */
>> + [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
>> + /* 3v3 power source */
>> + [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
>> + },
>> + .drive_strength_ua = true,
>> + .iolh_groupb_oi = { [0 ... 3] = RZG2L_INVALID_IOLH_VAL, },
>> + .func_base = 1,
>> +};
>> +
>> static struct rzg2l_pinctrl_data r9a07g043_data = {
>> .port_pins = rzg2l_gpio_names,
>> .port_pin_configs = r9a07g043_gpio_configs,
>> @@ -1844,6 +1954,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
>> .hwcfg = &rzg2l_hwcfg,
>> };
>>
>> +static struct rzg2l_pinctrl_data r9a08g045_data = {
>> + .port_pins = rzg2l_gpio_names,
>> + .port_pin_configs = r9a08g045_gpio_configs,
>> + .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
>> + .dedicated_pins = rzg3s_dedicated_pins,
>> + .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
>> + .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
>> + .hwcfg = &rzg3s_hwcfg,
>> +};
>> +
>> static const struct of_device_id rzg2l_pinctrl_of_table[] = {
>> {
>> .compatible = "renesas,r9a07g043-pinctrl",
>
> Please add a BUILD_BUG_ON() check for RZ/G3S to the
> rzg2l_pinctrl_probe() function, as is done for the other SoCs in
> the family.
Ok.
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
> Geert
>