2023-09-29 09:45:31

by claudiu beznea

Subject: [PATCH v2 02/28] clk: renesas: rzg2l: wait for status bit of SD mux before continuing

From: Claudiu Beznea <[email protected]>

Hardware user manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for
SD clock switching status.

Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <[email protected]>
---

Changes in v2:
- initialized msk

drivers/clk/renesas/rzg2l-cpg.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 9baae7bb7094..5343d04fd70d 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -188,7 +188,8 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
u32 off = GET_REG_OFFSET(hwdata->conf);
u32 shift = GET_SHIFT(hwdata->conf);
const u32 clk_src_266 = 2;
- u32 bitmask;
+ u32 msk, val, bitmask;
+ int ret;

/*
* As per the HW manual, we should not directly switch from 533 MHz to
@@ -202,14 +203,10 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
* the index to value mapping is done by adding 1 to the index.
*/
bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
+ msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
if (index != clk_src_266) {
- u32 msk, val;
- int ret;
-
writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);

- msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
-
ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
!(val & msk), 100,
CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
@@ -221,7 +218,13 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)

writel(bitmask | ((index + 1) << shift), priv->base + off);

- return 0;
+ ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
+ !(val & msk), 100,
+ CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+ if (ret)
+ dev_err(priv->dev, "failed to switch clk source\n");
+
+ return ret;
}

static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
--
2.39.2

2023-10-03 15:15:14

by Geert Uytterhoeven

Subject: Re: [PATCH v2 02/28] clk: renesas: rzg2l: wait for status bit of SD mux before continuing

On Fri, Sep 29, 2023 at 7:39 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> Hardware user manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
> chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
> Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for
> SD clock switching status.
>
> Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
> Signed-off-by: Claudiu Beznea <[email protected]>
> ---
>
> Changes in v2:
> - initialized msk

Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-clk-for-v6.7.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds