v3 -- Replaced "refusal mode" commit with one that gates config
space accesses based on link status (Bjorn)
-- Restrict the brcm_pcie_start_link() code to only those things
related to link-up and put the rest in brcm_pcie_setup()
-- Added commit to change map functions to end with 'map_bus' (Bjorn)
-- s/0x060400/PCI_CLASS_BRIDGE_PCI_NORMAL/ (Pali)
-- Limit config space accesess to 4k window.
-- Remove wording in a commit message that said the regulators
could be endpoint power supplies
V2 -- As v1 included the minimal code to fix a regression. v2 does
the same but adds some improvements suggested by Bjorn.
-- In the unlikely but possible case that some other driver
starts using the port driver's dev_data field, do not overwrite
it but issue an error and return.
-- Functions probe() and resume() do similar operations but
did them in a different order; make this order consistent
for both.
-- New commit to remove forward declarations.
-- New commit for only the PCIe config-space access "refusal mode".
-- brcm_pcie_linkup renamed to brcm_pcie_start_link
-- Add '_noirq' to the brcm_pcie_{suspend,resume} function names
to match the dev_pm_ops names.
-- Changes to commit messages:
o Explain why we are splitting a function in two parts.
o s/RB/Root Port/
NOTE for Bjorn: The two commits "add mechanism .." and "add control ..."
would probably be more clear if they were squashed. They are kept
separate as the first one's code may someday be moved under the Port
driver. As such, there's some churn.
NOTE for Bjorn: There is no hurry on Broadcom's side wrt which
release cycle/phase this patchset is applied. It goes in
when you think it is ready.
V1 -- Resubmission of patchset after original was reverted for a
regression.
A submission [1] was made to enable a PCIe root port to turn on
regulators for downstream devices. It was accepted. Months later, a
regression was discovered on an RPi CM4 [2]. The patchset was reverted
[3] as the fix came too late in the release cycle. The regression in
question is triggered only when the PCIe RC DT node has no root port
subnode, which is a perfectly reasonsable configuration.
The original commits are now being resubmitted with some modifications
to fix the regression. The modifcations on the original commits are
described below (the SHA is that of the original commit):
[830aa6f29f07 PCI: brcmstb: Split brcm_pcie_setup() into two funcs]
NOTE: In the originally submitted patchset, this commit introduced a
regression that was corrected by a subsequent commit in the same
patchset. Let's not do this again.
@@ -1411,6 +1411,10 @@ static int brcm_pcie_probe(struct platform_device *pdev)
if (ret)
goto fail;
+ ret = brcm_pcie_linkup(pcie);
+ if (ret)
+ goto fail;
[67211aadcb4b PCI: brcmstb: Add mechanism to turn on subdev regulators]
NOTE: Not related to the regression, the regulators must be freed whenever
the PCIe tree is dismantled:
@@ -507,6 +507,7 @@ static void pci_subdev_regulators_remove_bus(struct pci_bus *bus)
if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
dev_err(dev, "failed to disable regulators for downstream device\n");
+ regulator_bulk_free(sr->num_supplies, sr->supplies);
dev->driver_data = NULL;
[93e41f3fca3d PCI: brcmstb: Add control of subdevice voltage regulators]
NOTE: If the PCIe RC DT node was missing a Root Port subnode, the PCIe
link-up was skipped. This is the regression. Fix it by attempting
link-up even if the Root Port DT subnode is missing.
@@ -503,11 +503,10 @@ static int pci_subdev_regulators_add_bus(struct pci_bus *bus)
static int brcm_pcie_add_bus(struct pci_bus *bus)
{
- struct device *dev = &bus->dev;
struct brcm_pcie *pcie = (struct brcm_pcie *) bus->sysdata;
int ret;
- if (!dev->of_node || !bus->parent || !pci_is_root_bus(bus->parent))
+ if (!bus->parent || !pci_is_root_bus(bus->parent))
return 0;
ret = pci_subdev_regulators_add_bus(bus);
[1] https://lore.kernel.org/r/[email protected]
[2] https://bugzilla.kernel.org/show_bug.cgi?id=215925
[3] https://lore.kernel.org/linux-pci/[email protected]/
Jim Quinlan (7):
PCI: brcmstb: Remove unnecessary forward declarations
PCI: brcmstb: Split brcm_pcie_setup() into two funcs
PCI: brcmstb: Gate config space access on link status
PCI: brcmstb: Add mechanism to turn on subdev regulators
PCI: brcmstb: Add control of subdevice voltage regulators
PCI: brcmstb: Do not turn off WOL regulators on suspend
PCI: brcmstb: Have .map_bus function names end with 'map_bus'
drivers/pci/controller/pcie-brcmstb.c | 476 ++++++++++++++++++--------
1 file changed, 341 insertions(+), 135 deletions(-)
base-commit: e0dccc3b76fb35bb257b4118367a883073d7390e
--
2.17.1
The forward function declarations in this driver are removed. Besides
that, some constant structure definitions are moved towards a lower
position in the file. There are no changes to the code that has been
moved.
Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 149 +++++++++++++-------------
1 file changed, 72 insertions(+), 77 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index e61058e13818..bd88a0a46c63 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -190,11 +190,6 @@
/* Forward declarations */
struct brcm_pcie;
-static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
-static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
-static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
-static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
-static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
enum {
RGR1_SW_INIT_1,
@@ -223,66 +218,6 @@ struct pcie_cfg_data {
void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
};
-static const int pcie_offsets[] = {
- [RGR1_SW_INIT_1] = 0x9210,
- [EXT_CFG_INDEX] = 0x9000,
- [EXT_CFG_DATA] = 0x9004,
-};
-
-static const int pcie_offsets_bmips_7425[] = {
- [RGR1_SW_INIT_1] = 0x8010,
- [EXT_CFG_INDEX] = 0x8300,
- [EXT_CFG_DATA] = 0x8304,
-};
-
-static const struct pcie_cfg_data generic_cfg = {
- .offsets = pcie_offsets,
- .type = GENERIC,
- .perst_set = brcm_pcie_perst_set_generic,
- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
-};
-
-static const struct pcie_cfg_data bcm7425_cfg = {
- .offsets = pcie_offsets_bmips_7425,
- .type = BCM7425,
- .perst_set = brcm_pcie_perst_set_generic,
- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
-};
-
-static const struct pcie_cfg_data bcm7435_cfg = {
- .offsets = pcie_offsets,
- .type = BCM7435,
- .perst_set = brcm_pcie_perst_set_generic,
- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
-};
-
-static const struct pcie_cfg_data bcm4908_cfg = {
- .offsets = pcie_offsets,
- .type = BCM4908,
- .perst_set = brcm_pcie_perst_set_4908,
- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
-};
-
-static const int pcie_offset_bcm7278[] = {
- [RGR1_SW_INIT_1] = 0xc010,
- [EXT_CFG_INDEX] = 0x9000,
- [EXT_CFG_DATA] = 0x9004,
-};
-
-static const struct pcie_cfg_data bcm7278_cfg = {
- .offsets = pcie_offset_bcm7278,
- .type = BCM7278,
- .perst_set = brcm_pcie_perst_set_7278,
- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
-};
-
-static const struct pcie_cfg_data bcm2711_cfg = {
- .offsets = pcie_offsets,
- .type = BCM2711,
- .perst_set = brcm_pcie_perst_set_generic,
- .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
-};
-
struct brcm_msi {
struct device *dev;
void __iomem *base;
@@ -775,18 +710,6 @@ static void __iomem *brcm_pcie_map_conf32(struct pci_bus *bus, unsigned int devf
return base + DATA_ADDR(pcie);
}
-static struct pci_ops brcm_pcie_ops = {
- .map_bus = brcm_pcie_map_conf,
- .read = pci_generic_config_read,
- .write = pci_generic_config_write,
-};
-
-static struct pci_ops brcm_pcie_ops32 = {
- .map_bus = brcm_pcie_map_conf32,
- .read = pci_generic_config_read32,
- .write = pci_generic_config_write32,
-};
-
static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
{
u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
@@ -1316,6 +1239,66 @@ static int brcm_pcie_remove(struct platform_device *pdev)
return 0;
}
+static const int pcie_offsets[] = {
+ [RGR1_SW_INIT_1] = 0x9210,
+ [EXT_CFG_INDEX] = 0x9000,
+ [EXT_CFG_DATA] = 0x9004,
+};
+
+static const int pcie_offsets_bmips_7425[] = {
+ [RGR1_SW_INIT_1] = 0x8010,
+ [EXT_CFG_INDEX] = 0x8300,
+ [EXT_CFG_DATA] = 0x8304,
+};
+
+static const struct pcie_cfg_data generic_cfg = {
+ .offsets = pcie_offsets,
+ .type = GENERIC,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
+static const struct pcie_cfg_data bcm7425_cfg = {
+ .offsets = pcie_offsets_bmips_7425,
+ .type = BCM7425,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
+static const struct pcie_cfg_data bcm7435_cfg = {
+ .offsets = pcie_offsets,
+ .type = BCM7435,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
+static const struct pcie_cfg_data bcm4908_cfg = {
+ .offsets = pcie_offsets,
+ .type = BCM4908,
+ .perst_set = brcm_pcie_perst_set_4908,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
+static const int pcie_offset_bcm7278[] = {
+ [RGR1_SW_INIT_1] = 0xc010,
+ [EXT_CFG_INDEX] = 0x9000,
+ [EXT_CFG_DATA] = 0x9004,
+};
+
+static const struct pcie_cfg_data bcm7278_cfg = {
+ .offsets = pcie_offset_bcm7278,
+ .type = BCM7278,
+ .perst_set = brcm_pcie_perst_set_7278,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
+};
+
+static const struct pcie_cfg_data bcm2711_cfg = {
+ .offsets = pcie_offsets,
+ .type = BCM2711,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
@@ -1328,6 +1311,18 @@ static const struct of_device_id brcm_pcie_match[] = {
{},
};
+static struct pci_ops brcm_pcie_ops = {
+ .map_bus = brcm_pcie_map_conf,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+};
+
+static struct pci_ops brcm_pcie_ops32 = {
+ .map_bus = brcm_pcie_map_conf32,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+};
+
static int brcm_pcie_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node, *msi_np;
--
2.17.1
Add a mechanism to identify standard PCIe regulators in the DT, allocate
them, and turn them on before the rest of the bus is scanned during
pci_host_probe().
The allocated structure that contains the regulators is stored in the port
driver dev.driver_data field. Here is a point-by-point of how and when
this mechanism is activated:
If:
-- PCIe RC driver sets pci_ops {add,remove)_bus to
pci_subdev_regulators_{add,remove}_bus during its probe.
-- There is a root port DT node under the host bridge DT node.
-- During the RC driver's pci_host_probe() the add_bus callback
is invoked where (bus->parent && pci_is_root_bus(bus->parent)
is true
Then:
-- A struct subdev_regulators structure will be allocated and
assigned to bus->dev.driver_data.
-- regulator_bulk_{get,enable} will be invoked on &bus->dev
and the former will search for and process any
vpcie{12v,3v3,3v3aux}-supply properties that reside in the
root port DT node.
-- The regulators will be turned off/on for any unbind/bind operations.
-- The regulators will be turned off/on for any suspend/resumes, but
only if the RC driver handles this on its own. This will appear
in a later commit for the pcie-brcmstb.c driver.
The unabridged reason for doing this is as follows. We would like the
Broadcom STB PCIe root complex driver (and others) to be able to turn
off/on standard PCIe regulators. Typically, the drivers of endpoint
devices are stock Linux drivers that are not aware that these regulator(s)
exist and must be turned on for the driver to be probed. The simple
solution of course is to turn these regulators on at boot and keep them on.
However, this solution does not satisfy at least three of our usage modes:
1. For example, one customer uses multiple PCIe controllers, but wants
the ability to, by script invoking and unbind, turn any or all of them
and their subdevices off to save power, e.g. when in battery mode.
2. Another example is when a watchdog script discovers that an endpoint
device is in an unresponsive state and would like to unbind, power
toggle, and re-bind just the PCIe endpoint and controller.
3. Of course we also want power turned off during suspend mode. However,
some endpoint devices may be able to "wake" during suspend and we need
to recognise this case and veto the nominal act of turning off its
regulator. Such is the case with Wake-on-LAN and Wake-on-WLAN support
where the PCIe endpoint device needs to be kept powered on in order to
receive network packets and wake the system.
In all of these cases it is advantageous for the PCIe controller to govern
the turning off/on the regulators needed by the endpoint device. The first
two cases can be done by simply unbinding and binding the PCIe controller,
if the controller has control of these regulators.
[1] The 99% configuration of our boards is a single endpoint device
attached to the PCIe controller. I use the term endpoint but it could
possibly mean a switch as well.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 96 +++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 3443206d2a95..1be6e71142d8 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -24,6 +24,7 @@
#include <linux/pci.h>
#include <linux/pci-ecam.h>
#include <linux/printk.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/sizes.h>
#include <linux/slab.h>
@@ -218,6 +219,11 @@ struct pcie_cfg_data {
void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
};
+struct subdev_regulators {
+ unsigned int num_supplies;
+ struct regulator_bulk_data supplies[];
+};
+
struct brcm_msi {
struct device *dev;
void __iomem *base;
@@ -1065,6 +1071,92 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)
return 0;
}
+static const char * const supplies[] = {
+ "vpcie3v3",
+ "vpcie3v3aux",
+ "vpcie12v",
+};
+
+static void *alloc_subdev_regulators(struct device *dev)
+{
+ const size_t size = sizeof(struct subdev_regulators)
+ + sizeof(struct regulator_bulk_data) * ARRAY_SIZE(supplies);
+ struct subdev_regulators *sr;
+ int i;
+
+ sr = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (sr) {
+ sr->num_supplies = ARRAY_SIZE(supplies);
+ for (i = 0; i < ARRAY_SIZE(supplies); i++)
+ sr->supplies[i].supply = supplies[i];
+ }
+
+ return sr;
+}
+
+static int pci_subdev_regulators_add_bus(struct pci_bus *bus)
+{
+ struct device *dev = &bus->dev;
+ struct subdev_regulators *sr;
+ int ret;
+
+ if (!dev->of_node || !bus->parent || !pci_is_root_bus(bus->parent))
+ return 0;
+
+ if (dev->driver_data) {
+ /*
+ * Oops, this is unfortunate. We are using the port
+ * driver's driver_data field to store our regulator info
+ * and it appears that another driver started using it as
+ * well. If so, be a team player do not overwrite it. We
+ * may still be okay if there are no regulators.
+ */
+ dev_err(dev, "root port dev.driver_data non-NULL; something wrong\n");
+ return 0;
+ }
+
+ sr = alloc_subdev_regulators(dev);
+ if (!sr)
+ return -ENOMEM;
+
+ /*
+ * There is not much of a point to return an error as currently it
+ * will cause a WARNING() from pci_alloc_child_bus(). So only
+ * return the error if it is -ENOMEM. Note that we are always
+ * doing a dev_err() for other erros.
+ */
+ ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
+ if (ret) {
+ dev_err(dev, "failed to get regulators for downstream device\n");
+ return 0;
+ }
+
+ ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
+ if (ret) {
+ dev_err(dev, "failed to enable regulators for downstream device\n");
+ regulator_bulk_free(sr->num_supplies, sr->supplies);
+ return 0;
+ }
+
+ dev->driver_data = sr;
+
+ return 0;
+}
+
+static void pci_subdev_regulators_remove_bus(struct pci_bus *bus)
+{
+ struct device *dev = &bus->dev;
+ struct subdev_regulators *sr = dev->driver_data;
+
+ if (!dev->of_node || !sr || !bus->parent || !pci_is_root_bus(bus->parent))
+ return;
+
+ if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
+ dev_err(dev, "failed to disable regulators for downstream device\n");
+ regulator_bulk_free(sr->num_supplies, sr->supplies);
+ dev->driver_data = NULL;
+}
+
/* L23 is a low-power PCIe link state */
static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
{
@@ -1336,12 +1428,16 @@ static struct pci_ops brcm_pcie_ops = {
.map_bus = brcm_pcie_map_conf,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
+ .add_bus = pci_subdev_regulators_add_bus,
+ .remove_bus = pci_subdev_regulators_remove_bus,
};
static struct pci_ops brcm_pcie_ops32 = {
.map_bus = brcm_pcie_map_conf32,
.read = pci_generic_config_read32,
.write = pci_generic_config_write32,
+ .add_bus = pci_subdev_regulators_add_bus,
+ .remove_bus = pci_subdev_regulators_remove_bus,
};
static int brcm_pcie_probe(struct platform_device *pdev)
--
2.17.1
If any downstream device can be a wakeup device, do not turn off the
regulators as the device will need them on.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 54 ++++++++++++++++++++++-----
1 file changed, 44 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index aa199b0a39e2..fc1d36f6094e 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -263,6 +263,7 @@ struct brcm_pcie {
void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
bool regulator_oops;
struct subdev_regulators *sr;
+ bool ep_wakeup_capable;
};
static inline bool is_bmips(const struct brcm_pcie *pcie)
@@ -1283,9 +1284,21 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
pcie->bridge_sw_init_set(pcie, 1);
}
+static int pci_dev_may_wakeup(struct pci_dev *dev, void *data)
+{
+ bool *ret = data;
+
+ if (device_may_wakeup(&dev->dev)) {
+ *ret = true;
+ dev_info(&dev->dev, "disable cancelled for wake-up device\n");
+ }
+ return (int) *ret;
+}
+
static int brcm_pcie_suspend_noirq(struct device *dev)
{
struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
int ret;
brcm_pcie_turn_off(pcie);
@@ -1304,11 +1317,22 @@ static int brcm_pcie_suspend_noirq(struct device *dev)
}
if (pcie->sr) {
- ret = regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
- if (ret) {
- dev_err(dev, "Could not turn off regulators\n");
- reset_control_reset(pcie->rescal);
- return ret;
+ /*
+ * Now turn off the regulators, but if at least one
+ * downstream device is enabled as a wake-up source, do not
+ * turn off regulators.
+ */
+ pcie->ep_wakeup_capable = false;
+ pci_walk_bus(bridge->bus, pci_dev_may_wakeup,
+ &pcie->ep_wakeup_capable);
+ if (!pcie->ep_wakeup_capable) {
+ ret = regulator_bulk_disable(pcie->sr->num_supplies,
+ pcie->sr->supplies);
+ if (ret) {
+ dev_err(dev, "Could not turn off regulators\n");
+ reset_control_reset(pcie->rescal);
+ return ret;
+ }
}
}
clk_disable_unprepare(pcie->clk);
@@ -1352,11 +1376,21 @@ static int brcm_pcie_resume_noirq(struct device *dev)
goto err_reset;
if (pcie->sr) {
- ret = regulator_bulk_enable(pcie->sr->num_supplies,
- pcie->sr->supplies);
- if (ret) {
- dev_err(dev, "Could not turn on regulators\n");
- goto err_reset;
+ if (pcie->ep_wakeup_capable) {
+ /*
+ * We are resuming from a suspend. In the suspend we
+ * did not disable the power supplies, so there is
+ * no need to enable them (and falsely increase their
+ * usage count).
+ */
+ pcie->ep_wakeup_capable = false;
+ } else {
+ ret = regulator_bulk_enable(pcie->sr->num_supplies,
+ pcie->sr->supplies);
+ if (ret) {
+ dev_err(dev, "Could not turn on regulators\n");
+ goto err_reset;
+ }
}
}
--
2.17.1
Our PCIe RC HW has an atypical behavior: if it does not have PCIe link
established between itself and downstream, any subsequent config space
access for a downstream device causes a CPU abort. This commit allows a
config space access for dowwnstream devices only if the PCIe link is up.
Note that config space accesses to the root port are diverted to the RC
registers and are honored regardless of link status.
Some other minor changes are also made: (1) limit the "where" offset to
4K and (2) reject RC accesses if devfn != 0.
Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 15e47e8c94eb..3443206d2a95 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -683,14 +683,18 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
void __iomem *base = pcie->base;
int idx;
- /* Accesses to the RC go right to the RC registers if slot==0 */
+ /* Accesses to the RC go right to the RC registers if !devfn */
if (pci_is_root_bus(bus))
- return PCI_SLOT(devfn) ? NULL : base + where;
+ return devfn ? NULL : base + (where & 0xfff);
+
+ /* An access to our HW w/o link-up will cause a CPU Abort */
+ if (!brcm_pcie_link_up(pcie))
+ return NULL;
/* For devices, write to the config space index register */
idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
- return base + PCIE_EXT_CFG_DATA + where;
+ return base + PCIE_EXT_CFG_DATA + (where & 0xfff);
}
static void __iomem *brcm_pcie_map_conf32(struct pci_bus *bus, unsigned int devfn,
@@ -700,12 +704,16 @@ static void __iomem *brcm_pcie_map_conf32(struct pci_bus *bus, unsigned int devf
void __iomem *base = pcie->base;
int idx;
- /* Accesses to the RC go right to the RC registers if slot==0 */
+ /* Accesses to the RC go right to the RC registers if !devfn */
if (pci_is_root_bus(bus))
- return PCI_SLOT(devfn) ? NULL : base + (where & ~0x3);
+ return devfn ? NULL : base + (where & 0xffc);
+
+ /* An access to our HW w/o link-up will cause a CPU Abort */
+ if (!brcm_pcie_link_up(pcie))
+ return NULL;
/* For devices, write to the config space index register */
- idx = PCIE_ECAM_OFFSET(bus->number, devfn, (where & ~3));
+ idx = PCIE_ECAM_OFFSET(bus->number, devfn, (where & 0xffc));
writel(idx, base + IDX_ADDR(pcie));
return base + DATA_ADDR(pcie);
}
--
2.17.1
Currently, the function does the setup for establishing PCIe link-up
with the downstream device, and it does the actual link-up as well.
The calling sequence is (roughly) the following in the probe:
-> brcm_pcie_probe()
-> brcm_pcie_setup(); /* Set-up and link-up */
-> pci_host_probe(bridge);
This commit splits the setup function in two: brcm_pcie_setup(), which only
does the set-up, and brcm_pcie_start_link(), which only does the link-up.
The reason why we are doing this is to lay a foundation for subsequent
commits so that we can turn on any power regulators, as described in the
root port's DT node, prior to doing link-up. We do this by defining an
add_bus() callback which is invoked during enumeration. At the end of this
patchset the probe function trace will look something like this:
-> brcm_pcie_probe()
-> brcm_pcie_setup(); /* Set-up only */
-> pci_host_probe(bridge);
-> [enumeration]
-> pci_alloc_child_bus()
-> bus->ops->add_bus(bus); /* We've set this op */
-> brcm_pcie_add_bus() /* Our callback */
-> [turn on regulators] /* Main objective! */
-> brcm_pcie_start_link() /* Link-up */
One final note: some code that was executed after the PCIe linkup is now
placed so that it executes prior to linkup, since this code has to run
prior to the invocation of pci_host_probe().
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 111 +++++++++++++++-----------
1 file changed, 64 insertions(+), 47 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index bd88a0a46c63..15e47e8c94eb 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -849,17 +849,13 @@ static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
static int brcm_pcie_setup(struct brcm_pcie *pcie)
{
- struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
u64 rc_bar2_offset, rc_bar2_size;
void __iomem *base = pcie->base;
- struct device *dev = pcie->dev;
+ struct pci_host_bridge *bridge;
struct resource_entry *entry;
- bool ssc_good = false;
- struct resource *res;
- int num_out_wins = 0;
- u16 nlw, cls, lnksta;
- int i, ret, memc;
u32 tmp, burst, aspm_support;
+ int num_out_wins = 0;
+ int ret, memc;
/* Reset the bridge */
pcie->bridge_sw_init_set(pcie, 1);
@@ -935,6 +931,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
else
pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
+ if (!brcm_pcie_rc_mode(pcie)) {
+ dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
+ return -EINVAL;
+ }
+
/* disable the PCIe->GISB memory window (RC_BAR1) */
tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
@@ -945,31 +946,27 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
- if (pcie->gen)
- brcm_pcie_set_gen(pcie, pcie->gen);
-
- /* Unassert the fundamental reset */
- pcie->perst_set(pcie, 0);
+ /* Don't advertise L0s capability if 'aspm-no-l0s' */
+ aspm_support = PCIE_LINK_STATE_L1;
+ if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
+ aspm_support |= PCIE_LINK_STATE_L0S;
+ tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+ u32p_replace_bits(&tmp, aspm_support,
+ PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
+ writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
/*
- * Give the RC/EP time to wake up, before trying to configure RC.
- * Intermittently check status for link-up, up to a total of 100ms.
+ * For config space accesses on the RC, show the right class for
+ * a PCIe-PCIe bridge (the default setting is to be EP mode).
*/
- for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
- msleep(5);
-
- if (!brcm_pcie_link_up(pcie)) {
- dev_err(dev, "link down\n");
- return -ENODEV;
- }
-
- if (!brcm_pcie_rc_mode(pcie)) {
- dev_err(dev, "PCIe misconfigured; is in EP mode\n");
- return -EINVAL;
- }
+ tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
+ u32p_replace_bits(&tmp, 0x060400,
+ PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
+ writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
+ bridge = pci_host_bridge_from_priv(pcie);
resource_list_for_each_entry(entry, &bridge->windows) {
- res = entry->res;
+ struct resource *res = entry->res;
if (resource_type(res) != IORESOURCE_MEM)
continue;
@@ -998,23 +995,41 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
num_out_wins++;
}
- /* Don't advertise L0s capability if 'aspm-no-l0s' */
- aspm_support = PCIE_LINK_STATE_L1;
- if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
- aspm_support |= PCIE_LINK_STATE_L0S;
- tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
- u32p_replace_bits(&tmp, aspm_support,
- PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
- writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+ /* PCIe->SCB endian mode for BAR */
+ tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
+ u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
+ PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
+ writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
+
+ return 0;
+}
+
+static int brcm_pcie_start_link(struct brcm_pcie *pcie)
+{
+ struct device *dev = pcie->dev;
+ void __iomem *base = pcie->base;
+ u16 nlw, cls, lnksta;
+ bool ssc_good = false;
+ u32 tmp;
+ int ret, i;
+
+ /* Unassert the fundamental reset */
+ pcie->perst_set(pcie, 0);
/*
- * For config space accesses on the RC, show the right class for
- * a PCIe-PCIe bridge (the default setting is to be EP mode).
+ * Give the RC/EP time to wake up, before trying to configure RC.
+ * Intermittently check status for link-up, up to a total of 100ms.
*/
- tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
- u32p_replace_bits(&tmp, 0x060400,
- PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
- writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
+ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
+ msleep(5);
+
+ if (!brcm_pcie_link_up(pcie)) {
+ dev_err(dev, "link down\n");
+ return -ENODEV;
+ }
+
+ if (pcie->gen)
+ brcm_pcie_set_gen(pcie, pcie->gen);
if (pcie->ssc) {
ret = brcm_pcie_set_ssc(pcie);
@@ -1031,12 +1046,6 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
pci_speed_string(pcie_link_speed[cls]), nlw,
ssc_good ? "(SSC)" : "(!SSC)");
- /* PCIe->SCB endian mode for BAR */
- tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
- u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
- PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
- writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
-
/*
* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
* is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
@@ -1204,6 +1213,10 @@ static int brcm_pcie_resume(struct device *dev)
if (ret)
goto err_reset;
+ ret = brcm_pcie_start_link(pcie);
+ if (ret)
+ goto err_reset;
+
if (pcie->msi)
brcm_msi_set_regs(pcie->msi);
@@ -1393,6 +1406,10 @@ static int brcm_pcie_probe(struct platform_device *pdev)
if (ret)
goto fail;
+ ret = brcm_pcie_start_link(pcie);
+ if (ret)
+ goto fail;
+
pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
--
2.17.1
This Broadcom STB PCIe RC driver has one port and connects directly to one
device, be it a switch or an endpoint. We want to be able to leverage the
recently added mechanism that allocates and turns on/off subdevice
regulators.
All that needs to be done is to put the regulator DT nodes in the bridge
below host and to set the pci_ops methods add_bus and remove_bus.
Note that the pci_subdev_regulators_add_bus() method is wrapped for two
reasons:
1. To achieve link up after the voltage regulators are turned on.
2. If, in the case of an unsuccessful link up, to redirect any PCIe
accesses to subdevices, e.g. the scan for DEV/ID. This redirection
is needed because the Broadcom PCIe HW will issue a CPU abort if such
an access is made when the link is down.
The pci_subdev_regulators_remove_bus() is wrapped as well as
we must avoid invoking it if we see that there is a collision
in the use of dev->driver_data.
[bhelgaas: fold in
https://lore.kernel.org/r/[email protected]]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 134 ++++++++++++++++++--------
1 file changed, 95 insertions(+), 39 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 1be6e71142d8..aa199b0a39e2 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -261,6 +261,8 @@ struct brcm_pcie {
u32 hw_rev;
void (*perst_set)(struct brcm_pcie *pcie, u32 val);
void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
+ bool regulator_oops;
+ struct subdev_regulators *sr;
};
static inline bool is_bmips(const struct brcm_pcie *pcie)
@@ -1100,10 +1102,37 @@ static int pci_subdev_regulators_add_bus(struct pci_bus *bus)
struct subdev_regulators *sr;
int ret;
- if (!dev->of_node || !bus->parent || !pci_is_root_bus(bus->parent))
+ sr = alloc_subdev_regulators(dev);
+ if (!sr)
+ return -ENOMEM;
+
+ ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
+ if (ret) {
+ dev_err(dev, "failed to get regulators for downstream device\n");
+ return ret;
+ }
+
+ ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
+ if (ret) {
+ dev_err(dev, "failed to enable regulators for downstream device\n");
+ regulator_bulk_free(sr->num_supplies, sr->supplies);
+ return ret;
+ }
+ dev->driver_data = sr;
+
+ return 0;
+}
+
+static int brcm_pcie_add_bus(struct pci_bus *bus)
+{
+ struct brcm_pcie *pcie = (struct brcm_pcie *) bus->sysdata;
+ struct device *dev = &bus->dev;
+ int ret;
+
+ if (!bus->parent || !pci_is_root_bus(bus->parent) || !pcie)
return 0;
- if (dev->driver_data) {
+ if (dev->of_node && dev->driver_data) {
/*
* Oops, this is unfortunate. We are using the port
* driver's driver_data field to store our regulator info
@@ -1112,12 +1141,15 @@ static int pci_subdev_regulators_add_bus(struct pci_bus *bus)
* may still be okay if there are no regulators.
*/
dev_err(dev, "root port dev.driver_data non-NULL; something wrong\n");
- return 0;
+
+ } else if (dev->of_node) {
+ ret = pci_subdev_regulators_add_bus(bus);
+ /* Grab the regulators for suspend/resume */
+ pcie->sr = bus->dev.driver_data;
}
- sr = alloc_subdev_regulators(dev);
- if (!sr)
- return -ENOMEM;
+ /* Try to start the link. */
+ brcm_pcie_start_link(pcie);
/*
* There is not much of a point to return an error as currently it
@@ -1125,22 +1157,7 @@ static int pci_subdev_regulators_add_bus(struct pci_bus *bus)
* return the error if it is -ENOMEM. Note that we are always
* doing a dev_err() for other erros.
*/
- ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
- if (ret) {
- dev_err(dev, "failed to get regulators for downstream device\n");
- return 0;
- }
-
- ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
- if (ret) {
- dev_err(dev, "failed to enable regulators for downstream device\n");
- regulator_bulk_free(sr->num_supplies, sr->supplies);
- return 0;
- }
-
- dev->driver_data = sr;
-
- return 0;
+ return ret == -ENOMEM ? ret : 0;
}
static void pci_subdev_regulators_remove_bus(struct pci_bus *bus)
@@ -1148,15 +1165,28 @@ static void pci_subdev_regulators_remove_bus(struct pci_bus *bus)
struct device *dev = &bus->dev;
struct subdev_regulators *sr = dev->driver_data;
- if (!dev->of_node || !sr || !bus->parent || !pci_is_root_bus(bus->parent))
- return;
-
if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
dev_err(dev, "failed to disable regulators for downstream device\n");
regulator_bulk_free(sr->num_supplies, sr->supplies);
dev->driver_data = NULL;
}
+static void brcm_pcie_remove_bus(struct pci_bus *bus)
+{
+ struct device *dev = &bus->dev;
+ struct brcm_pcie *pcie;
+
+ if (!dev->of_node || !dev->driver_data || !bus->parent ||
+ !pci_is_root_bus(bus->parent))
+ return;
+
+ pcie = (struct brcm_pcie *) bus->sysdata;
+ if (pcie && pcie->sr) {
+ pci_subdev_regulators_remove_bus(bus);
+ pcie->sr = NULL;
+ }
+}
+
/* L23 is a low-power PCIe link state */
static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
{
@@ -1253,7 +1283,7 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
pcie->bridge_sw_init_set(pcie, 1);
}
-static int brcm_pcie_suspend(struct device *dev)
+static int brcm_pcie_suspend_noirq(struct device *dev)
{
struct brcm_pcie *pcie = dev_get_drvdata(dev);
int ret;
@@ -1273,12 +1303,20 @@ static int brcm_pcie_suspend(struct device *dev)
return ret;
}
+ if (pcie->sr) {
+ ret = regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
+ if (ret) {
+ dev_err(dev, "Could not turn off regulators\n");
+ reset_control_reset(pcie->rescal);
+ return ret;
+ }
+ }
clk_disable_unprepare(pcie->clk);
return 0;
}
-static int brcm_pcie_resume(struct device *dev)
+static int brcm_pcie_resume_noirq(struct device *dev)
{
struct brcm_pcie *pcie = dev_get_drvdata(dev);
void __iomem *base;
@@ -1313,15 +1351,27 @@ static int brcm_pcie_resume(struct device *dev)
if (ret)
goto err_reset;
+ if (pcie->sr) {
+ ret = regulator_bulk_enable(pcie->sr->num_supplies,
+ pcie->sr->supplies);
+ if (ret) {
+ dev_err(dev, "Could not turn on regulators\n");
+ goto err_reset;
+ }
+ }
+
ret = brcm_pcie_start_link(pcie);
if (ret)
- goto err_reset;
+ goto err_regulator;
if (pcie->msi)
brcm_msi_set_regs(pcie->msi);
return 0;
+err_regulator:
+ if (pcie->sr)
+ regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
err_reset:
reset_control_rearm(pcie->rescal);
err_disable_clk:
@@ -1428,16 +1478,16 @@ static struct pci_ops brcm_pcie_ops = {
.map_bus = brcm_pcie_map_conf,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
- .add_bus = pci_subdev_regulators_add_bus,
- .remove_bus = pci_subdev_regulators_remove_bus,
+ .add_bus = brcm_pcie_add_bus,
+ .remove_bus = brcm_pcie_remove_bus
};
static struct pci_ops brcm_pcie_ops32 = {
.map_bus = brcm_pcie_map_conf32,
.read = pci_generic_config_read32,
.write = pci_generic_config_write32,
- .add_bus = pci_subdev_regulators_add_bus,
- .remove_bus = pci_subdev_regulators_remove_bus,
+ .add_bus = brcm_pcie_add_bus,
+ .remove_bus = brcm_pcie_remove_bus
};
static int brcm_pcie_probe(struct platform_device *pdev)
@@ -1510,10 +1560,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
if (ret)
goto fail;
- ret = brcm_pcie_start_link(pcie);
- if (ret)
- goto fail;
-
pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
@@ -1535,7 +1581,17 @@ static int brcm_pcie_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pcie);
- return pci_host_probe(bridge);
+ ret = pci_host_probe(bridge);
+ if (!ret && !brcm_pcie_link_up(pcie))
+ ret = -ENODEV;
+
+ if (ret) {
+ brcm_pcie_remove(pdev);
+ return ret;
+ }
+
+ return 0;
+
fail:
__brcm_pcie_remove(pcie);
return ret;
@@ -1544,8 +1600,8 @@ static int brcm_pcie_probe(struct platform_device *pdev)
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
static const struct dev_pm_ops brcm_pcie_pm_ops = {
- .suspend = brcm_pcie_suspend,
- .resume = brcm_pcie_resume,
+ .suspend_noirq = brcm_pcie_suspend_noirq,
+ .resume_noirq = brcm_pcie_resume_noirq,
};
static struct platform_driver brcm_pcie_driver = {
--
2.17.1
On Mon, Jul 25, 2022 at 11:12:49AM -0400, Jim Quinlan wrote:
> ...
> Jim Quinlan (7):
> PCI: brcmstb: Remove unnecessary forward declarations
> PCI: brcmstb: Split brcm_pcie_setup() into two funcs
> PCI: brcmstb: Gate config space access on link status
> PCI: brcmstb: Add mechanism to turn on subdev regulators
> PCI: brcmstb: Add control of subdevice voltage regulators
> PCI: brcmstb: Do not turn off WOL regulators on suspend
> PCI: brcmstb: Have .map_bus function names end with 'map_bus'
>
> drivers/pci/controller/pcie-brcmstb.c | 476 ++++++++++++++++++--------
> 1 file changed, 341 insertions(+), 135 deletions(-)
I reworked these and put them on pci/ctrl/brcm for v5.20. This is a
proposal, not something set in stone. But time is of the essence to
figure out how we want to proceed.
I changed a lot of stuff and it's likely I broke something in the
process, so please take a look and test this out. Here's an outline
of what I changed:
- Moved the config access "link up" check earlier because it's not
related to the power regulator patches.
- Changed config access "link up" checks to use PCIE_ECAM_REG()
instead of hard-coding 0xfff masks. The 32-bit accessors already
mask out the low two bits, so we don't need to do that here.
- Squashed pci_subdev_regulators_add_bus() directly into
brcm_pcie_add_bus() for readability. Similarly for
pci_subdev_regulators_remove_bus().
- This makes a clear split between:
* A patch that adds get/enable of regulators, and starting the
link after enabling regulators, and
* A patch that disables/enables regulators for suspend/resume.
- Since we only support one set of subregulator info (for one Root
Port, and brcm_pcie_suspend_noirq() depends on this since it uses
the pcie->sr pointer), use pcie->sr always instead of
dev->driver_data.
- Squashed wakeup device checking into the suspend/resume patch so
there's not a time when suspend might turn off power to a wakeup
device.
- Renamed brcm_pcie_map_bus32() to brcm7425_pcie_map_bus() so it
ends in "_map_bus()" like other drivers. Also,
brcm7425_pcie_map_bus() doesn't actually depend on the 32-bitness.
Bjorn
On 7/26/22 15:03, Bjorn Helgaas wrote:
> On Mon, Jul 25, 2022 at 11:12:49AM -0400, Jim Quinlan wrote:
>> ...
>> Jim Quinlan (7):
>> PCI: brcmstb: Remove unnecessary forward declarations
>> PCI: brcmstb: Split brcm_pcie_setup() into two funcs
>> PCI: brcmstb: Gate config space access on link status
>> PCI: brcmstb: Add mechanism to turn on subdev regulators
>> PCI: brcmstb: Add control of subdevice voltage regulators
>> PCI: brcmstb: Do not turn off WOL regulators on suspend
>> PCI: brcmstb: Have .map_bus function names end with 'map_bus'
>>
>> drivers/pci/controller/pcie-brcmstb.c | 476 ++++++++++++++++++--------
>> 1 file changed, 341 insertions(+), 135 deletions(-)
>
> I reworked these and put them on pci/ctrl/brcm for v5.20. This is a
> proposal, not something set in stone. But time is of the essence to
> figure out how we want to proceed.
>
> I changed a lot of stuff and it's likely I broke something in the
> process, so please take a look and test this out. Here's an outline
> of what I changed:
>
> - Moved the config access "link up" check earlier because it's not
> related to the power regulator patches.
>
> - Changed config access "link up" checks to use PCIE_ECAM_REG()
> instead of hard-coding 0xfff masks. The 32-bit accessors already
> mask out the low two bits, so we don't need to do that here.
>
> - Squashed pci_subdev_regulators_add_bus() directly into
> brcm_pcie_add_bus() for readability. Similarly for
> pci_subdev_regulators_remove_bus().
>
> - This makes a clear split between:
>
> * A patch that adds get/enable of regulators, and starting the
> link after enabling regulators, and
>
> * A patch that disables/enables regulators for suspend/resume.
>
> - Since we only support one set of subregulator info (for one Root
> Port, and brcm_pcie_suspend_noirq() depends on this since it uses
> the pcie->sr pointer), use pcie->sr always instead of
> dev->driver_data.
>
> - Squashed wakeup device checking into the suspend/resume patch so
> there's not a time when suspend might turn off power to a wakeup
> device.
>
> - Renamed brcm_pcie_map_bus32() to brcm7425_pcie_map_bus() so it
> ends in "_map_bus()" like other drivers. Also,
> brcm7425_pcie_map_bus() doesn't actually depend on the 32-bitness.
Attached is the diff between Jim's and your branch just so it is easier to see what moved around.
Initial testing on an ARCH_BRCMSTB system with PCIe appears to be good, we don't have any regulator on that board so the dummy ones get picked up which is expected. Same thing with a Raspberry Pi 4B system.
I could unbind and bind again and there were no reference count leaks on the regulators, so this looks good to me.
Tested-by: Florian Fainelli <[email protected]>
of course, we should have Jim's test results as well as Cyril's ideally to make sure there are no regressions on the CM4 board.
Thanks Bjorn!
--
Florian
On Tue, Jul 26, 2022 at 6:03 PM Bjorn Helgaas <[email protected]> wrote:
>
> On Mon, Jul 25, 2022 at 11:12:49AM -0400, Jim Quinlan wrote:
> > ...
> > Jim Quinlan (7):
> > PCI: brcmstb: Remove unnecessary forward declarations
> > PCI: brcmstb: Split brcm_pcie_setup() into two funcs
> > PCI: brcmstb: Gate config space access on link status
> > PCI: brcmstb: Add mechanism to turn on subdev regulators
> > PCI: brcmstb: Add control of subdevice voltage regulators
> > PCI: brcmstb: Do not turn off WOL regulators on suspend
> > PCI: brcmstb: Have .map_bus function names end with 'map_bus'
> >
> > drivers/pci/controller/pcie-brcmstb.c | 476 ++++++++++++++++++--------
> > 1 file changed, 341 insertions(+), 135 deletions(-)
>
> I reworked these and put them on pci/ctrl/brcm for v5.20. This is a
> proposal, not something set in stone. But time is of the essence to
> figure out how we want to proceed.
>
> I changed a lot of stuff and it's likely I broke something in the
> process, so please take a look and test this out. Here's an outline
> of what I changed:
>
> - Moved the config access "link up" check earlier because it's not
> related to the power regulator patches.
>
> - Changed config access "link up" checks to use PCIE_ECAM_REG()
> instead of hard-coding 0xfff masks. The 32-bit accessors already
> mask out the low two bits, so we don't need to do that here.
>
> - Squashed pci_subdev_regulators_add_bus() directly into
> brcm_pcie_add_bus() for readability. Similarly for
> pci_subdev_regulators_remove_bus().
>
> - This makes a clear split between:
>
> * A patch that adds get/enable of regulators, and starting the
> link after enabling regulators, and
>
> * A patch that disables/enables regulators for suspend/resume.
>
> - Since we only support one set of subregulator info (for one Root
> Port, and brcm_pcie_suspend_noirq() depends on this since it uses
> the pcie->sr pointer), use pcie->sr always instead of
> dev->driver_data.
>
> - Squashed wakeup device checking into the suspend/resume patch so
> there's not a time when suspend might turn off power to a wakeup
> device.
>
> - Renamed brcm_pcie_map_bus32() to brcm7425_pcie_map_bus() so it
> ends in "_map_bus()" like other drivers. Also,
> brcm7425_pcie_map_bus() doesn't actually depend on the 32-bitness.
Hi Bjorn,
Sorry, it seems that some of my future commits have somehow bled code
into the driver (e.g. "has_phy").
LGTM.
Thanks and regards,
Jim Quinlan
Broadcom STB
>
> Bjorn
On Tue, Jul 26, 2022 at 04:41:09PM -0700, Florian Fainelli wrote:
> On 7/26/22 15:03, Bjorn Helgaas wrote:
> > On Mon, Jul 25, 2022 at 11:12:49AM -0400, Jim Quinlan wrote:
> >> ...
> >> Jim Quinlan (7):
> >> PCI: brcmstb: Remove unnecessary forward declarations
> >> PCI: brcmstb: Split brcm_pcie_setup() into two funcs
> >> PCI: brcmstb: Gate config space access on link status
> >> PCI: brcmstb: Add mechanism to turn on subdev regulators
> >> PCI: brcmstb: Add control of subdevice voltage regulators
> >> PCI: brcmstb: Do not turn off WOL regulators on suspend
> >> PCI: brcmstb: Have .map_bus function names end with 'map_bus'
> >>
> >> drivers/pci/controller/pcie-brcmstb.c | 476 ++++++++++++++++++--------
> >> 1 file changed, 341 insertions(+), 135 deletions(-)
> >
> > I reworked these and put them on pci/ctrl/brcm for v5.20. This is a
> > proposal, not something set in stone. But time is of the essence to
> > figure out how we want to proceed.
> >
> > I changed a lot of stuff and it's likely I broke something in the
> > process, so please take a look and test this out. Here's an outline
> > of what I changed:
> >
> > - Moved the config access "link up" check earlier because it's not
> > related to the power regulator patches.
> >
> > - Changed config access "link up" checks to use PCIE_ECAM_REG()
> > instead of hard-coding 0xfff masks. The 32-bit accessors already
> > mask out the low two bits, so we don't need to do that here.
> >
> > - Squashed pci_subdev_regulators_add_bus() directly into
> > brcm_pcie_add_bus() for readability. Similarly for
> > pci_subdev_regulators_remove_bus().
> >
> > - This makes a clear split between:
> >
> > * A patch that adds get/enable of regulators, and starting the
> > link after enabling regulators, and
> >
> > * A patch that disables/enables regulators for suspend/resume.
> >
> > - Since we only support one set of subregulator info (for one Root
> > Port, and brcm_pcie_suspend_noirq() depends on this since it uses
> > the pcie->sr pointer), use pcie->sr always instead of
> > dev->driver_data.
> >
> > - Squashed wakeup device checking into the suspend/resume patch so
> > there's not a time when suspend might turn off power to a wakeup
> > device.
> >
> > - Renamed brcm_pcie_map_bus32() to brcm7425_pcie_map_bus() so it
> > ends in "_map_bus()" like other drivers. Also,
> > brcm7425_pcie_map_bus() doesn't actually depend on the 32-bitness.
>
> Attached is the diff between Jim's and your branch just so it is easier to see what moved around.
>
> Initial testing on an ARCH_BRCMSTB system with PCIe appears to be good, we don't have any regulator on that board so the dummy ones get picked up which is expected. Same thing with a Raspberry Pi 4B system.
>
> I could unbind and bind again and there were no reference count leaks on the regulators, so this looks good to me.
>
> Tested-by: Florian Fainelli <[email protected]>
>
> of course, we should have Jim's test results as well as Cyril's ideally to make sure there are no regressions on the CM4 board.
Cyril, any chance you could test this to be sure it fixes the problem
you reported? This is in -next and hopefully headed for v5.20/v6.0
soon.
I see that we failed to reference
https://bugzilla.kernel.org/show_bug.cgi?id=215925 in the commit logs,
but IIUC, this *should* fix that.
Bjorn
On Mon, Aug 1, 2022 at 6:19 PM Bjorn Helgaas <[email protected]> wrote:
>
> On Tue, Jul 26, 2022 at 04:41:09PM -0700, Florian Fainelli wrote:
> > On 7/26/22 15:03, Bjorn Helgaas wrote:
> > > On Mon, Jul 25, 2022 at 11:12:49AM -0400, Jim Quinlan wrote:
> > >> ...
> > >> Jim Quinlan (7):
> > >> PCI: brcmstb: Remove unnecessary forward declarations
> > >> PCI: brcmstb: Split brcm_pcie_setup() into two funcs
> > >> PCI: brcmstb: Gate config space access on link status
> > >> PCI: brcmstb: Add mechanism to turn on subdev regulators
> > >> PCI: brcmstb: Add control of subdevice voltage regulators
> > >> PCI: brcmstb: Do not turn off WOL regulators on suspend
> > >> PCI: brcmstb: Have .map_bus function names end with 'map_bus'
> > >>
> > >> drivers/pci/controller/pcie-brcmstb.c | 476 ++++++++++++++++++--------
> > >> 1 file changed, 341 insertions(+), 135 deletions(-)
> > >
> > > I reworked these and put them on pci/ctrl/brcm for v5.20. This is a
> > > proposal, not something set in stone. But time is of the essence to
> > > figure out how we want to proceed.
> > >
> > > I changed a lot of stuff and it's likely I broke something in the
> > > process, so please take a look and test this out. Here's an outline
> > > of what I changed:
> > >
> > > - Moved the config access "link up" check earlier because it's not
> > > related to the power regulator patches.
> > >
> > > - Changed config access "link up" checks to use PCIE_ECAM_REG()
> > > instead of hard-coding 0xfff masks. The 32-bit accessors already
> > > mask out the low two bits, so we don't need to do that here.
> > >
> > > - Squashed pci_subdev_regulators_add_bus() directly into
> > > brcm_pcie_add_bus() for readability. Similarly for
> > > pci_subdev_regulators_remove_bus().
> > >
> > > - This makes a clear split between:
> > >
> > > * A patch that adds get/enable of regulators, and starting the
> > > link after enabling regulators, and
> > >
> > > * A patch that disables/enables regulators for suspend/resume.
> > >
> > > - Since we only support one set of subregulator info (for one Root
> > > Port, and brcm_pcie_suspend_noirq() depends on this since it uses
> > > the pcie->sr pointer), use pcie->sr always instead of
> > > dev->driver_data.
> > >
> > > - Squashed wakeup device checking into the suspend/resume patch so
> > > there's not a time when suspend might turn off power to a wakeup
> > > device.
> > >
> > > - Renamed brcm_pcie_map_bus32() to brcm7425_pcie_map_bus() so it
> > > ends in "_map_bus()" like other drivers. Also,
> > > brcm7425_pcie_map_bus() doesn't actually depend on the 32-bitness.
> >
> > Attached is the diff between Jim's and your branch just so it is easier to see what moved around.
> >
> > Initial testing on an ARCH_BRCMSTB system with PCIe appears to be good, we don't have any regulator on that board so the dummy ones get picked up which is expected. Same thing with a Raspberry Pi 4B system.
> >
> > I could unbind and bind again and there were no reference count leaks on the regulators, so this looks good to me.
> >
> > Tested-by: Florian Fainelli <[email protected]>
> >
> > of course, we should have Jim's test results as well as Cyril's ideally to make sure there are no regressions on the CM4 board.
>
> Cyril, any chance you could test this to be sure it fixes the problem
> you reported? This is in -next and hopefully headed for v5.20/v6.0
> soon.
Hello Bjorn,
Cyril sent me an email about a week ago saying that he probably
wouldn't have the bandwidth to test this.
I immediately ordered an overpriced CM4 via Ebay and it recently
arrived. I'm happy to say that this
patchset tests successfully, w/ or w/o a device in the slot.
That being said, there is an old device, when paired with the CM4,
works with RPi Linux but not with upstream Linux. It is unrelated
to this patchset; i.e. it fails w/ or w/o this patchset applied. I
know the reason for this failure: the current driver
assumes clkreq# asserted, which is true for all STB boards. I can add
a patch for this now or in the next release
cycle, your choice.
Regards,
Jim Quinlan
Broadcom STB
>
> I see that we failed to reference
> https://bugzilla.kernel.org/show_bug.cgi?id=215925 in the commit logs,
> but IIUC, this *should* fix that.
>
> Bjorn
On Thu, Aug 04, 2022 at 01:05:04PM -0400, Jim Quinlan wrote:
> On Mon, Aug 1, 2022 at 6:19 PM Bjorn Helgaas <[email protected]> wrote:
> > On Tue, Jul 26, 2022 at 04:41:09PM -0700, Florian Fainelli wrote:
> > > On 7/26/22 15:03, Bjorn Helgaas wrote:
> > > > On Mon, Jul 25, 2022 at 11:12:49AM -0400, Jim Quinlan wrote:
> > > >> ...
> > > >> Jim Quinlan (7):
> > > >> PCI: brcmstb: Remove unnecessary forward declarations
> > > >> PCI: brcmstb: Split brcm_pcie_setup() into two funcs
> > > >> PCI: brcmstb: Gate config space access on link status
> > > >> PCI: brcmstb: Add mechanism to turn on subdev regulators
> > > >> PCI: brcmstb: Add control of subdevice voltage regulators
> > > >> PCI: brcmstb: Do not turn off WOL regulators on suspend
> > > >> PCI: brcmstb: Have .map_bus function names end with 'map_bus'
> > > >>
> > > >> drivers/pci/controller/pcie-brcmstb.c | 476 ++++++++++++++++++--------
> > > >> 1 file changed, 341 insertions(+), 135 deletions(-)
> > > >
> > > > I reworked these and put them on pci/ctrl/brcm for v5.20. This is a
> > > > proposal, not something set in stone. But time is of the essence to
> > > > figure out how we want to proceed.
> > > >
> > > > I changed a lot of stuff and it's likely I broke something in the
> > > > process, so please take a look and test this out. Here's an outline
> > > > of what I changed:
> > > >
> > > > - Moved the config access "link up" check earlier because it's not
> > > > related to the power regulator patches.
> > > >
> > > > - Changed config access "link up" checks to use PCIE_ECAM_REG()
> > > > instead of hard-coding 0xfff masks. The 32-bit accessors already
> > > > mask out the low two bits, so we don't need to do that here.
> > > >
> > > > - Squashed pci_subdev_regulators_add_bus() directly into
> > > > brcm_pcie_add_bus() for readability. Similarly for
> > > > pci_subdev_regulators_remove_bus().
> > > >
> > > > - This makes a clear split between:
> > > >
> > > > * A patch that adds get/enable of regulators, and starting the
> > > > link after enabling regulators, and
> > > >
> > > > * A patch that disables/enables regulators for suspend/resume.
> > > >
> > > > - Since we only support one set of subregulator info (for one Root
> > > > Port, and brcm_pcie_suspend_noirq() depends on this since it uses
> > > > the pcie->sr pointer), use pcie->sr always instead of
> > > > dev->driver_data.
> > > >
> > > > - Squashed wakeup device checking into the suspend/resume patch so
> > > > there's not a time when suspend might turn off power to a wakeup
> > > > device.
> > > >
> > > > - Renamed brcm_pcie_map_bus32() to brcm7425_pcie_map_bus() so it
> > > > ends in "_map_bus()" like other drivers. Also,
> > > > brcm7425_pcie_map_bus() doesn't actually depend on the 32-bitness.
> > >
> > > Attached is the diff between Jim's and your branch just so it is easier to see what moved around.
> > >
> > > Initial testing on an ARCH_BRCMSTB system with PCIe appears to be good, we don't have any regulator on that board so the dummy ones get picked up which is expected. Same thing with a Raspberry Pi 4B system.
> > >
> > > I could unbind and bind again and there were no reference count leaks on the regulators, so this looks good to me.
> > >
> > > Tested-by: Florian Fainelli <[email protected]>
> > >
> > > of course, we should have Jim's test results as well as Cyril's ideally to make sure there are no regressions on the CM4 board.
> >
> > Cyril, any chance you could test this to be sure it fixes the problem
> > you reported? This is in -next and hopefully headed for v5.20/v6.0
> > soon.
>
> Cyril sent me an email about a week ago saying that he probably
> wouldn't have the bandwidth to test this.
> I immediately ordered an overpriced CM4 via Ebay and it recently
> arrived. I'm happy to say that this
> patchset tests successfully, w/ or w/o a device in the slot.
Great, thanks a lot for testing this!
> That being said, there is an old device, when paired with the CM4,
> works with RPi Linux but not with upstream Linux. It is unrelated
> to this patchset; i.e. it fails w/ or w/o this patchset applied. I
> know the reason for this failure: the current driver
> assumes clkreq# asserted, which is true for all STB boards. I can add
> a patch for this now or in the next release
> cycle, your choice.
It's too late for v5.20-rc1, but if this would fix a regression or
otherwise exceptional bug, Lorenzo might still consider it for the
v5.20.
Bjorn