Signed-off-by: Cho KyongHo <[email protected]>
---
.../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
arch/arm/boot/dts/exynos4210.dtsi | 25 ++
arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
5 files changed, 617 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
new file mode 100644
index 0000000..92f0a33
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
@@ -0,0 +1,103 @@
+Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
+
+Samsung's Exynos architecture contains System MMU that enables scattered
+physical memory chunks visible as a contiguous region to DMA-capable peripheral
+devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
+
+System MMU is a sort of IOMMU and support identical translation table format to
+ARMv7 translation tables with minimum set of page properties including access
+permissions, shareability and security protection. In addition, System MMU has
+another capabilities like L2 TLB or block-fetch buffers to minimize translation
+latency.
+
+A System MMU is dedicated to a single master peripheral device. Thus, it is
+important to specify the correct System MMU in the device node of its master
+device. Whereas a System MMU is dedicated to a master device, the master device
+may have more than one System MMU.
+
+Required properties:
+- compatible: Should be "samsung,exynos4210-sysmmu"
+- reg: A tuple of base address and size of System MMU registers.
+- interrupt-parent: The phandle of the interrupt controller of System MMU
+- interrupts: A tuple of numbers that indicates the interrupt source.
+- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
+ Please refer to the following documents:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ Documentation/devicetree/bindings/clock/exynos4-clock.txt
+ Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+ Optional "master" if the clock to the System MMU is gated by
+ another gate clock other than "sysmmu". The System MMU driver
+ sets "master" the parent of "sysmmu".
+ Exynos4 SoCs, there needs no "master" clocks.
+ Exynos5 SoCs, some System MMUs must have "master" clocks.
+- clocks: Required if the System MMU is needed to gate its clock.
+ Please refer to the documents listed above.
+- samsung,power-domain: Required if the System MMU is needed to gate its power.
+ Please refer to the following document:
+ Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+
+Required properties for the master peripheral devices:
+- iommu: phandles to the System MMUs of the device
+
+Examples:
+A System MMU is dedicated to a single master device.
+ gsc_0: gsc@0x13e00000 {
+ compatible = "samsung,exynos5-gsc";
+ reg = <0x13e00000 0x1000>;
+ interrupts = <0 85 0>;
+ samsung,power-domain = <&pd_gsc>;
+ clocks = <&clock 256>;
+ clock-names = "gscl";
+ iommu = <&sysmmu_gsc1>;
+ };
+
+ sysmmu_gsc0: sysmmu@13E80000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13E80000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-gsc0";
+ interrupts = <2 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 262>, <&clock 256>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
+to define 2 System MMUs for each port of the MFC:
+
+ mfc: codec@13400000 {
+ compatible = "samsung,mfc-v5";
+ reg = <0x13400000 0x10000>;
+ interrupts = <0 94 0>;
+ samsung,power-domain = <&pd_mfc>;
+ clocks = <&clock 170>, <&clock 273>;
+ clock-names = "sclk_mfc", "mfc";
+ status = "ok";
+ iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+ };
+
+ sysmmu_mfc_l: sysmmu@13620000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13620000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-mfc-l";
+ interrupts = <5 5>;
+ clock-names = "sysmmu";
+ clocks = <&clock 274>;
+ samsung,power-domain = <&pd_mfc>;
+ status = "ok";
+ };
+
+ sysmmu_mfc_r: sysmmu@13630000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13630000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-mfc-r";
+ interrupts = <5 6>;
+ clock-names = "sysmmu";
+ clocks = <&clock 275>;
+ samsung,power-domain = <&pd_mfc>;
+ status = "ok";
+ };
+
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 359694c..ba74ee8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -161,6 +161,7 @@
interrupts = <0 94 0>;
samsung,power-domain = <&pd_mfc>;
status = "disabled";
+ iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
};
serial@13800000 {
@@ -395,5 +396,126 @@
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
status = "disabled";
+ iommu = <&sysmmu_fimd0>;
+ };
+
+ sysmmu_mfc_l: sysmmu@13620000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13620000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-mfc-l";
+ interrupts = <5 5>;
+ clock-names = "sysmmu";
+ clocks = <&clock 274>;
+ samsung,power-domain = <&pd_mfc>;
+ status = "ok";
+ };
+
+ sysmmu_mfc_r: sysmmu@13630000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13630000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-mfc-r";
+ interrupts = <5 6>;
+ clock-names = "sysmmu";
+ clocks = <&clock 275>;
+ samsung,power-domain = <&pd_mfc>;
+ status = "ok";
+ };
+
+ sysmmu_tv: sysmmu@13E20000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13E20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-tv";
+ interrupts = <5 4>;
+ clock-names = "sysmmu";
+ clocks = <&clock 272>;
+ samsung,power-domain = <&pd_tv>;
+ status = "ok";
+ };
+
+ sysmmu_fimc0: sysmmu@11A20000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11A20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc0";
+ interrupts = <4 2>;
+ clock-names = "sysmmu";
+ clocks = <&clock 263>;
+ samsung,power-domain = <&pd_cam>;
+ status = "ok";
+ };
+
+ sysmmu_fimc1: sysmmu@11A30000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11A30000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc1";
+ interrupts = <4 3>;
+ clock-names = "sysmmu";
+ clocks = <&clock 264>;
+ samsung,power-domain = <&pd_cam>;
+ status = "ok";
+ };
+
+ sysmmu_fimc2: sysmmu@11A40000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11A40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc2";
+ interrupts = <4 4>;
+ clock-names = "sysmmu";
+ clocks = <&clock 265>;
+ samsung,power-domain = <&pd_cam>;
+ status = "ok";
+ };
+
+ sysmmu_fimc3: sysmmu@11A50000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11A50000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc3";
+ interrupts = <4 5>;
+ clock-names = "sysmmu";
+ clocks = <&clock 266>;
+ samsung,power-domain = <&pd_cam>;
+ status = "ok";
+ };
+
+ sysmmu_jpeg: sysmmu@11A60000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11A60000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-jpeg";
+ interrupts = <4 6>;
+ clock-names = "sysmmu";
+ clocks = <&clock 267>;
+ samsung,power-domain = <&pd_cam>;
+ status = "ok";
+ };
+
+ sysmmu_rotator: sysmmu@12A30000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x12A30000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-rotator";
+ interrupts = <5 0>;
+ clock-names = "sysmmu";
+ clocks = <&clock 281>;
+ samsung,power-domain = <&pd_lcd0>;
+ status = "ok";
+ };
+
+ sysmmu_fimd0: sysmmu@11E20000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11E20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimd0";
+ interrupts = <5 2>;
+ clock-names = "sysmmu";
+ clocks = <&clock 287>;
+ samsung,power-domain = <&pd_lcd0>;
+ status = "ok";
};
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 54710de..09b13da 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -119,5 +119,30 @@
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
+ iommu = <&sysmmu_g2d>;
+ };
+
+ sysmmu_g2d: sysmmu@12A20000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x12A20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-g2d";
+ interrupts = <4 7>;
+ clock-names = "sysmmu";
+ clocks = <&clock 280>;
+ samsung,power-domain = <&pd_lcd0>;
+ status = "ok";
+ };
+
+ sysmmu_fimd1: sysmmu@12220000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimd1";
+ reg = <0x12220000 0x1000>;
+ interrupts = <5 3>;
+ clock-names = "sysmmu";
+ clocks = <&clock 291>;
+ samsung,power-domain = <&pd_lcd1>;
+ status = "ok";
};
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7..681db32 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -79,4 +79,80 @@
interrupts = <0 89 0>;
status = "disabled";
};
+
+ sysmmu_g2d: sysmmu@10A40000{
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x10A40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-g2d";
+ interrupts = <4 7>;
+ clock-names = "sysmmu";
+ status = "ok";
+ };
+
+ sysmmu_fimc_isp: sysmmu@12260000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x12260000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_isp";
+ interrupts = <16 2>;
+ clock-names = "sysmmu";
+ clocks = <&clock 362>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_drc: sysmmu@12270000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x12270000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_drc";
+ interrupts = <16 3>;
+ clock-names = "sysmmu";
+ clocks = <&clock 363>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_fd: sysmmu@122A0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x122A0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_fd";
+ interrupts = <16 4>;
+ clock-names = "sysmmu";
+ clocks = <&clock 364>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_mcuctl: sysmmu@122B0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x122B0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_mcuctl";
+ interrupts = <16 5>;
+ clock-names = "sysmmu";
+ clocks = <&clock 376>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_lite0: sysmmu@123B0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x123B0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_lite0";
+ interrupts = <16 0>;
+ clock-names = "sysmmu";
+ clocks = <&clock 366>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_lite1: sysmmu@123C0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x123C0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_lite1";
+ interrupts = <16 1>;
+ clock-names = "sysmmu";
+ clocks = <&clock 365>;
+ status = "ok";
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index fc9fb3d..130d23d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -66,6 +66,16 @@
reg = <0x10044040 0x20>;
};
+ pd_isp: mfc-power-domain@0x10044020 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10044020 0x20>;
+ };
+
+ pd_disp1: mfc-power-domain@0x100440A0 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x100440A0 0x20>;
+ };
+
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>;
@@ -180,6 +190,7 @@
reg = <0x11000000 0x10000>;
interrupts = <0 96 0>;
samsung,power-domain = <&pd_mfc>;
+ iommu = <&sysmmu_mfc_l &sysmmu_mfc_l>;
};
rtc {
@@ -571,6 +582,7 @@
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 256>;
clock-names = "gscl";
+ iommu = <&sysmmu_gsc1>;
};
gsc_1: gsc@0x13e10000 {
@@ -580,6 +592,7 @@
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 257>;
clock-names = "gscl";
+ iommu = <&sysmmu_gsc1>;
};
gsc_2: gsc@0x13e20000 {
@@ -589,6 +602,7 @@
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 258>;
clock-names = "gscl";
+ iommu = <&sysmmu_gsc2>;
};
gsc_3: gsc@0x13e30000 {
@@ -598,6 +612,7 @@
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 259>;
clock-names = "gscl";
+ iommu = <&sysmmu_gsc3>;
};
hdmi {
@@ -614,6 +629,7 @@
compatible = "samsung,exynos5-mixer";
reg = <0x14450000 0x10000>;
interrupts = <0 94 0>;
+ iommu = <&sysmmu_tv>;
};
dp-controller {
@@ -638,5 +654,280 @@
interrupts = <18 4>, <18 5>, <18 6>;
clocks = <&clock 133>, <&clock 339>;
clock-names = "sclk_fimd", "fimd";
+ iommu = <&sysmmu_fimd1>;
+ };
+
+ sysmmu_mfc_l: sysmmu@11210000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11210000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-mfc_l";
+ interrupts = <8 5>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 267>, <&clock 266>;
+ samsung,power-domain = <&pd_mfc>;
+ status = "ok";
+ };
+
+ sysmmu_mfc_r: sysmmu@11200000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11200000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-mfc_r";
+ interrupts = <6 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 268>, <&clock 266>;
+ samsung,power-domain = <&pd_mfc>;
+ status = "ok";
+ };
+
+ sysmmu_tv: sysmmu@14650000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x14650000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-tv";
+ interrupts = <7 4>;
+ clock-names = "sysmmu";
+ clocks = <&clock 349>;
+ samsung,power-domain = <&pd_disp1>;
+ status = "ok";
+ };
+
+ sysmmu_gsc0: sysmmu@13E80000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13E80000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-gsc0";
+ interrupts = <2 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 262>, <&clock 256>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+ sysmmu_gsc1: sysmmu@13E90000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13E90000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-gsc1";
+ interrupts = <2 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 263>, <&clock 257>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+ sysmmu_gsc2: sysmmu@13EA0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13EA0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-gsc2";
+ interrupts = <2 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 264>, <&clock 258>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+ sysmmu_gsc3: sysmmu@13EB0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13EB0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-gsc3";
+ interrupts = <2 6>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 265>, <&clock 259>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+ sysmmu_fimd1: sysmmu@14640000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x14640000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimd1";
+ interrupts = <3 2>;
+ clock-names = "sysmmu";
+ clocks = <&clock 350>;
+ samsung,power-domain = <&pd_disp1>;
+ status = "ok";
+ };
+
+ sysmmu_rotator: sysmmu@11D40000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11D40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-rotator";
+ interrupts = <4 0>;
+ clock-names = "sysmmu";
+ clocks = <&clock 272>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_isp: sysmmu@13260000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13260000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_isp";
+ interrupts = <10 6>;
+ clock-names = "sysmmu";
+ clocks = <&clock 361>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_drc: sysmmu@13270000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13270000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_drc";
+ interrupts = <11 6>;
+ clock-names = "sysmmu";
+ clocks = <&clock 362>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_fd: sysmmu@132A0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x132A0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_fd";
+ interrupts = <5 0>;
+ clock-names = "sysmmu";
+ clocks = <&clock 363>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_scc: sysmmu@13280000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13280000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_scalerc";
+ interrupts = <5 2>;
+ clock-names = "sysmmu";
+ clocks = <&clock 364>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_scp: sysmmu@13290000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13290000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_scalerp";
+ interrupts = <3 6>;
+ clock-names = "sysmmu";
+ clocks = <&clock 365>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_mcuctl: sysmmu@132B0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x132B0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_mcuctl";
+ interrupts = <5 4>;
+ clock-names = "sysmmu";
+ clocks = <&clock 366>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_odc: sysmmu@132C0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x132C0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_odc";
+ interrupts = <11 0>;
+ clock-names = "sysmmu";
+ clocks = <&clock 367>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_dis0: sysmmu@132D0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x132D0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_dis0";
+ interrupts = <10 4>;
+ clock-names = "sysmmu";
+ clocks = <&clock 368>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_dis1: sysmmu@132E0000{
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x132E0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_dis1";
+ interrupts = <9 4>;
+ clock-names = "sysmmu";
+ clocks = <&clock 369>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_3dnr: sysmmu@132F0000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x132F0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_3dnr";
+ interrupts = <5 6>;
+ clock-names = "sysmmu";
+ clocks = <&clock 370>;
+ samsung,power-domain = <&pd_isp>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_lite0: sysmmu@13C40000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13C40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_lite0";
+ interrupts = <3 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 346>, <&clock 345>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_lite1: sysmmu@13C50000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x13C50000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-fimc_lite1";
+ interrupts = <24 1>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 347>, <&clock 345>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_jpeg: sysmmu@11F20000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x11F20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-jpeg";
+ interrupts = <4 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock 273>, <&clock 270>;
+ samsung,power-domain = <&pd_gsc>;
+ status = "ok";
+ };
+
+ sysmmu_fimc_2d: sysmmu@10A60000 {
+ compatible = "samsung,exynos4210-sysmmu";
+ reg = <0x10A60000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupt-names = "sysmmu-2d";
+ interrupts = <24 5>;
+ clock-names = "sysmmu";
+ clocks = <&clock 361>;
+ status = "ok";
};
};
--
1.7.2.5
On Fri, Jul 26, 2013 at 4:28 AM, Cho KyongHo <[email protected]> wrote:
> Signed-off-by: Cho KyongHo <[email protected]>
> ---
> .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> 5 files changed, 617 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>
> diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> new file mode 100644
> index 0000000..92f0a33
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> @@ -0,0 +1,103 @@
> +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> +
> +Samsung's Exynos architecture contains System MMU that enables scattered
Cho,
"MMU" should be plural? "MMUs"?
> +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> +
> +System MMU is a sort of IOMMU and support identical translation table format to
s/a sort of/an/ . Or perhaps "is also an". For the purposes of
documenting DMA support, we are talking about the IOMMU functionality
this device provides. It might be better to mention the functionality
the System MMU supports and refer to other subsystem documents (e,g,
clocking and power control) for details.
> +ARMv7 translation tables with minimum set of page properties including access
> +permissions, shareability and security protection. In addition, System MMU has
> +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> +latency.
> +
> +A System MMU is dedicated to a single master peripheral device. Thus, it is
> +important to specify the correct System MMU in the device node of its master
> +device. Whereas a System MMU is dedicated to a master device, the master device
> +may have more than one System MMU.
Can I suggest rewriting the last two sentences to:
The master device node must correctly specify at least one
SystemMMU. A master device may have more than one System MMU.
BTW, is there a difference between "master device" and "master
peripheral device" that I'm not aware of? Perhaps use just one of
those expressions in this document, not both if they are the same
thing (which is what I assumed).
cheers,
grant
> +
> +Required properties:
> +- compatible: Should be "samsung,exynos4210-sysmmu"
> +- reg: A tuple of base address and size of System MMU registers.
> +- interrupt-parent: The phandle of the interrupt controller of System MMU
> +- interrupts: A tuple of numbers that indicates the interrupt source.
> +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> + Please refer to the following documents:
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> + Optional "master" if the clock to the System MMU is gated by
> + another gate clock other than "sysmmu". The System MMU driver
> + sets "master" the parent of "sysmmu".
> + Exynos4 SoCs, there needs no "master" clocks.
> + Exynos5 SoCs, some System MMUs must have "master" clocks.
> +- clocks: Required if the System MMU is needed to gate its clock.
> + Please refer to the documents listed above.
> +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> + Please refer to the following document:
> + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> +
> +Required properties for the master peripheral devices:
> +- iommu: phandles to the System MMUs of the device
> +
> +Examples:
> +A System MMU is dedicated to a single master device.
> + gsc_0: gsc@0x13e00000 {
> + compatible = "samsung,exynos5-gsc";
> + reg = <0x13e00000 0x1000>;
> + interrupts = <0 85 0>;
> + samsung,power-domain = <&pd_gsc>;
> + clocks = <&clock 256>;
> + clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> + };
> +
> + sysmmu_gsc0: sysmmu@13E80000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E80000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc0";
> + interrupts = <2 0>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 262>, <&clock 256>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> +to define 2 System MMUs for each port of the MFC:
> +
> + mfc: codec@13400000 {
> + compatible = "samsung,mfc-v5";
> + reg = <0x13400000 0x10000>;
> + interrupts = <0 94 0>;
> + samsung,power-domain = <&pd_mfc>;
> + clocks = <&clock 170>, <&clock 273>;
> + clock-names = "sclk_mfc", "mfc";
> + status = "ok";
> + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@13620000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13620000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-l";
> + interrupts = <5 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 274>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@13630000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13630000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-r";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 275>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> index 359694c..ba74ee8 100644
> --- a/arch/arm/boot/dts/exynos4.dtsi
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -161,6 +161,7 @@
> interrupts = <0 94 0>;
> samsung,power-domain = <&pd_mfc>;
> status = "disabled";
> + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> };
>
> serial@13800000 {
> @@ -395,5 +396,126 @@
> clock-names = "sclk_fimd", "fimd";
> samsung,power-domain = <&pd_lcd0>;
> status = "disabled";
> + iommu = <&sysmmu_fimd0>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@13620000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13620000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-l";
> + interrupts = <5 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 274>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@13630000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13630000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-r";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 275>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_tv: sysmmu@13E20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-tv";
> + interrupts = <5 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 272>;
> + samsung,power-domain = <&pd_tv>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc0: sysmmu@11A20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc0";
> + interrupts = <4 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 263>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc1: sysmmu@11A30000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A30000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc1";
> + interrupts = <4 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 264>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc2: sysmmu@11A40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc2";
> + interrupts = <4 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 265>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc3: sysmmu@11A50000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A50000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc3";
> + interrupts = <4 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 266>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_jpeg: sysmmu@11A60000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A60000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-jpeg";
> + interrupts = <4 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 267>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_rotator: sysmmu@12A30000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12A30000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-rotator";
> + interrupts = <5 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 281>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd0: sysmmu@11E20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11E20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd0";
> + interrupts = <5 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 287>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> };
> };
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> index 54710de..09b13da 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -119,5 +119,30 @@
> reg = <0x12800000 0x1000>;
> interrupts = <0 89 0>;
> status = "disabled";
> + iommu = <&sysmmu_g2d>;
> + };
> +
> + sysmmu_g2d: sysmmu@12A20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12A20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-g2d";
> + interrupts = <4 7>;
> + clock-names = "sysmmu";
> + clocks = <&clock 280>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd1: sysmmu@12220000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd1";
> + reg = <0x12220000 0x1000>;
> + interrupts = <5 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 291>;
> + samsung,power-domain = <&pd_lcd1>;
> + status = "ok";
> };
> };
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index e3380a7..681db32 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -79,4 +79,80 @@
> interrupts = <0 89 0>;
> status = "disabled";
> };
> +
> + sysmmu_g2d: sysmmu@10A40000{
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x10A40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-g2d";
> + interrupts = <4 7>;
> + clock-names = "sysmmu";
> + status = "ok";
> + };
> +
> + sysmmu_fimc_isp: sysmmu@12260000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12260000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_isp";
> + interrupts = <16 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 362>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_drc: sysmmu@12270000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12270000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_drc";
> + interrupts = <16 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 363>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_fd: sysmmu@122A0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x122A0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_fd";
> + interrupts = <16 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 364>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_mcuctl: sysmmu@122B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x122B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_mcuctl";
> + interrupts = <16 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 376>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite0: sysmmu@123B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x123B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite0";
> + interrupts = <16 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 366>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite1: sysmmu@123C0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x123C0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite1";
> + interrupts = <16 1>;
> + clock-names = "sysmmu";
> + clocks = <&clock 365>;
> + status = "ok";
> + };
> };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index fc9fb3d..130d23d 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -66,6 +66,16 @@
> reg = <0x10044040 0x20>;
> };
>
> + pd_isp: mfc-power-domain@0x10044020 {
> + compatible = "samsung,exynos4210-pd";
> + reg = <0x10044020 0x20>;
> + };
> +
> + pd_disp1: mfc-power-domain@0x100440A0 {
> + compatible = "samsung,exynos4210-pd";
> + reg = <0x100440A0 0x20>;
> + };
> +
> clock: clock-controller@0x10010000 {
> compatible = "samsung,exynos5250-clock";
> reg = <0x10010000 0x30000>;
> @@ -180,6 +190,7 @@
> reg = <0x11000000 0x10000>;
> interrupts = <0 96 0>;
> samsung,power-domain = <&pd_mfc>;
> + iommu = <&sysmmu_mfc_l &sysmmu_mfc_l>;
> };
>
> rtc {
> @@ -571,6 +582,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 256>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> };
>
> gsc_1: gsc@0x13e10000 {
> @@ -580,6 +592,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 257>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> };
>
> gsc_2: gsc@0x13e20000 {
> @@ -589,6 +602,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 258>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc2>;
> };
>
> gsc_3: gsc@0x13e30000 {
> @@ -598,6 +612,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 259>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc3>;
> };
>
> hdmi {
> @@ -614,6 +629,7 @@
> compatible = "samsung,exynos5-mixer";
> reg = <0x14450000 0x10000>;
> interrupts = <0 94 0>;
> + iommu = <&sysmmu_tv>;
> };
>
> dp-controller {
> @@ -638,5 +654,280 @@
> interrupts = <18 4>, <18 5>, <18 6>;
> clocks = <&clock 133>, <&clock 339>;
> clock-names = "sclk_fimd", "fimd";
> + iommu = <&sysmmu_fimd1>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@11210000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11210000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc_l";
> + interrupts = <8 5>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 267>, <&clock 266>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@11200000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11200000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc_r";
> + interrupts = <6 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 268>, <&clock 266>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_tv: sysmmu@14650000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x14650000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-tv";
> + interrupts = <7 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 349>;
> + samsung,power-domain = <&pd_disp1>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc0: sysmmu@13E80000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E80000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc0";
> + interrupts = <2 0>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 262>, <&clock 256>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc1: sysmmu@13E90000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E90000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc1";
> + interrupts = <2 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 263>, <&clock 257>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc2: sysmmu@13EA0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13EA0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc2";
> + interrupts = <2 4>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 264>, <&clock 258>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc3: sysmmu@13EB0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13EB0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc3";
> + interrupts = <2 6>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 265>, <&clock 259>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd1: sysmmu@14640000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x14640000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd1";
> + interrupts = <3 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 350>;
> + samsung,power-domain = <&pd_disp1>;
> + status = "ok";
> + };
> +
> + sysmmu_rotator: sysmmu@11D40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11D40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-rotator";
> + interrupts = <4 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 272>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_isp: sysmmu@13260000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13260000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_isp";
> + interrupts = <10 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 361>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_drc: sysmmu@13270000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13270000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_drc";
> + interrupts = <11 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 362>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_fd: sysmmu@132A0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132A0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_fd";
> + interrupts = <5 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 363>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_scc: sysmmu@13280000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13280000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_scalerc";
> + interrupts = <5 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 364>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_scp: sysmmu@13290000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13290000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_scalerp";
> + interrupts = <3 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 365>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_mcuctl: sysmmu@132B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_mcuctl";
> + interrupts = <5 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 366>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_odc: sysmmu@132C0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132C0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_odc";
> + interrupts = <11 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 367>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_dis0: sysmmu@132D0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132D0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_dis0";
> + interrupts = <10 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 368>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_dis1: sysmmu@132E0000{
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132E0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_dis1";
> + interrupts = <9 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 369>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_3dnr: sysmmu@132F0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132F0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_3dnr";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 370>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite0: sysmmu@13C40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13C40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite0";
> + interrupts = <3 4>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 346>, <&clock 345>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite1: sysmmu@13C50000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13C50000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite1";
> + interrupts = <24 1>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 347>, <&clock 345>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_jpeg: sysmmu@11F20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11F20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-jpeg";
> + interrupts = <4 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 273>, <&clock 270>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_2d: sysmmu@10A60000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x10A60000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-2d";
> + interrupts = <24 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 361>;
> + status = "ok";
> };
> };
> --
> 1.7.2.5
>
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On Behalf Of Grant Grundler
> Sent: Saturday, July 27, 2013 2:58 AM
>
> On Fri, Jul 26, 2013 at 4:28 AM, Cho KyongHo <[email protected]> wrote:
> > Signed-off-by: Cho KyongHo <[email protected]>
> > ---
> > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > 5 files changed, 617 insertions(+), 0 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > new file mode 100644
> > index 0000000..92f0a33
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > @@ -0,0 +1,103 @@
> > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > +
> > +Samsung's Exynos architecture contains System MMU that enables scattered
>
> Cho,
> "MMU" should be plural? "MMUs"?
>
An Exynos SoC has tens of System MMUs.
I agree with you.
Thanks.
> > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > +
> > +System MMU is a sort of IOMMU and support identical translation table format to
>
> s/a sort of/an/ . Or perhaps "is also an". For the purposes of
> documenting DMA support, we are talking about the IOMMU functionality
> this device provides. It might be better to mention the functionality
> the System MMU supports and refer to other subsystem documents (e,g,
> clocking and power control) for details.
>
Thank you for the advice.
Let me check the details in another documents.
> > +ARMv7 translation tables with minimum set of page properties including access
> > +permissions, shareability and security protection. In addition, System MMU has
> > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > +latency.
> > +
> > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > +important to specify the correct System MMU in the device node of its master
> > +device. Whereas a System MMU is dedicated to a master device, the master device
> > +may have more than one System MMU.
>
> Can I suggest rewriting the last two sentences to:
> The master device node must correctly specify at least one
> SystemMMU. A master device may have more than one System MMU.
>
Thanks. It looks much clearer than my expression.
> BTW, is there a difference between "master device" and "master
> peripheral device" that I'm not aware of? Perhaps use just one of
> those expressions in this document, not both if they are the same
> thing (which is what I assumed).
>
You assumed correctly.
I meant them the same thing.
Thank you for the detail and kind review.
> cheers,
> grant
>
> > +
> > +Required properties:
> > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > +- reg: A tuple of base address and size of System MMU registers.
> > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > + Please refer to the following documents:
> > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > + Optional "master" if the clock to the System MMU is gated by
> > + another gate clock other than "sysmmu". The System MMU driver
> > + sets "master" the parent of "sysmmu".
> > + Exynos4 SoCs, there needs no "master" clocks.
> > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > +- clocks: Required if the System MMU is needed to gate its clock.
> > + Please refer to the documents listed above.
> > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > + Please refer to the following document:
> > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > +
> > +Required properties for the master peripheral devices:
> > +- iommu: phandles to the System MMUs of the device
> > +
> > +Examples:
> > +A System MMU is dedicated to a single master device.
> > + gsc_0: gsc@0x13e00000 {
> > + compatible = "samsung,exynos5-gsc";
> > + reg = <0x13e00000 0x1000>;
> > + interrupts = <0 85 0>;
> > + samsung,power-domain = <&pd_gsc>;
> > + clocks = <&clock 256>;
> > + clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > + };
> > +
> > + sysmmu_gsc0: sysmmu@13E80000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E80000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc0";
> > + interrupts = <2 0>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 262>, <&clock 256>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> > +to define 2 System MMUs for each port of the MFC:
> > +
> > + mfc: codec@13400000 {
> > + compatible = "samsung,mfc-v5";
> > + reg = <0x13400000 0x10000>;
> > + interrupts = <0 94 0>;
> > + samsung,power-domain = <&pd_mfc>;
> > + clocks = <&clock 170>, <&clock 273>;
> > + clock-names = "sclk_mfc", "mfc";
> > + status = "ok";
> > + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@13620000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13620000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-l";
> > + interrupts = <5 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 274>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@13630000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13630000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-r";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 275>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> > index 359694c..ba74ee8 100644
> > --- a/arch/arm/boot/dts/exynos4.dtsi
> > +++ b/arch/arm/boot/dts/exynos4.dtsi
> > @@ -161,6 +161,7 @@
> > interrupts = <0 94 0>;
> > samsung,power-domain = <&pd_mfc>;
> > status = "disabled";
> > + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> > };
> >
> > serial@13800000 {
> > @@ -395,5 +396,126 @@
> > clock-names = "sclk_fimd", "fimd";
> > samsung,power-domain = <&pd_lcd0>;
> > status = "disabled";
> > + iommu = <&sysmmu_fimd0>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@13620000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13620000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-l";
> > + interrupts = <5 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 274>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@13630000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13630000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-r";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 275>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_tv: sysmmu@13E20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-tv";
> > + interrupts = <5 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 272>;
> > + samsung,power-domain = <&pd_tv>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc0: sysmmu@11A20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc0";
> > + interrupts = <4 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 263>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc1: sysmmu@11A30000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A30000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc1";
> > + interrupts = <4 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 264>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc2: sysmmu@11A40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc2";
> > + interrupts = <4 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 265>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc3: sysmmu@11A50000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A50000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc3";
> > + interrupts = <4 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 266>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_jpeg: sysmmu@11A60000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A60000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-jpeg";
> > + interrupts = <4 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 267>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_rotator: sysmmu@12A30000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12A30000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-rotator";
> > + interrupts = <5 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 281>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd0: sysmmu@11E20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11E20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd0";
> > + interrupts = <5 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 287>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> > index 54710de..09b13da 100644
> > --- a/arch/arm/boot/dts/exynos4210.dtsi
> > +++ b/arch/arm/boot/dts/exynos4210.dtsi
> > @@ -119,5 +119,30 @@
> > reg = <0x12800000 0x1000>;
> > interrupts = <0 89 0>;
> > status = "disabled";
> > + iommu = <&sysmmu_g2d>;
> > + };
> > +
> > + sysmmu_g2d: sysmmu@12A20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12A20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-g2d";
> > + interrupts = <4 7>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 280>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd1: sysmmu@12220000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd1";
> > + reg = <0x12220000 0x1000>;
> > + interrupts = <5 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 291>;
> > + samsung,power-domain = <&pd_lcd1>;
> > + status = "ok";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> > index e3380a7..681db32 100644
> > --- a/arch/arm/boot/dts/exynos4x12.dtsi
> > +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> > @@ -79,4 +79,80 @@
> > interrupts = <0 89 0>;
> > status = "disabled";
> > };
> > +
> > + sysmmu_g2d: sysmmu@10A40000{
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x10A40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-g2d";
> > + interrupts = <4 7>;
> > + clock-names = "sysmmu";
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_isp: sysmmu@12260000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12260000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_isp";
> > + interrupts = <16 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 362>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_drc: sysmmu@12270000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12270000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_drc";
> > + interrupts = <16 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 363>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_fd: sysmmu@122A0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x122A0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_fd";
> > + interrupts = <16 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 364>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_mcuctl: sysmmu@122B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x122B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_mcuctl";
> > + interrupts = <16 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 376>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite0: sysmmu@123B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x123B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite0";
> > + interrupts = <16 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 366>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite1: sysmmu@123C0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x123C0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite1";
> > + interrupts = <16 1>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 365>;
> > + status = "ok";
> > + };
> > };
> > diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> > index fc9fb3d..130d23d 100644
> > --- a/arch/arm/boot/dts/exynos5250.dtsi
> > +++ b/arch/arm/boot/dts/exynos5250.dtsi
> > @@ -66,6 +66,16 @@
> > reg = <0x10044040 0x20>;
> > };
> >
> > + pd_isp: mfc-power-domain@0x10044020 {
> > + compatible = "samsung,exynos4210-pd";
> > + reg = <0x10044020 0x20>;
> > + };
> > +
> > + pd_disp1: mfc-power-domain@0x100440A0 {
> > + compatible = "samsung,exynos4210-pd";
> > + reg = <0x100440A0 0x20>;
> > + };
> > +
> > clock: clock-controller@0x10010000 {
> > compatible = "samsung,exynos5250-clock";
> > reg = <0x10010000 0x30000>;
> > @@ -180,6 +190,7 @@
> > reg = <0x11000000 0x10000>;
> > interrupts = <0 96 0>;
> > samsung,power-domain = <&pd_mfc>;
> > + iommu = <&sysmmu_mfc_l &sysmmu_mfc_l>;
> > };
> >
> > rtc {
> > @@ -571,6 +582,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 256>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > };
> >
> > gsc_1: gsc@0x13e10000 {
> > @@ -580,6 +592,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 257>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > };
> >
> > gsc_2: gsc@0x13e20000 {
> > @@ -589,6 +602,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 258>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc2>;
> > };
> >
> > gsc_3: gsc@0x13e30000 {
> > @@ -598,6 +612,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 259>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc3>;
> > };
> >
> > hdmi {
> > @@ -614,6 +629,7 @@
> > compatible = "samsung,exynos5-mixer";
> > reg = <0x14450000 0x10000>;
> > interrupts = <0 94 0>;
> > + iommu = <&sysmmu_tv>;
> > };
> >
> > dp-controller {
> > @@ -638,5 +654,280 @@
> > interrupts = <18 4>, <18 5>, <18 6>;
> > clocks = <&clock 133>, <&clock 339>;
> > clock-names = "sclk_fimd", "fimd";
> > + iommu = <&sysmmu_fimd1>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@11210000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11210000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc_l";
> > + interrupts = <8 5>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 267>, <&clock 266>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@11200000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11200000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc_r";
> > + interrupts = <6 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 268>, <&clock 266>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_tv: sysmmu@14650000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x14650000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-tv";
> > + interrupts = <7 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 349>;
> > + samsung,power-domain = <&pd_disp1>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc0: sysmmu@13E80000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E80000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc0";
> > + interrupts = <2 0>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 262>, <&clock 256>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc1: sysmmu@13E90000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E90000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc1";
> > + interrupts = <2 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 263>, <&clock 257>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc2: sysmmu@13EA0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13EA0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc2";
> > + interrupts = <2 4>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 264>, <&clock 258>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc3: sysmmu@13EB0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13EB0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc3";
> > + interrupts = <2 6>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 265>, <&clock 259>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd1: sysmmu@14640000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x14640000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd1";
> > + interrupts = <3 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 350>;
> > + samsung,power-domain = <&pd_disp1>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_rotator: sysmmu@11D40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11D40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-rotator";
> > + interrupts = <4 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 272>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_isp: sysmmu@13260000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13260000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_isp";
> > + interrupts = <10 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 361>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_drc: sysmmu@13270000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13270000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_drc";
> > + interrupts = <11 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 362>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_fd: sysmmu@132A0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132A0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_fd";
> > + interrupts = <5 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 363>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_scc: sysmmu@13280000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13280000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_scalerc";
> > + interrupts = <5 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 364>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_scp: sysmmu@13290000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13290000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_scalerp";
> > + interrupts = <3 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 365>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_mcuctl: sysmmu@132B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_mcuctl";
> > + interrupts = <5 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 366>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_odc: sysmmu@132C0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132C0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_odc";
> > + interrupts = <11 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 367>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_dis0: sysmmu@132D0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132D0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_dis0";
> > + interrupts = <10 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 368>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_dis1: sysmmu@132E0000{
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132E0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_dis1";
> > + interrupts = <9 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 369>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_3dnr: sysmmu@132F0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132F0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_3dnr";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 370>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite0: sysmmu@13C40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13C40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite0";
> > + interrupts = <3 4>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 346>, <&clock 345>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite1: sysmmu@13C50000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13C50000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite1";
> > + interrupts = <24 1>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 347>, <&clock 345>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_jpeg: sysmmu@11F20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11F20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-jpeg";
> > + interrupts = <4 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 273>, <&clock 270>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_2d: sysmmu@10A60000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x10A60000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-2d";
> > + interrupts = <24 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 361>;
> > + status = "ok";
> > };
> > };
> > --
> > 1.7.2.5
> >
> >
On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo <[email protected]> wrote:
> Signed-off-by: Cho KyongHo <[email protected]>
> ---
> .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> 5 files changed, 617 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>
> diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> new file mode 100644
> index 0000000..92f0a33
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> @@ -0,0 +1,103 @@
> +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> +
> +Samsung's Exynos architecture contains System MMU that enables scattered
> +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> +
> +System MMU is a sort of IOMMU and support identical translation table format to
> +ARMv7 translation tables with minimum set of page properties including access
> +permissions, shareability and security protection. In addition, System MMU has
> +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> +latency.
> +
> +A System MMU is dedicated to a single master peripheral device. Thus, it is
> +important to specify the correct System MMU in the device node of its master
> +device. Whereas a System MMU is dedicated to a master device, the master device
> +may have more than one System MMU.
I don't follow the last sentence. Can you elaborate on the type of
connection you are talking about.
Also, please align with the ARM system MMU binding that Will Deacon
has submitted particularly in terms of how master connections are
described.
Rob
> +
> +Required properties:
> +- compatible: Should be "samsung,exynos4210-sysmmu"
> +- reg: A tuple of base address and size of System MMU registers.
> +- interrupt-parent: The phandle of the interrupt controller of System MMU
> +- interrupts: A tuple of numbers that indicates the interrupt source.
> +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> + Please refer to the following documents:
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> + Optional "master" if the clock to the System MMU is gated by
> + another gate clock other than "sysmmu". The System MMU driver
> + sets "master" the parent of "sysmmu".
> + Exynos4 SoCs, there needs no "master" clocks.
> + Exynos5 SoCs, some System MMUs must have "master" clocks.
> +- clocks: Required if the System MMU is needed to gate its clock.
> + Please refer to the documents listed above.
> +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> + Please refer to the following document:
> + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> +
> +Required properties for the master peripheral devices:
> +- iommu: phandles to the System MMUs of the device
> +
> +Examples:
> +A System MMU is dedicated to a single master device.
> + gsc_0: gsc@0x13e00000 {
> + compatible = "samsung,exynos5-gsc";
> + reg = <0x13e00000 0x1000>;
> + interrupts = <0 85 0>;
> + samsung,power-domain = <&pd_gsc>;
> + clocks = <&clock 256>;
> + clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> + };
> +
> + sysmmu_gsc0: sysmmu@13E80000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E80000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc0";
> + interrupts = <2 0>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 262>, <&clock 256>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> +to define 2 System MMUs for each port of the MFC:
> +
> + mfc: codec@13400000 {
> + compatible = "samsung,mfc-v5";
> + reg = <0x13400000 0x10000>;
> + interrupts = <0 94 0>;
> + samsung,power-domain = <&pd_mfc>;
> + clocks = <&clock 170>, <&clock 273>;
> + clock-names = "sclk_mfc", "mfc";
> + status = "ok";
> + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@13620000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13620000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-l";
> + interrupts = <5 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 274>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@13630000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13630000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-r";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 275>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> index 359694c..ba74ee8 100644
> --- a/arch/arm/boot/dts/exynos4.dtsi
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -161,6 +161,7 @@
> interrupts = <0 94 0>;
> samsung,power-domain = <&pd_mfc>;
> status = "disabled";
> + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> };
>
> serial@13800000 {
> @@ -395,5 +396,126 @@
> clock-names = "sclk_fimd", "fimd";
> samsung,power-domain = <&pd_lcd0>;
> status = "disabled";
> + iommu = <&sysmmu_fimd0>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@13620000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13620000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-l";
> + interrupts = <5 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 274>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@13630000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13630000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-r";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 275>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_tv: sysmmu@13E20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-tv";
> + interrupts = <5 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 272>;
> + samsung,power-domain = <&pd_tv>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc0: sysmmu@11A20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc0";
> + interrupts = <4 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 263>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc1: sysmmu@11A30000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A30000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc1";
> + interrupts = <4 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 264>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc2: sysmmu@11A40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc2";
> + interrupts = <4 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 265>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc3: sysmmu@11A50000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A50000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc3";
> + interrupts = <4 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 266>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_jpeg: sysmmu@11A60000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A60000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-jpeg";
> + interrupts = <4 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 267>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_rotator: sysmmu@12A30000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12A30000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-rotator";
> + interrupts = <5 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 281>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd0: sysmmu@11E20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11E20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd0";
> + interrupts = <5 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 287>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> };
> };
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> index 54710de..09b13da 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -119,5 +119,30 @@
> reg = <0x12800000 0x1000>;
> interrupts = <0 89 0>;
> status = "disabled";
> + iommu = <&sysmmu_g2d>;
> + };
> +
> + sysmmu_g2d: sysmmu@12A20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12A20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-g2d";
> + interrupts = <4 7>;
> + clock-names = "sysmmu";
> + clocks = <&clock 280>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd1: sysmmu@12220000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd1";
> + reg = <0x12220000 0x1000>;
> + interrupts = <5 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 291>;
> + samsung,power-domain = <&pd_lcd1>;
> + status = "ok";
> };
> };
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index e3380a7..681db32 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -79,4 +79,80 @@
> interrupts = <0 89 0>;
> status = "disabled";
> };
> +
> + sysmmu_g2d: sysmmu@10A40000{
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x10A40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-g2d";
> + interrupts = <4 7>;
> + clock-names = "sysmmu";
> + status = "ok";
> + };
> +
> + sysmmu_fimc_isp: sysmmu@12260000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12260000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_isp";
> + interrupts = <16 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 362>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_drc: sysmmu@12270000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12270000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_drc";
> + interrupts = <16 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 363>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_fd: sysmmu@122A0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x122A0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_fd";
> + interrupts = <16 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 364>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_mcuctl: sysmmu@122B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x122B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_mcuctl";
> + interrupts = <16 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 376>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite0: sysmmu@123B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x123B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite0";
> + interrupts = <16 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 366>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite1: sysmmu@123C0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x123C0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite1";
> + interrupts = <16 1>;
> + clock-names = "sysmmu";
> + clocks = <&clock 365>;
> + status = "ok";
> + };
> };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index fc9fb3d..130d23d 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -66,6 +66,16 @@
> reg = <0x10044040 0x20>;
> };
>
> + pd_isp: mfc-power-domain@0x10044020 {
> + compatible = "samsung,exynos4210-pd";
> + reg = <0x10044020 0x20>;
> + };
> +
> + pd_disp1: mfc-power-domain@0x100440A0 {
> + compatible = "samsung,exynos4210-pd";
> + reg = <0x100440A0 0x20>;
> + };
> +
> clock: clock-controller@0x10010000 {
> compatible = "samsung,exynos5250-clock";
> reg = <0x10010000 0x30000>;
> @@ -180,6 +190,7 @@
> reg = <0x11000000 0x10000>;
> interrupts = <0 96 0>;
> samsung,power-domain = <&pd_mfc>;
> + iommu = <&sysmmu_mfc_l &sysmmu_mfc_l>;
> };
>
> rtc {
> @@ -571,6 +582,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 256>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> };
>
> gsc_1: gsc@0x13e10000 {
> @@ -580,6 +592,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 257>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> };
>
> gsc_2: gsc@0x13e20000 {
> @@ -589,6 +602,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 258>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc2>;
> };
>
> gsc_3: gsc@0x13e30000 {
> @@ -598,6 +612,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 259>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc3>;
> };
>
> hdmi {
> @@ -614,6 +629,7 @@
> compatible = "samsung,exynos5-mixer";
> reg = <0x14450000 0x10000>;
> interrupts = <0 94 0>;
> + iommu = <&sysmmu_tv>;
> };
>
> dp-controller {
> @@ -638,5 +654,280 @@
> interrupts = <18 4>, <18 5>, <18 6>;
> clocks = <&clock 133>, <&clock 339>;
> clock-names = "sclk_fimd", "fimd";
> + iommu = <&sysmmu_fimd1>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@11210000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11210000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc_l";
> + interrupts = <8 5>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 267>, <&clock 266>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@11200000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11200000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc_r";
> + interrupts = <6 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 268>, <&clock 266>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_tv: sysmmu@14650000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x14650000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-tv";
> + interrupts = <7 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 349>;
> + samsung,power-domain = <&pd_disp1>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc0: sysmmu@13E80000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E80000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc0";
> + interrupts = <2 0>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 262>, <&clock 256>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc1: sysmmu@13E90000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E90000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc1";
> + interrupts = <2 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 263>, <&clock 257>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc2: sysmmu@13EA0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13EA0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc2";
> + interrupts = <2 4>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 264>, <&clock 258>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc3: sysmmu@13EB0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13EB0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc3";
> + interrupts = <2 6>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 265>, <&clock 259>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd1: sysmmu@14640000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x14640000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd1";
> + interrupts = <3 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 350>;
> + samsung,power-domain = <&pd_disp1>;
> + status = "ok";
> + };
> +
> + sysmmu_rotator: sysmmu@11D40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11D40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-rotator";
> + interrupts = <4 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 272>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_isp: sysmmu@13260000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13260000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_isp";
> + interrupts = <10 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 361>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_drc: sysmmu@13270000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13270000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_drc";
> + interrupts = <11 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 362>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_fd: sysmmu@132A0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132A0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_fd";
> + interrupts = <5 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 363>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_scc: sysmmu@13280000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13280000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_scalerc";
> + interrupts = <5 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 364>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_scp: sysmmu@13290000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13290000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_scalerp";
> + interrupts = <3 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 365>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_mcuctl: sysmmu@132B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_mcuctl";
> + interrupts = <5 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 366>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_odc: sysmmu@132C0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132C0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_odc";
> + interrupts = <11 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 367>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_dis0: sysmmu@132D0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132D0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_dis0";
> + interrupts = <10 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 368>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_dis1: sysmmu@132E0000{
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132E0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_dis1";
> + interrupts = <9 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 369>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_3dnr: sysmmu@132F0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132F0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_3dnr";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 370>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite0: sysmmu@13C40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13C40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite0";
> + interrupts = <3 4>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 346>, <&clock 345>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite1: sysmmu@13C50000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13C50000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite1";
> + interrupts = <24 1>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 347>, <&clock 345>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_jpeg: sysmmu@11F20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11F20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-jpeg";
> + interrupts = <4 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 273>, <&clock 270>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_2d: sysmmu@10A60000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x10A60000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-2d";
> + interrupts = <24 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 361>;
> + status = "ok";
> };
> };
> --
> 1.7.2.5
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi KyongHo,
On 26 July 2013 16:58, Cho KyongHo <[email protected]> wrote:
> Signed-off-by: Cho KyongHo <[email protected]>
> ---
> .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> 5 files changed, 617 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
This patch does not apply on the mainline Linus' tree (3.11-rc2). Please rebase.
--
With warm regards,
Sachin
> -----Original Message-----
> From: Sachin Kamat [mailto:[email protected]]
> Sent: Monday, July 29, 2013 3:38 PM
>
> Hi KyongHo,
>
> On 26 July 2013 16:58, Cho KyongHo <[email protected]> wrote:
> > Signed-off-by: Cho KyongHo <[email protected]>
> > ---
> > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > 5 files changed, 617 insertions(+), 0 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>
> This patch does not apply on the mainline Linus' tree (3.11-rc2). Please rebase.
>
OK. I will rebase the next patches on that.
Thank you.
Cho KyongHo.
> --
> With warm regards,
> Sachin
> -----Original Message-----
> From: Cho KyongHo [mailto:[email protected]]
> Sent: Monday, July 29, 2013 4:20 PM
>
> > -----Original Message-----
> > From: Sachin Kamat [mailto:[email protected]]
> > Sent: Monday, July 29, 2013 3:38 PM
> >
> > Hi KyongHo,
> >
> > On 26 July 2013 16:58, Cho KyongHo <[email protected]> wrote:
> > > Signed-off-by: Cho KyongHo <[email protected]>
> > > ---
> > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > > 5 files changed, 617 insertions(+), 0 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> >
> > This patch does not apply on the mainline Linus' tree (3.11-rc2). Please rebase.
> >
>
> OK. I will rebase the next patches on that.
I don't get any conflict both on the latest of Linus's tree (3.11-rc3)
and for-next branch of Samsung git.
Can you show me the diff?
>
> Thank you.
>
> Cho KyongHo.
> > --
> > With warm regards,
> > Sachin
On 29 July 2013 13:27, Cho KyongHo <[email protected]> wrote:
>> -----Original Message-----
>> From: Cho KyongHo [mailto:[email protected]]
>> Sent: Monday, July 29, 2013 4:20 PM
>>
>> > -----Original Message-----
>> > From: Sachin Kamat [mailto:[email protected]]
>> > Sent: Monday, July 29, 2013 3:38 PM
>> >
>> > Hi KyongHo,
>> >
>> > On 26 July 2013 16:58, Cho KyongHo <[email protected]> wrote:
>> > > Signed-off-by: Cho KyongHo <[email protected]>
>> > > ---
>> > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
>> > > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
>> > > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
>> > > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
>> > > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
>> > > 5 files changed, 617 insertions(+), 0 deletions(-)
>> > > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>> >
>> > This patch does not apply on the mainline Linus' tree (3.11-rc2). Please rebase.
>> >
>>
>> OK. I will rebase the next patches on that.
>
> I don't get any conflict both on the latest of Linus's tree (3.11-rc3)
> and for-next branch of Samsung git.
> Can you show me the diff?
>
I get the following error when I do git am on this patch (linus' tree
3.11-rc3). Other patches apply fine.
Applying: ARM: dts: Add description of System MMU of Exynos SoCs
<local_path>/linux/.git/rebase-apply/patch:120: new blank line at EOF.
+
error: patch failed: arch/arm/boot/dts/exynos4.dtsi:161
error: arch/arm/boot/dts/exynos4.dtsi: patch does not apply
error: patch failed: arch/arm/boot/dts/exynos4210.dtsi:119
error: arch/arm/boot/dts/exynos4210.dtsi: patch does not apply
error: patch failed: arch/arm/boot/dts/exynos4x12.dtsi:79
error: arch/arm/boot/dts/exynos4x12.dtsi: patch does not apply
error: patch failed: arch/arm/boot/dts/exynos5250.dtsi:614
error: arch/arm/boot/dts/exynos5250.dtsi: patch does not apply
Patch failed at 0001 ARM: dts: Add description of System MMU of Exynos SoCs
When you have resolved this problem run "git am --resolved".
If you would prefer to skip this patch, instead run "git am --skip".
To restore the original branch and stop patching run "git am --abort".
--
With warm regards,
Sachin
> -----Original Message-----
> From: Rob Herring [mailto:[email protected]]
> Sent: Saturday, July 27, 2013 10:55 PM
> On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo <[email protected]> wrote:
> > Signed-off-by: Cho KyongHo <[email protected]>
> > ---
> > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > 5 files changed, 617 insertions(+), 0 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > new file mode 100644
> > index 0000000..92f0a33
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > @@ -0,0 +1,103 @@
> > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > +
> > +Samsung's Exynos architecture contains System MMU that enables scattered
> > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > +
> > +System MMU is a sort of IOMMU and support identical translation table format to
> > +ARMv7 translation tables with minimum set of page properties including access
> > +permissions, shareability and security protection. In addition, System MMU has
> > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > +latency.
> > +
> > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > +important to specify the correct System MMU in the device node of its master
> > +device. Whereas a System MMU is dedicated to a master device, the master device
> > +may have more than one System MMU.
>
> I don't follow the last sentence. Can you elaborate on the type of
> connection you are talking about.
>
Grant also addressed that.
He corrected the sentence like the following:
" Can I suggest rewriting the last two sentences to:
The master device node must correctly specify at least one
SystemMMU. A master device may have more than one System MMU. "
I will change the sentence
> Also, please align with the ARM system MMU binding that Will Deacon
> has submitted particularly in terms of how master connections are
> described.
>
I didn't check it.
Should this align with ARM System MMU bindings?
System MMU in Exynos SoC is different from ARM System MMU.
It does not follows the specifications of ARM System MMU.
> Rob
>
> > +
> > +Required properties:
> > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > +- reg: A tuple of base address and size of System MMU registers.
> > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > + Please refer to the following documents:
> > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > + Optional "master" if the clock to the System MMU is gated by
> > + another gate clock other than "sysmmu". The System MMU driver
> > + sets "master" the parent of "sysmmu".
> > + Exynos4 SoCs, there needs no "master" clocks.
> > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > +- clocks: Required if the System MMU is needed to gate its clock.
> > + Please refer to the documents listed above.
> > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > + Please refer to the following document:
> > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > +
> > +Required properties for the master peripheral devices:
> > +- iommu: phandles to the System MMUs of the device
> > +
> > +Examples:
> > +A System MMU is dedicated to a single master device.
> > + gsc_0: gsc@0x13e00000 {
> > + compatible = "samsung,exynos5-gsc";
> > + reg = <0x13e00000 0x1000>;
> > + interrupts = <0 85 0>;
> > + samsung,power-domain = <&pd_gsc>;
> > + clocks = <&clock 256>;
> > + clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > + };
> > +
> > + sysmmu_gsc0: sysmmu@13E80000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E80000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc0";
> > + interrupts = <2 0>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 262>, <&clock 256>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> > +to define 2 System MMUs for each port of the MFC:
> > +
> > + mfc: codec@13400000 {
> > + compatible = "samsung,mfc-v5";
> > + reg = <0x13400000 0x10000>;
> > + interrupts = <0 94 0>;
> > + samsung,power-domain = <&pd_mfc>;
> > + clocks = <&clock 170>, <&clock 273>;
> > + clock-names = "sclk_mfc", "mfc";
> > + status = "ok";
> > + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@13620000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13620000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-l";
> > + interrupts = <5 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 274>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@13630000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13630000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-r";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 275>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> > index 359694c..ba74ee8 100644
> > --- a/arch/arm/boot/dts/exynos4.dtsi
> > +++ b/arch/arm/boot/dts/exynos4.dtsi
> > @@ -161,6 +161,7 @@
> > interrupts = <0 94 0>;
> > samsung,power-domain = <&pd_mfc>;
> > status = "disabled";
> > + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> > };
> >
> > serial@13800000 {
> > @@ -395,5 +396,126 @@
> > clock-names = "sclk_fimd", "fimd";
> > samsung,power-domain = <&pd_lcd0>;
> > status = "disabled";
> > + iommu = <&sysmmu_fimd0>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@13620000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13620000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-l";
> > + interrupts = <5 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 274>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@13630000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13630000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-r";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 275>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_tv: sysmmu@13E20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-tv";
> > + interrupts = <5 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 272>;
> > + samsung,power-domain = <&pd_tv>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc0: sysmmu@11A20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc0";
> > + interrupts = <4 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 263>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc1: sysmmu@11A30000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A30000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc1";
> > + interrupts = <4 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 264>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc2: sysmmu@11A40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc2";
> > + interrupts = <4 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 265>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc3: sysmmu@11A50000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A50000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc3";
> > + interrupts = <4 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 266>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_jpeg: sysmmu@11A60000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A60000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-jpeg";
> > + interrupts = <4 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 267>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_rotator: sysmmu@12A30000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12A30000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-rotator";
> > + interrupts = <5 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 281>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd0: sysmmu@11E20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11E20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd0";
> > + interrupts = <5 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 287>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> > index 54710de..09b13da 100644
> > --- a/arch/arm/boot/dts/exynos4210.dtsi
> > +++ b/arch/arm/boot/dts/exynos4210.dtsi
> > @@ -119,5 +119,30 @@
> > reg = <0x12800000 0x1000>;
> > interrupts = <0 89 0>;
> > status = "disabled";
> > + iommu = <&sysmmu_g2d>;
> > + };
> > +
> > + sysmmu_g2d: sysmmu@12A20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12A20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-g2d";
> > + interrupts = <4 7>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 280>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd1: sysmmu@12220000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd1";
> > + reg = <0x12220000 0x1000>;
> > + interrupts = <5 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 291>;
> > + samsung,power-domain = <&pd_lcd1>;
> > + status = "ok";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> > index e3380a7..681db32 100644
> > --- a/arch/arm/boot/dts/exynos4x12.dtsi
> > +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> > @@ -79,4 +79,80 @@
> > interrupts = <0 89 0>;
> > status = "disabled";
> > };
> > +
> > + sysmmu_g2d: sysmmu@10A40000{
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x10A40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-g2d";
> > + interrupts = <4 7>;
> > + clock-names = "sysmmu";
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_isp: sysmmu@12260000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12260000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_isp";
> > + interrupts = <16 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 362>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_drc: sysmmu@12270000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12270000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_drc";
> > + interrupts = <16 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 363>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_fd: sysmmu@122A0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x122A0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_fd";
> > + interrupts = <16 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 364>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_mcuctl: sysmmu@122B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x122B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_mcuctl";
> > + interrupts = <16 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 376>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite0: sysmmu@123B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x123B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite0";
> > + interrupts = <16 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 366>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite1: sysmmu@123C0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x123C0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite1";
> > + interrupts = <16 1>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 365>;
> > + status = "ok";
> > + };
> > };
> > diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> > index fc9fb3d..130d23d 100644
> > --- a/arch/arm/boot/dts/exynos5250.dtsi
> > +++ b/arch/arm/boot/dts/exynos5250.dtsi
> > @@ -66,6 +66,16 @@
> > reg = <0x10044040 0x20>;
> > };
> >
> > + pd_isp: mfc-power-domain@0x10044020 {
> > + compatible = "samsung,exynos4210-pd";
> > + reg = <0x10044020 0x20>;
> > + };
> > +
> > + pd_disp1: mfc-power-domain@0x100440A0 {
> > + compatible = "samsung,exynos4210-pd";
> > + reg = <0x100440A0 0x20>;
> > + };
> > +
> > clock: clock-controller@0x10010000 {
> > compatible = "samsung,exynos5250-clock";
> > reg = <0x10010000 0x30000>;
> > @@ -180,6 +190,7 @@
> > reg = <0x11000000 0x10000>;
> > interrupts = <0 96 0>;
> > samsung,power-domain = <&pd_mfc>;
> > + iommu = <&sysmmu_mfc_l &sysmmu_mfc_l>;
> > };
> >
> > rtc {
> > @@ -571,6 +582,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 256>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > };
> >
> > gsc_1: gsc@0x13e10000 {
> > @@ -580,6 +592,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 257>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > };
> >
> > gsc_2: gsc@0x13e20000 {
> > @@ -589,6 +602,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 258>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc2>;
> > };
> >
> > gsc_3: gsc@0x13e30000 {
> > @@ -598,6 +612,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 259>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc3>;
> > };
> >
> > hdmi {
> > @@ -614,6 +629,7 @@
> > compatible = "samsung,exynos5-mixer";
> > reg = <0x14450000 0x10000>;
> > interrupts = <0 94 0>;
> > + iommu = <&sysmmu_tv>;
> > };
> >
> > dp-controller {
> > @@ -638,5 +654,280 @@
> > interrupts = <18 4>, <18 5>, <18 6>;
> > clocks = <&clock 133>, <&clock 339>;
> > clock-names = "sclk_fimd", "fimd";
> > + iommu = <&sysmmu_fimd1>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@11210000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11210000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc_l";
> > + interrupts = <8 5>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 267>, <&clock 266>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@11200000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11200000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc_r";
> > + interrupts = <6 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 268>, <&clock 266>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_tv: sysmmu@14650000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x14650000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-tv";
> > + interrupts = <7 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 349>;
> > + samsung,power-domain = <&pd_disp1>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc0: sysmmu@13E80000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E80000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc0";
> > + interrupts = <2 0>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 262>, <&clock 256>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc1: sysmmu@13E90000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E90000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc1";
> > + interrupts = <2 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 263>, <&clock 257>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc2: sysmmu@13EA0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13EA0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc2";
> > + interrupts = <2 4>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 264>, <&clock 258>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc3: sysmmu@13EB0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13EB0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc3";
> > + interrupts = <2 6>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 265>, <&clock 259>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd1: sysmmu@14640000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x14640000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd1";
> > + interrupts = <3 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 350>;
> > + samsung,power-domain = <&pd_disp1>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_rotator: sysmmu@11D40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11D40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-rotator";
> > + interrupts = <4 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 272>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_isp: sysmmu@13260000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13260000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_isp";
> > + interrupts = <10 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 361>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_drc: sysmmu@13270000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13270000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_drc";
> > + interrupts = <11 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 362>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_fd: sysmmu@132A0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132A0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_fd";
> > + interrupts = <5 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 363>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_scc: sysmmu@13280000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13280000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_scalerc";
> > + interrupts = <5 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 364>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_scp: sysmmu@13290000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13290000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_scalerp";
> > + interrupts = <3 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 365>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_mcuctl: sysmmu@132B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_mcuctl";
> > + interrupts = <5 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 366>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_odc: sysmmu@132C0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132C0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_odc";
> > + interrupts = <11 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 367>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_dis0: sysmmu@132D0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132D0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_dis0";
> > + interrupts = <10 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 368>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_dis1: sysmmu@132E0000{
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132E0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_dis1";
> > + interrupts = <9 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 369>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_3dnr: sysmmu@132F0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132F0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_3dnr";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 370>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite0: sysmmu@13C40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13C40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite0";
> > + interrupts = <3 4>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 346>, <&clock 345>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite1: sysmmu@13C50000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13C50000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite1";
> > + interrupts = <24 1>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 347>, <&clock 345>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_jpeg: sysmmu@11F20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11F20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-jpeg";
> > + interrupts = <4 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 273>, <&clock 270>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_2d: sysmmu@10A60000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x10A60000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-2d";
> > + interrupts = <24 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 361>;
> > + status = "ok";
> > };
> > };
> > --
> > 1.7.2.5
> >
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> -----Original Message-----
> From: Sachin Kamat [mailto:[email protected]]
> Sent: Monday, July 29, 2013 5:05 PM
>
> On 29 July 2013 13:27, Cho KyongHo <[email protected]> wrote:
> >> -----Original Message-----
> >> From: Cho KyongHo [mailto:[email protected]]
> >> Sent: Monday, July 29, 2013 4:20 PM
> >>
> >> > -----Original Message-----
> >> > From: Sachin Kamat [mailto:[email protected]]
> >> > Sent: Monday, July 29, 2013 3:38 PM
> >> >
> >> > Hi KyongHo,
> >> >
> >> > On 26 July 2013 16:58, Cho KyongHo <[email protected]> wrote:
> >> > > Signed-off-by: Cho KyongHo <[email protected]>
> >> > > ---
> >> > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> >> > > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> >> > > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> >> > > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> >> > > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> >> > > 5 files changed, 617 insertions(+), 0 deletions(-)
> >> > > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> >> >
> >> > This patch does not apply on the mainline Linus' tree (3.11-rc2). Please rebase.
> >> >
> >>
> >> OK. I will rebase the next patches on that.
> >
> > I don't get any conflict both on the latest of Linus's tree (3.11-rc3)
> > and for-next branch of Samsung git.
> > Can you show me the diff?
> >
>
> I get the following error when I do git am on this patch (linus' tree
> 3.11-rc3). Other patches apply fine.
>
> Applying: ARM: dts: Add description of System MMU of Exynos SoCs
> <local_path>/linux/.git/rebase-apply/patch:120: new blank line at EOF.
> +
> error: patch failed: arch/arm/boot/dts/exynos4.dtsi:161
> error: arch/arm/boot/dts/exynos4.dtsi: patch does not apply
> error: patch failed: arch/arm/boot/dts/exynos4210.dtsi:119
> error: arch/arm/boot/dts/exynos4210.dtsi: patch does not apply
> error: patch failed: arch/arm/boot/dts/exynos4x12.dtsi:79
> error: arch/arm/boot/dts/exynos4x12.dtsi: patch does not apply
> error: patch failed: arch/arm/boot/dts/exynos5250.dtsi:614
> error: arch/arm/boot/dts/exynos5250.dtsi: patch does not apply
> Patch failed at 0001 ARM: dts: Add description of System MMU of Exynos SoCs
> When you have resolved this problem run "git am --resolved".
> If you would prefer to skip this patch, instead run "git am --skip".
> To restore the original branch and stop patching run "git am --abort".
>
I wonder why you get the errors.
The error message shows the patch has extra blank line after the mark of EOF.
Or, maybe the patch I posted omitted some format information...
> --
> With warm regards,
> Sachin
Hi,
On Friday, July 26, 2013 08:28:19 PM Cho KyongHo wrote:
> Signed-off-by: Cho KyongHo <[email protected]>
> ---
> .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> 5 files changed, 617 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>
> diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> new file mode 100644
> index 0000000..92f0a33
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> @@ -0,0 +1,103 @@
> +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> +
> +Samsung's Exynos architecture contains System MMU that enables scattered
> +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> +
> +System MMU is a sort of IOMMU and support identical translation table format to
> +ARMv7 translation tables with minimum set of page properties including access
> +permissions, shareability and security protection. In addition, System MMU has
> +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> +latency.
> +
> +A System MMU is dedicated to a single master peripheral device. Thus, it is
> +important to specify the correct System MMU in the device node of its master
> +device. Whereas a System MMU is dedicated to a master device, the master device
> +may have more than one System MMU.
> +
> +Required properties:
> +- compatible: Should be "samsung,exynos4210-sysmmu"
> +- reg: A tuple of base address and size of System MMU registers.
> +- interrupt-parent: The phandle of the interrupt controller of System MMU
> +- interrupts: A tuple of numbers that indicates the interrupt source.
> +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> + Please refer to the following documents:
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> + Optional "master" if the clock to the System MMU is gated by
> + another gate clock other than "sysmmu". The System MMU driver
> + sets "master" the parent of "sysmmu".
> + Exynos4 SoCs, there needs no "master" clocks.
> + Exynos5 SoCs, some System MMUs must have "master" clocks.
> +- clocks: Required if the System MMU is needed to gate its clock.
> + Please refer to the documents listed above.
> +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> + Please refer to the following document:
> + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> +
> +Required properties for the master peripheral devices:
> +- iommu: phandles to the System MMUs of the device
> +
> +Examples:
> +A System MMU is dedicated to a single master device.
> + gsc_0: gsc@0x13e00000 {
> + compatible = "samsung,exynos5-gsc";
> + reg = <0x13e00000 0x1000>;
> + interrupts = <0 85 0>;
> + samsung,power-domain = <&pd_gsc>;
> + clocks = <&clock 256>;
> + clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> + };
> +
> + sysmmu_gsc0: sysmmu@13E80000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E80000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc0";
> + interrupts = <2 0>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 262>, <&clock 256>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> +to define 2 System MMUs for each port of the MFC:
Marek Szyprowski (added to cc:) has a patch fixing MFC to create separate
mfc_l and mfc_r devices (like it was in the past). Using this patch it
would be possible to bind sysmmu_mfc_l to mfc_l device and sysmmu_mfc_r to
mfc_r device. This probably also requires adding some MFC specific handling
in a device tree node and to the new master's device PM ops (in patch #10)
as previously (in our trees) sysmmu_mfc r device was set as parent of
sysmmu_mfc_l device which in turn was a parent for main MFC device (to make
runtime Power Management work). However because MFC is the only device
requiring use of multiple System MMUs above changes would allow us (unless
I'm missing something?) to use just one System MMU device per struct
exynos_iommu_client instance (making driver a lot simpler).
> + mfc: codec@13400000 {
> + compatible = "samsung,mfc-v5";
> + reg = <0x13400000 0x10000>;
> + interrupts = <0 94 0>;
> + samsung,power-domain = <&pd_mfc>;
> + clocks = <&clock 170>, <&clock 273>;
> + clock-names = "sclk_mfc", "mfc";
> + status = "ok";
> + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@13620000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13620000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-l";
> + interrupts = <5 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 274>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@13630000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13630000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-r";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 275>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> index 359694c..ba74ee8 100644
> --- a/arch/arm/boot/dts/exynos4.dtsi
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -161,6 +161,7 @@
> interrupts = <0 94 0>;
> samsung,power-domain = <&pd_mfc>;
> status = "disabled";
> + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> };
>
> serial@13800000 {
> @@ -395,5 +396,126 @@
> clock-names = "sclk_fimd", "fimd";
> samsung,power-domain = <&pd_lcd0>;
> status = "disabled";
> + iommu = <&sysmmu_fimd0>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@13620000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13620000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-l";
> + interrupts = <5 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 274>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@13630000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13630000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc-r";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 275>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_tv: sysmmu@13E20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-tv";
> + interrupts = <5 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 272>;
> + samsung,power-domain = <&pd_tv>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc0: sysmmu@11A20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc0";
> + interrupts = <4 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 263>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc1: sysmmu@11A30000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A30000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc1";
> + interrupts = <4 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 264>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc2: sysmmu@11A40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc2";
> + interrupts = <4 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 265>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc3: sysmmu@11A50000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A50000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc3";
> + interrupts = <4 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 266>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_jpeg: sysmmu@11A60000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11A60000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-jpeg";
> + interrupts = <4 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 267>;
> + samsung,power-domain = <&pd_cam>;
> + status = "ok";
> + };
> +
> + sysmmu_rotator: sysmmu@12A30000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12A30000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-rotator";
> + interrupts = <5 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 281>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd0: sysmmu@11E20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11E20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd0";
> + interrupts = <5 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 287>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> };
> };
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> index 54710de..09b13da 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -119,5 +119,30 @@
> reg = <0x12800000 0x1000>;
> interrupts = <0 89 0>;
> status = "disabled";
> + iommu = <&sysmmu_g2d>;
> + };
> +
> + sysmmu_g2d: sysmmu@12A20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12A20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-g2d";
> + interrupts = <4 7>;
> + clock-names = "sysmmu";
> + clocks = <&clock 280>;
> + samsung,power-domain = <&pd_lcd0>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd1: sysmmu@12220000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd1";
> + reg = <0x12220000 0x1000>;
> + interrupts = <5 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 291>;
> + samsung,power-domain = <&pd_lcd1>;
> + status = "ok";
> };
> };
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index e3380a7..681db32 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -79,4 +79,80 @@
> interrupts = <0 89 0>;
> status = "disabled";
> };
> +
> + sysmmu_g2d: sysmmu@10A40000{
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x10A40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-g2d";
> + interrupts = <4 7>;
> + clock-names = "sysmmu";
> + status = "ok";
> + };
> +
> + sysmmu_fimc_isp: sysmmu@12260000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12260000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_isp";
> + interrupts = <16 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 362>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_drc: sysmmu@12270000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x12270000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_drc";
> + interrupts = <16 3>;
> + clock-names = "sysmmu";
> + clocks = <&clock 363>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_fd: sysmmu@122A0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x122A0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_fd";
> + interrupts = <16 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 364>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_mcuctl: sysmmu@122B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x122B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_mcuctl";
> + interrupts = <16 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 376>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite0: sysmmu@123B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x123B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite0";
> + interrupts = <16 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 366>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite1: sysmmu@123C0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x123C0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite1";
> + interrupts = <16 1>;
> + clock-names = "sysmmu";
> + clocks = <&clock 365>;
> + status = "ok";
> + };
> };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index fc9fb3d..130d23d 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -66,6 +66,16 @@
> reg = <0x10044040 0x20>;
> };
>
> + pd_isp: mfc-power-domain@0x10044020 {
> + compatible = "samsung,exynos4210-pd";
> + reg = <0x10044020 0x20>;
> + };
> +
> + pd_disp1: mfc-power-domain@0x100440A0 {
> + compatible = "samsung,exynos4210-pd";
> + reg = <0x100440A0 0x20>;
> + };
> +
> clock: clock-controller@0x10010000 {
> compatible = "samsung,exynos5250-clock";
> reg = <0x10010000 0x30000>;
> @@ -180,6 +190,7 @@
> reg = <0x11000000 0x10000>;
> interrupts = <0 96 0>;
> samsung,power-domain = <&pd_mfc>;
> + iommu = <&sysmmu_mfc_l &sysmmu_mfc_l>;
Shouldn't it be:
iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
?
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> };
>
> rtc {
> @@ -571,6 +582,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 256>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> };
>
> gsc_1: gsc@0x13e10000 {
> @@ -580,6 +592,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 257>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc1>;
> };
>
> gsc_2: gsc@0x13e20000 {
> @@ -589,6 +602,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 258>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc2>;
> };
>
> gsc_3: gsc@0x13e30000 {
> @@ -598,6 +612,7 @@
> samsung,power-domain = <&pd_gsc>;
> clocks = <&clock 259>;
> clock-names = "gscl";
> + iommu = <&sysmmu_gsc3>;
> };
>
> hdmi {
> @@ -614,6 +629,7 @@
> compatible = "samsung,exynos5-mixer";
> reg = <0x14450000 0x10000>;
> interrupts = <0 94 0>;
> + iommu = <&sysmmu_tv>;
> };
>
> dp-controller {
> @@ -638,5 +654,280 @@
> interrupts = <18 4>, <18 5>, <18 6>;
> clocks = <&clock 133>, <&clock 339>;
> clock-names = "sclk_fimd", "fimd";
> + iommu = <&sysmmu_fimd1>;
> + };
> +
> + sysmmu_mfc_l: sysmmu@11210000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11210000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc_l";
> + interrupts = <8 5>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 267>, <&clock 266>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_mfc_r: sysmmu@11200000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11200000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-mfc_r";
> + interrupts = <6 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 268>, <&clock 266>;
> + samsung,power-domain = <&pd_mfc>;
> + status = "ok";
> + };
> +
> + sysmmu_tv: sysmmu@14650000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x14650000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-tv";
> + interrupts = <7 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 349>;
> + samsung,power-domain = <&pd_disp1>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc0: sysmmu@13E80000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E80000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc0";
> + interrupts = <2 0>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 262>, <&clock 256>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc1: sysmmu@13E90000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13E90000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc1";
> + interrupts = <2 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 263>, <&clock 257>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc2: sysmmu@13EA0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13EA0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc2";
> + interrupts = <2 4>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 264>, <&clock 258>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_gsc3: sysmmu@13EB0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13EB0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-gsc3";
> + interrupts = <2 6>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 265>, <&clock 259>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimd1: sysmmu@14640000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x14640000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimd1";
> + interrupts = <3 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 350>;
> + samsung,power-domain = <&pd_disp1>;
> + status = "ok";
> + };
> +
> + sysmmu_rotator: sysmmu@11D40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11D40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-rotator";
> + interrupts = <4 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 272>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_isp: sysmmu@13260000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13260000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_isp";
> + interrupts = <10 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 361>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_drc: sysmmu@13270000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13270000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_drc";
> + interrupts = <11 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 362>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_fd: sysmmu@132A0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132A0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_fd";
> + interrupts = <5 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 363>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_scc: sysmmu@13280000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13280000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_scalerc";
> + interrupts = <5 2>;
> + clock-names = "sysmmu";
> + clocks = <&clock 364>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_scp: sysmmu@13290000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13290000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_scalerp";
> + interrupts = <3 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 365>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_mcuctl: sysmmu@132B0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132B0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_mcuctl";
> + interrupts = <5 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 366>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_odc: sysmmu@132C0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132C0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_odc";
> + interrupts = <11 0>;
> + clock-names = "sysmmu";
> + clocks = <&clock 367>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_dis0: sysmmu@132D0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132D0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_dis0";
> + interrupts = <10 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 368>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_dis1: sysmmu@132E0000{
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132E0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_dis1";
> + interrupts = <9 4>;
> + clock-names = "sysmmu";
> + clocks = <&clock 369>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_3dnr: sysmmu@132F0000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x132F0000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_3dnr";
> + interrupts = <5 6>;
> + clock-names = "sysmmu";
> + clocks = <&clock 370>;
> + samsung,power-domain = <&pd_isp>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite0: sysmmu@13C40000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13C40000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite0";
> + interrupts = <3 4>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 346>, <&clock 345>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_lite1: sysmmu@13C50000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x13C50000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-fimc_lite1";
> + interrupts = <24 1>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 347>, <&clock 345>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_jpeg: sysmmu@11F20000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x11F20000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-jpeg";
> + interrupts = <4 2>;
> + clock-names = "sysmmu", "master";
> + clocks = <&clock 273>, <&clock 270>;
> + samsung,power-domain = <&pd_gsc>;
> + status = "ok";
> + };
> +
> + sysmmu_fimc_2d: sysmmu@10A60000 {
> + compatible = "samsung,exynos4210-sysmmu";
> + reg = <0x10A60000 0x1000>;
> + interrupt-parent = <&combiner>;
> + interrupt-names = "sysmmu-2d";
> + interrupts = <24 5>;
> + clock-names = "sysmmu";
> + clocks = <&clock 361>;
> + status = "ok";
> };
> };
> -----Original Message-----
> From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
> Sent: Saturday, August 03, 2013 2:14 AM
>
> Hi,
>
> On Friday, July 26, 2013 08:28:19 PM Cho KyongHo wrote:
> > Signed-off-by: Cho KyongHo <[email protected]>
> > ---
> > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > 5 files changed, 617 insertions(+), 0 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > new file mode 100644
> > index 0000000..92f0a33
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > @@ -0,0 +1,103 @@
> > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > +
> > +Samsung's Exynos architecture contains System MMU that enables scattered
> > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > +
> > +System MMU is a sort of IOMMU and support identical translation table format to
> > +ARMv7 translation tables with minimum set of page properties including access
> > +permissions, shareability and security protection. In addition, System MMU has
> > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > +latency.
> > +
> > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > +important to specify the correct System MMU in the device node of its master
> > +device. Whereas a System MMU is dedicated to a master device, the master device
> > +may have more than one System MMU.
> > +
> > +Required properties:
> > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > +- reg: A tuple of base address and size of System MMU registers.
> > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > + Please refer to the following documents:
> > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > + Optional "master" if the clock to the System MMU is gated by
> > + another gate clock other than "sysmmu". The System MMU driver
> > + sets "master" the parent of "sysmmu".
> > + Exynos4 SoCs, there needs no "master" clocks.
> > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > +- clocks: Required if the System MMU is needed to gate its clock.
> > + Please refer to the documents listed above.
> > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > + Please refer to the following document:
> > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > +
> > +Required properties for the master peripheral devices:
> > +- iommu: phandles to the System MMUs of the device
> > +
> > +Examples:
> > +A System MMU is dedicated to a single master device.
> > + gsc_0: gsc@0x13e00000 {
> > + compatible = "samsung,exynos5-gsc";
> > + reg = <0x13e00000 0x1000>;
> > + interrupts = <0 85 0>;
> > + samsung,power-domain = <&pd_gsc>;
> > + clocks = <&clock 256>;
> > + clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > + };
> > +
> > + sysmmu_gsc0: sysmmu@13E80000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E80000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc0";
> > + interrupts = <2 0>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 262>, <&clock 256>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> > +to define 2 System MMUs for each port of the MFC:
>
> Marek Szyprowski (added to cc:) has a patch fixing MFC to create separate
> mfc_l and mfc_r devices (like it was in the past). Using this patch it
> would be possible to bind sysmmu_mfc_l to mfc_l device and sysmmu_mfc_r to
> mfc_r device. This probably also requires adding some MFC specific handling
> in a device tree node and to the new master's device PM ops (in patch #10)
> as previously (in our trees) sysmmu_mfc r device was set as parent of
> sysmmu_mfc_l device which in turn was a parent for main MFC device (to make
> runtime Power Management work). However because MFC is the only device
> requiring use of multiple System MMUs above changes would allow us (unless
> I'm missing something?) to use just one System MMU device per struct
> exynos_iommu_client instance (making driver a lot simpler).
>
Does it mean that we can make the exynos-iommu driver simpler
with Marek Szyprowski's patch?
It is welcome but I don't think it covers all topologies of System MMU and
master H/W. Those are getting more complex.
> > + mfc: codec@13400000 {
> > + compatible = "samsung,mfc-v5";
> > + reg = <0x13400000 0x10000>;
> > + interrupts = <0 94 0>;
> > + samsung,power-domain = <&pd_mfc>;
> > + clocks = <&clock 170>, <&clock 273>;
> > + clock-names = "sclk_mfc", "mfc";
> > + status = "ok";
> > + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@13620000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13620000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-l";
> > + interrupts = <5 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 274>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@13630000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13630000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-r";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 275>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> > index 359694c..ba74ee8 100644
> > --- a/arch/arm/boot/dts/exynos4.dtsi
> > +++ b/arch/arm/boot/dts/exynos4.dtsi
> > @@ -161,6 +161,7 @@
> > interrupts = <0 94 0>;
> > samsung,power-domain = <&pd_mfc>;
> > status = "disabled";
> > + iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> > };
> >
> > serial@13800000 {
> > @@ -395,5 +396,126 @@
> > clock-names = "sclk_fimd", "fimd";
> > samsung,power-domain = <&pd_lcd0>;
> > status = "disabled";
> > + iommu = <&sysmmu_fimd0>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@13620000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13620000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-l";
> > + interrupts = <5 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 274>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@13630000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13630000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc-r";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 275>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_tv: sysmmu@13E20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-tv";
> > + interrupts = <5 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 272>;
> > + samsung,power-domain = <&pd_tv>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc0: sysmmu@11A20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc0";
> > + interrupts = <4 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 263>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc1: sysmmu@11A30000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A30000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc1";
> > + interrupts = <4 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 264>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc2: sysmmu@11A40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc2";
> > + interrupts = <4 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 265>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc3: sysmmu@11A50000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A50000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc3";
> > + interrupts = <4 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 266>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_jpeg: sysmmu@11A60000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11A60000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-jpeg";
> > + interrupts = <4 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 267>;
> > + samsung,power-domain = <&pd_cam>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_rotator: sysmmu@12A30000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12A30000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-rotator";
> > + interrupts = <5 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 281>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd0: sysmmu@11E20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11E20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd0";
> > + interrupts = <5 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 287>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> > index 54710de..09b13da 100644
> > --- a/arch/arm/boot/dts/exynos4210.dtsi
> > +++ b/arch/arm/boot/dts/exynos4210.dtsi
> > @@ -119,5 +119,30 @@
> > reg = <0x12800000 0x1000>;
> > interrupts = <0 89 0>;
> > status = "disabled";
> > + iommu = <&sysmmu_g2d>;
> > + };
> > +
> > + sysmmu_g2d: sysmmu@12A20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12A20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-g2d";
> > + interrupts = <4 7>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 280>;
> > + samsung,power-domain = <&pd_lcd0>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd1: sysmmu@12220000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd1";
> > + reg = <0x12220000 0x1000>;
> > + interrupts = <5 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 291>;
> > + samsung,power-domain = <&pd_lcd1>;
> > + status = "ok";
> > };
> > };
> > diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> > index e3380a7..681db32 100644
> > --- a/arch/arm/boot/dts/exynos4x12.dtsi
> > +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> > @@ -79,4 +79,80 @@
> > interrupts = <0 89 0>;
> > status = "disabled";
> > };
> > +
> > + sysmmu_g2d: sysmmu@10A40000{
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x10A40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-g2d";
> > + interrupts = <4 7>;
> > + clock-names = "sysmmu";
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_isp: sysmmu@12260000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12260000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_isp";
> > + interrupts = <16 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 362>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_drc: sysmmu@12270000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x12270000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_drc";
> > + interrupts = <16 3>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 363>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_fd: sysmmu@122A0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x122A0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_fd";
> > + interrupts = <16 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 364>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_mcuctl: sysmmu@122B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x122B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_mcuctl";
> > + interrupts = <16 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 376>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite0: sysmmu@123B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x123B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite0";
> > + interrupts = <16 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 366>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite1: sysmmu@123C0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x123C0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite1";
> > + interrupts = <16 1>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 365>;
> > + status = "ok";
> > + };
> > };
> > diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> > index fc9fb3d..130d23d 100644
> > --- a/arch/arm/boot/dts/exynos5250.dtsi
> > +++ b/arch/arm/boot/dts/exynos5250.dtsi
> > @@ -66,6 +66,16 @@
> > reg = <0x10044040 0x20>;
> > };
> >
> > + pd_isp: mfc-power-domain@0x10044020 {
> > + compatible = "samsung,exynos4210-pd";
> > + reg = <0x10044020 0x20>;
> > + };
> > +
> > + pd_disp1: mfc-power-domain@0x100440A0 {
> > + compatible = "samsung,exynos4210-pd";
> > + reg = <0x100440A0 0x20>;
> > + };
> > +
> > clock: clock-controller@0x10010000 {
> > compatible = "samsung,exynos5250-clock";
> > reg = <0x10010000 0x30000>;
> > @@ -180,6 +190,7 @@
> > reg = <0x11000000 0x10000>;
> > interrupts = <0 96 0>;
> > samsung,power-domain = <&pd_mfc>;
> > + iommu = <&sysmmu_mfc_l &sysmmu_mfc_l>;
>
> Shouldn't it be:
>
> iommu = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
>
> ?
Oh. yes you are right.
Thanks.
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
> > };
> >
> > rtc {
> > @@ -571,6 +582,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 256>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > };
> >
> > gsc_1: gsc@0x13e10000 {
> > @@ -580,6 +592,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 257>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc1>;
> > };
> >
> > gsc_2: gsc@0x13e20000 {
> > @@ -589,6 +602,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 258>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc2>;
> > };
> >
> > gsc_3: gsc@0x13e30000 {
> > @@ -598,6 +612,7 @@
> > samsung,power-domain = <&pd_gsc>;
> > clocks = <&clock 259>;
> > clock-names = "gscl";
> > + iommu = <&sysmmu_gsc3>;
> > };
> >
> > hdmi {
> > @@ -614,6 +629,7 @@
> > compatible = "samsung,exynos5-mixer";
> > reg = <0x14450000 0x10000>;
> > interrupts = <0 94 0>;
> > + iommu = <&sysmmu_tv>;
> > };
> >
> > dp-controller {
> > @@ -638,5 +654,280 @@
> > interrupts = <18 4>, <18 5>, <18 6>;
> > clocks = <&clock 133>, <&clock 339>;
> > clock-names = "sclk_fimd", "fimd";
> > + iommu = <&sysmmu_fimd1>;
> > + };
> > +
> > + sysmmu_mfc_l: sysmmu@11210000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11210000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc_l";
> > + interrupts = <8 5>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 267>, <&clock 266>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_mfc_r: sysmmu@11200000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11200000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-mfc_r";
> > + interrupts = <6 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 268>, <&clock 266>;
> > + samsung,power-domain = <&pd_mfc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_tv: sysmmu@14650000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x14650000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-tv";
> > + interrupts = <7 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 349>;
> > + samsung,power-domain = <&pd_disp1>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc0: sysmmu@13E80000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E80000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc0";
> > + interrupts = <2 0>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 262>, <&clock 256>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc1: sysmmu@13E90000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13E90000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc1";
> > + interrupts = <2 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 263>, <&clock 257>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc2: sysmmu@13EA0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13EA0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc2";
> > + interrupts = <2 4>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 264>, <&clock 258>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_gsc3: sysmmu@13EB0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13EB0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-gsc3";
> > + interrupts = <2 6>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 265>, <&clock 259>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimd1: sysmmu@14640000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x14640000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimd1";
> > + interrupts = <3 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 350>;
> > + samsung,power-domain = <&pd_disp1>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_rotator: sysmmu@11D40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11D40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-rotator";
> > + interrupts = <4 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 272>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_isp: sysmmu@13260000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13260000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_isp";
> > + interrupts = <10 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 361>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_drc: sysmmu@13270000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13270000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_drc";
> > + interrupts = <11 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 362>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_fd: sysmmu@132A0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132A0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_fd";
> > + interrupts = <5 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 363>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_scc: sysmmu@13280000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13280000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_scalerc";
> > + interrupts = <5 2>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 364>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_scp: sysmmu@13290000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13290000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_scalerp";
> > + interrupts = <3 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 365>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_mcuctl: sysmmu@132B0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132B0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_mcuctl";
> > + interrupts = <5 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 366>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_odc: sysmmu@132C0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132C0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_odc";
> > + interrupts = <11 0>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 367>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_dis0: sysmmu@132D0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132D0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_dis0";
> > + interrupts = <10 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 368>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_dis1: sysmmu@132E0000{
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132E0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_dis1";
> > + interrupts = <9 4>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 369>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_3dnr: sysmmu@132F0000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x132F0000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_3dnr";
> > + interrupts = <5 6>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 370>;
> > + samsung,power-domain = <&pd_isp>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite0: sysmmu@13C40000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13C40000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite0";
> > + interrupts = <3 4>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 346>, <&clock 345>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_lite1: sysmmu@13C50000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x13C50000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-fimc_lite1";
> > + interrupts = <24 1>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 347>, <&clock 345>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_jpeg: sysmmu@11F20000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x11F20000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-jpeg";
> > + interrupts = <4 2>;
> > + clock-names = "sysmmu", "master";
> > + clocks = <&clock 273>, <&clock 270>;
> > + samsung,power-domain = <&pd_gsc>;
> > + status = "ok";
> > + };
> > +
> > + sysmmu_fimc_2d: sysmmu@10A60000 {
> > + compatible = "samsung,exynos4210-sysmmu";
> > + reg = <0x10A60000 0x1000>;
> > + interrupt-parent = <&combiner>;
> > + interrupt-names = "sysmmu-2d";
> > + interrupts = <24 5>;
> > + clock-names = "sysmmu";
> > + clocks = <&clock 361>;
> > + status = "ok";
> > };
> > };
On Monday, August 05, 2013 08:16:40 PM Cho KyongHo wrote:
> > -----Original Message-----
> > From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
> > Sent: Saturday, August 03, 2013 2:14 AM
> >
> > Hi,
> >
> > On Friday, July 26, 2013 08:28:19 PM Cho KyongHo wrote:
> > > Signed-off-by: Cho KyongHo <[email protected]>
> > > ---
> > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > > 5 files changed, 617 insertions(+), 0 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > new file mode 100644
> > > index 0000000..92f0a33
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > @@ -0,0 +1,103 @@
> > > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > > +
> > > +Samsung's Exynos architecture contains System MMU that enables scattered
> > > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > > +
> > > +System MMU is a sort of IOMMU and support identical translation table format to
> > > +ARMv7 translation tables with minimum set of page properties including access
> > > +permissions, shareability and security protection. In addition, System MMU has
> > > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > > +latency.
> > > +
> > > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > > +important to specify the correct System MMU in the device node of its master
> > > +device. Whereas a System MMU is dedicated to a master device, the master device
> > > +may have more than one System MMU.
> > > +
> > > +Required properties:
> > > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > > +- reg: A tuple of base address and size of System MMU registers.
> > > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > > + Please refer to the following documents:
> > > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > > + Optional "master" if the clock to the System MMU is gated by
> > > + another gate clock other than "sysmmu". The System MMU driver
> > > + sets "master" the parent of "sysmmu".
> > > + Exynos4 SoCs, there needs no "master" clocks.
> > > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > > +- clocks: Required if the System MMU is needed to gate its clock.
> > > + Please refer to the documents listed above.
> > > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > > + Please refer to the following document:
> > > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > > +
> > > +Required properties for the master peripheral devices:
> > > +- iommu: phandles to the System MMUs of the device
> > > +
> > > +Examples:
> > > +A System MMU is dedicated to a single master device.
> > > + gsc_0: gsc@0x13e00000 {
> > > + compatible = "samsung,exynos5-gsc";
> > > + reg = <0x13e00000 0x1000>;
> > > + interrupts = <0 85 0>;
> > > + samsung,power-domain = <&pd_gsc>;
> > > + clocks = <&clock 256>;
> > > + clock-names = "gscl";
> > > + iommu = <&sysmmu_gsc1>;
> > > + };
> > > +
> > > + sysmmu_gsc0: sysmmu@13E80000 {
> > > + compatible = "samsung,exynos4210-sysmmu";
> > > + reg = <0x13E80000 0x1000>;
> > > + interrupt-parent = <&combiner>;
> > > + interrupt-names = "sysmmu-gsc0";
> > > + interrupts = <2 0>;
> > > + clock-names = "sysmmu", "master";
> > > + clocks = <&clock 262>, <&clock 256>;
> > > + samsung,power-domain = <&pd_gsc>;
> > > + status = "ok";
> > > + };
> > > +
> > > +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> > > +to define 2 System MMUs for each port of the MFC:
> >
> > Marek Szyprowski (added to cc:) has a patch fixing MFC to create separate
> > mfc_l and mfc_r devices (like it was in the past). Using this patch it
> > would be possible to bind sysmmu_mfc_l to mfc_l device and sysmmu_mfc_r to
> > mfc_r device. This probably also requires adding some MFC specific handling
> > in a device tree node and to the new master's device PM ops (in patch #10)
> > as previously (in our trees) sysmmu_mfc r device was set as parent of
> > sysmmu_mfc_l device which in turn was a parent for main MFC device (to make
> > runtime Power Management work). However because MFC is the only device
> > requiring use of multiple System MMUs above changes would allow us (unless
> > I'm missing something?) to use just one System MMU device per struct
> > exynos_iommu_client instance (making driver a lot simpler).
> >
>
> Does it mean that we can make the exynos-iommu driver simpler
> with Marek Szyprowski's patch?
I think so and you probably need to change MFC handling anyway because
MFC driver does DMA allocations per mfc_l/mfc_r devices and not per main
device (at least in the upstream kernels).
[ Marek, could you please resfresh and post your patch on the list? ]
BTW There is an additional problem with combining System MMU devices per
one main device - it limits available address space (which in case of MFC
is very limited by hardware design).
> It is welcome but I don't think it covers all topologies of System MMU and
> master H/W. Those are getting more complex.
Could you please be more specific? I know about FIMC ISP subsystem but
it doesn't require combining System MMUs. Are there any other examples of
complex System MMU + master H/W topologies?
Anyway I think that System MMUs should not be combined (as it is done in
patch #10) and should be binded per "memport" devices and not per main
device (as done in this patch).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Hello,
On 8/5/2013 3:09 PM, Bartlomiej Zolnierkiewicz wrote:
> On Monday, August 05, 2013 08:16:40 PM Cho KyongHo wrote:
> > > -----Original Message-----
> > > From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
> > > Sent: Saturday, August 03, 2013 2:14 AM
> > >
> > > Hi,
> > >
> > > On Friday, July 26, 2013 08:28:19 PM Cho KyongHo wrote:
> > > > Signed-off-by: Cho KyongHo <[email protected]>
> > > > ---
> > > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > > > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > > > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > > > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > > > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > > > 5 files changed, 617 insertions(+), 0 deletions(-)
> > > > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > new file mode 100644
> > > > index 0000000..92f0a33
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > @@ -0,0 +1,103 @@
> > > > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > > > +
> > > > +Samsung's Exynos architecture contains System MMU that enables scattered
> > > > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > > > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > > > +
> > > > +System MMU is a sort of IOMMU and support identical translation table format to
> > > > +ARMv7 translation tables with minimum set of page properties including access
> > > > +permissions, shareability and security protection. In addition, System MMU has
> > > > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > > > +latency.
> > > > +
> > > > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > > > +important to specify the correct System MMU in the device node of its master
> > > > +device. Whereas a System MMU is dedicated to a master device, the master device
> > > > +may have more than one System MMU.
> > > > +
> > > > +Required properties:
> > > > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > > > +- reg: A tuple of base address and size of System MMU registers.
> > > > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > > > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > > > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > > > + Please refer to the following documents:
> > > > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > > > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > > > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > > > + Optional "master" if the clock to the System MMU is gated by
> > > > + another gate clock other than "sysmmu". The System MMU driver
> > > > + sets "master" the parent of "sysmmu".
> > > > + Exynos4 SoCs, there needs no "master" clocks.
> > > > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > > > +- clocks: Required if the System MMU is needed to gate its clock.
> > > > + Please refer to the documents listed above.
> > > > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > > > + Please refer to the following document:
> > > > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > > > +
> > > > +Required properties for the master peripheral devices:
> > > > +- iommu: phandles to the System MMUs of the device
> > > > +
> > > > +Examples:
> > > > +A System MMU is dedicated to a single master device.
> > > > + gsc_0: gsc@0x13e00000 {
> > > > + compatible = "samsung,exynos5-gsc";
> > > > + reg = <0x13e00000 0x1000>;
> > > > + interrupts = <0 85 0>;
> > > > + samsung,power-domain = <&pd_gsc>;
> > > > + clocks = <&clock 256>;
> > > > + clock-names = "gscl";
> > > > + iommu = <&sysmmu_gsc1>;
> > > > + };
> > > > +
> > > > + sysmmu_gsc0: sysmmu@13E80000 {
> > > > + compatible = "samsung,exynos4210-sysmmu";
> > > > + reg = <0x13E80000 0x1000>;
> > > > + interrupt-parent = <&combiner>;
> > > > + interrupt-names = "sysmmu-gsc0";
> > > > + interrupts = <2 0>;
> > > > + clock-names = "sysmmu", "master";
> > > > + clocks = <&clock 262>, <&clock 256>;
> > > > + samsung,power-domain = <&pd_gsc>;
> > > > + status = "ok";
> > > > + };
> > > > +
> > > > +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> > > > +to define 2 System MMUs for each port of the MFC:
> > >
> > > Marek Szyprowski (added to cc:) has a patch fixing MFC to create separate
> > > mfc_l and mfc_r devices (like it was in the past). Using this patch it
> > > would be possible to bind sysmmu_mfc_l to mfc_l device and sysmmu_mfc_r to
> > > mfc_r device. This probably also requires adding some MFC specific handling
> > > in a device tree node and to the new master's device PM ops (in patch #10)
> > > as previously (in our trees) sysmmu_mfc r device was set as parent of
> > > sysmmu_mfc_l device which in turn was a parent for main MFC device (to make
> > > runtime Power Management work). However because MFC is the only device
> > > requiring use of multiple System MMUs above changes would allow us (unless
> > > I'm missing something?) to use just one System MMU device per struct
> > > exynos_iommu_client instance (making driver a lot simpler).
> > >
> >
> > Does it mean that we can make the exynos-iommu driver simpler
> > with Marek Szyprowski's patch?
>
> I think so and you probably need to change MFC handling anyway because
> MFC driver does DMA allocations per mfc_l/mfc_r devices and not per main
> device (at least in the upstream kernels).
>
> [ Marek, could you please resfresh and post your patch on the list? ]
My proposal for cleaning up MFC's bindings is available here:
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/21536/
> BTW There is an additional problem with combining System MMU devices per
> one main device - it limits available address space (which in case of MFC
> is very limited by hardware design).
>
> > It is welcome but I don't think it covers all topologies of System MMU and
> > master H/W. Those are getting more complex.
>
> Could you please be more specific? I know about FIMC ISP subsystem but
> it doesn't require combining System MMUs. Are there any other examples of
> complex System MMU + master H/W topologies?
>
> Anyway I think that System MMUs should not be combined (as it is done in
> patch #10) and should be binded per "memport" devices and not per main
> device (as done in this patch).
Best regards
--
Marek Szyprowski
Samsung R&D Institute Poland
> -----Original Message-----
> From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
> Sent: Monday, August 05, 2013 10:10 PM
>
> On Monday, August 05, 2013 08:16:40 PM Cho KyongHo wrote:
> > > -----Original Message-----
> > > From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
> > > Sent: Saturday, August 03, 2013 2:14 AM
> > >
> > > Hi,
> > >
> > > On Friday, July 26, 2013 08:28:19 PM Cho KyongHo wrote:
> > > > Signed-off-by: Cho KyongHo <[email protected]>
> > > > ---
> > > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > > > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > > > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > > > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > > > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > > > 5 files changed, 617 insertions(+), 0 deletions(-)
> > > > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > new file mode 100644
> > > > index 0000000..92f0a33
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > @@ -0,0 +1,103 @@
> > > > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > > > +
> > > > +Samsung's Exynos architecture contains System MMU that enables scattered
> > > > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > > > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > > > +
> > > > +System MMU is a sort of IOMMU and support identical translation table format to
> > > > +ARMv7 translation tables with minimum set of page properties including access
> > > > +permissions, shareability and security protection. In addition, System MMU has
> > > > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > > > +latency.
> > > > +
> > > > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > > > +important to specify the correct System MMU in the device node of its master
> > > > +device. Whereas a System MMU is dedicated to a master device, the master device
> > > > +may have more than one System MMU.
> > > > +
> > > > +Required properties:
> > > > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > > > +- reg: A tuple of base address and size of System MMU registers.
> > > > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > > > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > > > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > > > + Please refer to the following documents:
> > > > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > > > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > > > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > > > + Optional "master" if the clock to the System MMU is gated by
> > > > + another gate clock other than "sysmmu". The System MMU driver
> > > > + sets "master" the parent of "sysmmu".
> > > > + Exynos4 SoCs, there needs no "master" clocks.
> > > > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > > > +- clocks: Required if the System MMU is needed to gate its clock.
> > > > + Please refer to the documents listed above.
> > > > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > > > + Please refer to the following document:
> > > > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > > > +
> > > > +Required properties for the master peripheral devices:
> > > > +- iommu: phandles to the System MMUs of the device
> > > > +
> > > > +Examples:
> > > > +A System MMU is dedicated to a single master device.
> > > > + gsc_0: gsc@0x13e00000 {
> > > > + compatible = "samsung,exynos5-gsc";
> > > > + reg = <0x13e00000 0x1000>;
> > > > + interrupts = <0 85 0>;
> > > > + samsung,power-domain = <&pd_gsc>;
> > > > + clocks = <&clock 256>;
> > > > + clock-names = "gscl";
> > > > + iommu = <&sysmmu_gsc1>;
> > > > + };
> > > > +
> > > > + sysmmu_gsc0: sysmmu@13E80000 {
> > > > + compatible = "samsung,exynos4210-sysmmu";
> > > > + reg = <0x13E80000 0x1000>;
> > > > + interrupt-parent = <&combiner>;
> > > > + interrupt-names = "sysmmu-gsc0";
> > > > + interrupts = <2 0>;
> > > > + clock-names = "sysmmu", "master";
> > > > + clocks = <&clock 262>, <&clock 256>;
> > > > + samsung,power-domain = <&pd_gsc>;
> > > > + status = "ok";
> > > > + };
> > > > +
> > > > +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> > > > +to define 2 System MMUs for each port of the MFC:
> > >
> > > Marek Szyprowski (added to cc:) has a patch fixing MFC to create separate
> > > mfc_l and mfc_r devices (like it was in the past). Using this patch it
> > > would be possible to bind sysmmu_mfc_l to mfc_l device and sysmmu_mfc_r to
> > > mfc_r device. This probably also requires adding some MFC specific handling
> > > in a device tree node and to the new master's device PM ops (in patch #10)
> > > as previously (in our trees) sysmmu_mfc r device was set as parent of
> > > sysmmu_mfc_l device which in turn was a parent for main MFC device (to make
> > > runtime Power Management work). However because MFC is the only device
> > > requiring use of multiple System MMUs above changes would allow us (unless
> > > I'm missing something?) to use just one System MMU device per struct
> > > exynos_iommu_client instance (making driver a lot simpler).
> > >
> >
> > Does it mean that we can make the exynos-iommu driver simpler
> > with Marek Szyprowski's patch?
>
> I think so and you probably need to change MFC handling anyway because
> MFC driver does DMA allocations per mfc_l/mfc_r devices and not per main
> device (at least in the upstream kernels).
>
> [ Marek, could you please resfresh and post your patch on the list? ]
>
> BTW There is an additional problem with combining System MMU devices per
> one main device - it limits available address space (which in case of MFC
> is very limited by hardware design).
>
> > It is welcome but I don't think it covers all topologies of System MMU and
> > master H/W. Those are getting more complex.
>
> Could you please be more specific? I know about FIMC ISP subsystem but
> it doesn't require combining System MMUs. Are there any other examples of
> complex System MMU + master H/W topologies?
I meant a lot of System MMUs in FIMC-IS subsystem.
A big challenge to System MMU configuration is FIMC-IS as you mentioned.
Since I don't know how the driver of FIMC-IS controls its H/W,
I made the System MMU driver to configure System MMUs flexibly.
>
> Anyway I think that System MMUs should not be combined (as it is done in
> patch #10) and should be binded per "memport" devices and not per main
> device (as done in this patch).
>
Ok.
I will make it them as you advised.
And we can make the driver better gradually.
Thank you.
KyongHo.
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
Hello,
On 8/6/2013 11:54 AM, Cho KyongHo wrote:
> > -----Original Message-----
> > From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
> > Sent: Monday, August 05, 2013 10:10 PM
> >
> > On Monday, August 05, 2013 08:16:40 PM Cho KyongHo wrote:
> > > > -----Original Message-----
> > > > From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
> > > > Sent: Saturday, August 03, 2013 2:14 AM
> > > >
> > > > Hi,
> > > >
> > > > On Friday, July 26, 2013 08:28:19 PM Cho KyongHo wrote:
> > > > > Signed-off-by: Cho KyongHo <[email protected]>
> > > > > ---
> > > > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > > > > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > > > > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > > > > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > > > > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > > > > 5 files changed, 617 insertions(+), 0 deletions(-)
> > > > > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > > new file mode 100644
> > > > > index 0000000..92f0a33
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > > > > @@ -0,0 +1,103 @@
> > > > > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > > > > +
> > > > > +Samsung's Exynos architecture contains System MMU that enables scattered
> > > > > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > > > > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > > > > +
> > > > > +System MMU is a sort of IOMMU and support identical translation table format to
> > > > > +ARMv7 translation tables with minimum set of page properties including access
> > > > > +permissions, shareability and security protection. In addition, System MMU has
> > > > > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > > > > +latency.
> > > > > +
> > > > > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > > > > +important to specify the correct System MMU in the device node of its master
> > > > > +device. Whereas a System MMU is dedicated to a master device, the master device
> > > > > +may have more than one System MMU.
> > > > > +
> > > > > +Required properties:
> > > > > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > > > > +- reg: A tuple of base address and size of System MMU registers.
> > > > > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > > > > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > > > > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > > > > + Please refer to the following documents:
> > > > > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > > > > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > > > > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > > > > + Optional "master" if the clock to the System MMU is gated by
> > > > > + another gate clock other than "sysmmu". The System MMU driver
> > > > > + sets "master" the parent of "sysmmu".
> > > > > + Exynos4 SoCs, there needs no "master" clocks.
> > > > > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > > > > +- clocks: Required if the System MMU is needed to gate its clock.
> > > > > + Please refer to the documents listed above.
> > > > > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > > > > + Please refer to the following document:
> > > > > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > > > > +
> > > > > +Required properties for the master peripheral devices:
> > > > > +- iommu: phandles to the System MMUs of the device
> > > > > +
> > > > > +Examples:
> > > > > +A System MMU is dedicated to a single master device.
> > > > > + gsc_0: gsc@0x13e00000 {
> > > > > + compatible = "samsung,exynos5-gsc";
> > > > > + reg = <0x13e00000 0x1000>;
> > > > > + interrupts = <0 85 0>;
> > > > > + samsung,power-domain = <&pd_gsc>;
> > > > > + clocks = <&clock 256>;
> > > > > + clock-names = "gscl";
> > > > > + iommu = <&sysmmu_gsc1>;
> > > > > + };
> > > > > +
> > > > > + sysmmu_gsc0: sysmmu@13E80000 {
> > > > > + compatible = "samsung,exynos4210-sysmmu";
> > > > > + reg = <0x13E80000 0x1000>;
> > > > > + interrupt-parent = <&combiner>;
> > > > > + interrupt-names = "sysmmu-gsc0";
> > > > > + interrupts = <2 0>;
> > > > > + clock-names = "sysmmu", "master";
> > > > > + clocks = <&clock 262>, <&clock 256>;
> > > > > + samsung,power-domain = <&pd_gsc>;
> > > > > + status = "ok";
> > > > > + };
> > > > > +
> > > > > +MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
> > > > > +to define 2 System MMUs for each port of the MFC:
> > > >
> > > > Marek Szyprowski (added to cc:) has a patch fixing MFC to create separate
> > > > mfc_l and mfc_r devices (like it was in the past). Using this patch it
> > > > would be possible to bind sysmmu_mfc_l to mfc_l device and sysmmu_mfc_r to
> > > > mfc_r device. This probably also requires adding some MFC specific handling
> > > > in a device tree node and to the new master's device PM ops (in patch #10)
> > > > as previously (in our trees) sysmmu_mfc r device was set as parent of
> > > > sysmmu_mfc_l device which in turn was a parent for main MFC device (to make
> > > > runtime Power Management work). However because MFC is the only device
> > > > requiring use of multiple System MMUs above changes would allow us (unless
> > > > I'm missing something?) to use just one System MMU device per struct
> > > > exynos_iommu_client instance (making driver a lot simpler).
> > > >
> > >
> > > Does it mean that we can make the exynos-iommu driver simpler
> > > with Marek Szyprowski's patch?
> >
> > I think so and you probably need to change MFC handling anyway because
> > MFC driver does DMA allocations per mfc_l/mfc_r devices and not per main
> > device (at least in the upstream kernels).
> >
> > [ Marek, could you please resfresh and post your patch on the list? ]
> >
> > BTW There is an additional problem with combining System MMU devices per
> > one main device - it limits available address space (which in case of MFC
> > is very limited by hardware design).
> >
> > > It is welcome but I don't think it covers all topologies of System MMU and
> > > master H/W. Those are getting more complex.
> >
> > Could you please be more specific? I know about FIMC ISP subsystem but
> > it doesn't require combining System MMUs. Are there any other examples of
> > complex System MMU + master H/W topologies?
>
> I meant a lot of System MMUs in FIMC-IS subsystem.
> A big challenge to System MMU configuration is FIMC-IS as you mentioned.
> Since I don't know how the driver of FIMC-IS controls its H/W,
> I made the System MMU driver to configure System MMUs flexibly.
Don't think that combining the IOMMU controllers together made them
flexible.
I only see it as overengineering of the complex FIMC-IS and MFC devices
topology.
IMHO it is much better to have a simple driver, which binds to a single
IOMMU
controller and leave it to the driver whether to have a same virtual address
space for all parts of FIMC-IS or MFC submodules/memory ports or not.
Just make
sure that it will be possible to attach more than one sysmmu controller
to one
iommu domain.
With some fixes and additional initialization code I have finally
managed to
get Your driver working with FIMC & memport-based MFC together with
iommu based
dma-mapping on Exynos4210. I will post my patches after you post Your
updated
version.
> > Anyway I think that System MMUs should not be combined (as it is done in
> > patch #10) and should be binded per "memport" devices and not per main
> > device (as done in this patch).
> >
>
> Ok.
> I will make it them as you advised.
> And we can make the driver better gradually.
Best regards
--
Marek Szyprowski
Samsung R&D Institute Poland
Hi Marek,
On Tue, Aug 6, 2013 at 6:17 AM, Marek Szyprowski
<[email protected]> wrote:
...
> IMHO it is much better to have a simple driver, which binds to a single
> IOMMU controller and leave it to the driver whether to have a same virtual address
> space for all parts of FIMC-IS or MFC submodules/memory ports or not.
I understand this part. I having written the IOMMU support for 4
different IOMMUs, all of which had exactly one IO Page Table and one
IOMMU shared by many devices.
> Just make sure that it will be possible to attach more than one sysmmu
> controller to one iommu domain.
I don't understand how this is possible. Can someone explain this
better in the IOMMU documentation please?
"iommu domain" to me means one virtual IO address space for attached
devices that can master DMA transactions. The IOMMU then uses it's IO
Page Table to translate the DMA address to the system physical address
space and forwards the transaction.
What is the role of the sysmmu in all of this?
Is the sysmmu just the MMU (or collection of MMU) for host DRAM?
Or is sysmmu responsible for "other stuff"? (clocks, power domains, MMU, etc)
I can understand we might have multiple MMUs in a system...e.g. every
range of memory might have it's own MMU. But they share the same
physical address space and generally live under one page table.
Because of "one page table" I would consider them one entity from the
the IOMMUs perspective.
thanks,
grant
> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On Behalf Of Grant Grundler
> Sent: Wednesday, August 07, 2013 1:07 AM
> To: Marek Szyprowski
>
> Hi Marek,
>
> On Tue, Aug 6, 2013 at 6:17 AM, Marek Szyprowski
> <[email protected]> wrote:
> ...
> > IMHO it is much better to have a simple driver, which binds to a single
> > IOMMU controller and leave it to the driver whether to have a same virtual address
> > space for all parts of FIMC-IS or MFC submodules/memory ports or not.
>
> I understand this part. I having written the IOMMU support for 4
> different IOMMUs, all of which had exactly one IO Page Table and one
> IOMMU shared by many devices.
>
> > Just make sure that it will be possible to attach more than one sysmmu
> > controller to one iommu domain.
>
> I don't understand how this is possible. Can someone explain this
> better in the IOMMU documentation please?
System MMU is dedicated to a master H/W such as FIMD and FIMC.
Thus, attaching a master H/W to an iommu domain can be thought as
attaching a System MMU to an iommu domain even though such thinking
is not correct view of the relationship between iommu domain and
System MMU.
>
> "iommu domain" to me means one virtual IO address space for attached
> devices that can master DMA transactions. The IOMMU then uses it's IO
> Page Table to translate the DMA address to the system physical address
> space and forwards the transaction.
>
> What is the role of the sysmmu in all of this?
> Is the sysmmu just the MMU (or collection of MMU) for host DRAM?
> Or is sysmmu responsible for "other stuff"? (clocks, power domains, MMU, etc)
>
System MMU is responsible for address translation of traffic from a
master H/W which the System MMU is dedicated to.
> I can understand we might have multiple MMUs in a system...e.g. every
> range of memory might have it's own MMU. But they share the same
> physical address space and generally live under one page table.
> Because of "one page table" I would consider them one entity from the
> the IOMMUs perspective.
Sorry, I don't understand.
Do you mean you are thinking that it is better to share one page table
by all IOMMUs in a system?
Thank you,
KyongHo
>
> thanks,
> grant
On Wed, Aug 7, 2013 at 5:07 AM, Cho KyongHo <[email protected]> wrote:
...
>> I don't understand how this is possible. Can someone explain this
>> better in the IOMMU documentation please?
>
> System MMU is dedicated to a master H/W such as FIMD and FIMC.
Sory - Exynos 5250 documentation I have (confidential version) uses
FIMD and FIMC but never explains what they are nor identifies them in
a diagram. Based on the references, they are related to the video
mixer but I don't know exactly what function FIMD/FIMC serve.
> Thus, attaching a master H/W to an iommu domain can be thought as
> attaching a System MMU to an iommu domain even though such thinking
> is not correct view of the relationship between iommu domain and
> System MMU.
This almost makes sense. I understand the above to mean the System MMU
is a proxy for the FIMD and FIMC.
>> I can understand we might have multiple MMUs in a system...e.g. every
>> range of memory might have it's own MMU. But they share the same
>> physical address space and generally live under one page table.
>> Because of "one page table" I would consider them one entity from the
>> the IOMMUs perspective.
>
> Sorry, I don't understand.
> Do you mean you are thinking that it is better to share one page table
> by all IOMMUs in a system?
No. This is how the previous IOMMUs I worked on functioned. It doesn't
mean this is how current ones should.
My example above was referring to CPU MMUs in the case of NUMA
architectures. Each NUMA CPU socket can have it's own MMU (and TLB)
and corresponding memory controller. All CPUs in an SMP system map
process and kernel virtual addresses to one common "physical" address
space. This means allocation and use of "physical address space" has
to be managed as one entity (even if several page tables exist in the
implementation - e.g. NUMA).
Back to the original comment that started my question (pulled out of
context now...sorry):
"Just make sure that it will be possible to attach more than one
sysmmu controller to one iommu domain."
Does that mean the IOMMU now has to map to multiple "physical address
spaces" or am I completely missing what a SysMMU does?
The "SysMMU" is the System Memory Management Unit, right?
I still thinking one IOMMU domain maps one (IO) virtual address space
to one (common with CPU and other IOMMU) physical address space.
cheers,
grant
>
> Thank you,
> KyongHo
>>
>> thanks,
>> grant
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On Behalf Of Grant Grundler
> Sent: Thursday, August 08, 2013 1:21 AM
>
> On Wed, Aug 7, 2013 at 5:07 AM, Cho KyongHo <[email protected]> wrote:
> ...
> >> I don't understand how this is possible. Can someone explain this
> >> better in the IOMMU documentation please?
> >
> > System MMU is dedicated to a master H/W such as FIMD and FIMC.
>
> Sory - Exynos 5250 documentation I have (confidential version) uses
> FIMD and FIMC but never explains what they are nor identifies them in
> a diagram. Based on the references, they are related to the video
> mixer but I don't know exactly what function FIMD/FIMC serve.
Ok.
FIMD is a display controller that reads RGB data and conveys the data
to the screen.
FIMC performs various functions including storing camera censor data to
the memory, image post processing like scaling, color space conversion
and rotation and conveying the processed data to FIMD.
>
>
> > Thus, attaching a master H/W to an iommu domain can be thought as
> > attaching a System MMU to an iommu domain even though such thinking
> > is not correct view of the relationship between iommu domain and
> > System MMU.
>
> This almost makes sense. I understand the above to mean the System MMU
> is a proxy for the FIMD and FIMC.
>
> >> I can understand we might have multiple MMUs in a system...e.g. every
> >> range of memory might have it's own MMU. But they share the same
> >> physical address space and generally live under one page table.
> >> Because of "one page table" I would consider them one entity from the
> >> the IOMMUs perspective.
> >
> > Sorry, I don't understand.
> > Do you mean you are thinking that it is better to share one page table
> > by all IOMMUs in a system?
>
> No. This is how the previous IOMMUs I worked on functioned. It doesn't
> mean this is how current ones should.
>
> My example above was referring to CPU MMUs in the case of NUMA
> architectures. Each NUMA CPU socket can have it's own MMU (and TLB)
> and corresponding memory controller. All CPUs in an SMP system map
> process and kernel virtual addresses to one common "physical" address
> space. This means allocation and use of "physical address space" has
> to be managed as one entity (even if several page tables exist in the
> implementation - e.g. NUMA).
>
>
> Back to the original comment that started my question (pulled out of
> context now...sorry):
> "Just make sure that it will be possible to attach more than one
> sysmmu controller to one iommu domain."
>
> Does that mean the IOMMU now has to map to multiple "physical address
> spaces" or am I completely missing what a SysMMU does?
I think I have explained what the quotation actually intended.
Exynos System MMUs in a SoC have the same view of physical address space.
But they provide different views of memory to their master H/Ws.
I think this is what Marek wanted to say.
>
> The "SysMMU" is the System Memory Management Unit, right?
Yes it is IOMMU in Exynos SoCs.
It is referred as "SysMMU", "sysmmu", "smmu" or "System MMU".
All are the same in the context of Exynos SoCs.
It is not an implementation of ARM System MMU specifications.
>
> I still thinking one IOMMU domain maps one (IO) virtual address space
> to one (common with CPU and other IOMMU) physical address space.
Definitely I agree with you.
However, this discussion is not started from Marek's comment that
several System MMUs can be attached to the same page table
It actually means:
-> providing the same virtual address space to their master H/W
-> ** The master H/Ws are attached to the same iommu domain. **
Regards,
KyongHo.
>
> cheers,
> grant
>
> >
> > Thank you,
> > KyongHo
> >>
> >> thanks,
> >> grant
> >
On Thu, Aug 1, 2013 at 8:05 AM, Cho KyongHo <[email protected]> wrote:
>> -----Original Message-----
>> From: Rob Herring [mailto:[email protected]]
>> Sent: Saturday, July 27, 2013 10:55 PM
>> On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo <[email protected]> wrote:
>> > Signed-off-by: Cho KyongHo <[email protected]>
>> > ---
>> > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
>> > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
>> > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
>> > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
>> > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
>> > 5 files changed, 617 insertions(+), 0 deletions(-)
>> > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>> > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>> > new file mode 100644
>> > index 0000000..92f0a33
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>> > @@ -0,0 +1,103 @@
>> > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
>> > +
>> > +Samsung's Exynos architecture contains System MMU that enables scattered
>> > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
>> > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
>> > +
>> > +System MMU is a sort of IOMMU and support identical translation table format to
>> > +ARMv7 translation tables with minimum set of page properties including access
>> > +permissions, shareability and security protection. In addition, System MMU has
>> > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
>> > +latency.
>> > +
>> > +A System MMU is dedicated to a single master peripheral device. Thus, it is
>> > +important to specify the correct System MMU in the device node of its master
>> > +device. Whereas a System MMU is dedicated to a master device, the master device
>> > +may have more than one System MMU.
>>
>> I don't follow the last sentence. Can you elaborate on the type of
>> connection you are talking about.
>>
> Grant also addressed that.
> He corrected the sentence like the following:
>
> " Can I suggest rewriting the last two sentences to:
> The master device node must correctly specify at least one
> SystemMMU. A master device may have more than one System MMU. "
>
> I will change the sentence
>
>> Also, please align with the ARM system MMU binding that Will Deacon
>> has submitted particularly in terms of how master connections are
>> described.
>>
> I didn't check it.
>
> Should this align with ARM System MMU bindings?
> System MMU in Exynos SoC is different from ARM System MMU.
> It does not follows the specifications of ARM System MMU.
I'm not saying the h/w is the same or even the same spec, but how you
describe a master to iommu connection needs to be done in the same
way. This should be done in the same way for ALL iommu's. And if what
is defined does not work for you, then we need to understand that and
fix the binding now.
Rob
On Thursday 08 of August 2013 08:09:49 Rob Herring wrote:
> On Thu, Aug 1, 2013 at 8:05 AM, Cho KyongHo <[email protected]>
wrote:
> >> -----Original Message-----
> >> From: Rob Herring [mailto:[email protected]]
> >> Sent: Saturday, July 27, 2013 10:55 PM
> >>
> >> On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo <[email protected]>
wrote:
> >> > Signed-off-by: Cho KyongHo <[email protected]>
> >> > ---
> >> >
> >> > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> >> > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> >> > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> >> > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> >> > arch/arm/boot/dts/exynos5250.dtsi | 291
> >> > ++++++++++++++++++++ 5 files changed, 617 insertions(+), 0
> >> > deletions(-)
> >> > create mode 100644
> >> > Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu
> >> > .txt>> >
> >> > diff --git
> >> > a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmm
> >> > u.txt
> >> > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmm
> >> > u.txt new file mode 100644
> >> > index 0000000..92f0a33
> >> > --- /dev/null
> >> > +++
> >> > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmm
> >> > u.txt @@ -0,0 +1,103 @@
> >> > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management
> >> > Unit) +
> >> > +Samsung's Exynos architecture contains System MMU that enables
> >> > scattered +physical memory chunks visible as a contiguous region
> >> > to DMA-capable peripheral +devices like MFC, FIMC, FIMD, GScaler,
> >> > FIMC-IS and so forth.
> >> > +
> >> > +System MMU is a sort of IOMMU and support identical translation
> >> > table format to +ARMv7 translation tables with minimum set of page
> >> > properties including access +permissions, shareability and
> >> > security protection. In addition, System MMU has +another
> >> > capabilities like L2 TLB or block-fetch buffers to minimize
> >> > translation +latency.
> >> > +
> >> > +A System MMU is dedicated to a single master peripheral device.
> >> > Thus, it is +important to specify the correct System MMU in the
> >> > device node of its master +device. Whereas a System MMU is
> >> > dedicated to a master device, the master device +may have more
> >> > than one System MMU.
> >>
> >> I don't follow the last sentence. Can you elaborate on the type of
> >> connection you are talking about.
> >
> > Grant also addressed that.
> >
> > He corrected the sentence like the following:
> > " Can I suggest rewriting the last two sentences to:
> > The master device node must correctly specify at least one
> > SystemMMU. A master device may have more than one System MMU. "
> >
> > I will change the sentence
> >
> >> Also, please align with the ARM system MMU binding that Will Deacon
> >> has submitted particularly in terms of how master connections are
> >> described.
> >
> > I didn't check it.
> >
> > Should this align with ARM System MMU bindings?
> > System MMU in Exynos SoC is different from ARM System MMU.
> > It does not follows the specifications of ARM System MMU.
>
> I'm not saying the h/w is the same or even the same spec, but how you
> describe a master to iommu connection needs to be done in the same
> way. This should be done in the same way for ALL iommu's. And if what
> is defined does not work for you, then we need to understand that and
> fix the binding now.
+1
All IOMMUs should use a generic IOMMU Device Tree bindings (and in
general, the same should be true for all Device Tree bindings).
This means that if we already have some bindings for IOMMU, then they
should be reused if possible or extended if there is anything missing.
Of course there might be things that such generic bindings can't specify.
In this case device-specific properties can be introduced, but this is
last resort.
Best regards,
Tomasz
On Thu, Aug 08, 2013 at 10:38:10PM +0100, Tomasz Figa wrote:
> On Thursday 08 of August 2013 08:09:49 Rob Herring wrote:
> > On Thu, Aug 1, 2013 at 8:05 AM, Cho KyongHo <[email protected]>
> wrote:
> > > Should this align with ARM System MMU bindings?
> > > System MMU in Exynos SoC is different from ARM System MMU.
> > > It does not follows the specifications of ARM System MMU.
> >
> > I'm not saying the h/w is the same or even the same spec, but how you
> > describe a master to iommu connection needs to be done in the same
> > way. This should be done in the same way for ALL iommu's. And if what
> > is defined does not work for you, then we need to understand that and
> > fix the binding now.
>
> +1
>
> All IOMMUs should use a generic IOMMU Device Tree bindings (and in
> general, the same should be true for all Device Tree bindings).
>
> This means that if we already have some bindings for IOMMU, then they
> should be reused if possible or extended if there is anything missing.
>
> Of course there might be things that such generic bindings can't specify.
> In this case device-specific properties can be introduced, but this is
> last resort.
I'm also happy to discuss and/or review bindings in light of what we did for
the ARM SMMU.
Will
On Thu, 08 Aug 2013 22:43:43 +0100, Will Deacon wrote:
> On Thu, Aug 08, 2013 at 10:38:10PM +0100, Tomasz Figa wrote:
> > On Thursday 08 of August 2013 08:09:49 Rob Herring wrote:
> > > On Thu, Aug 1, 2013 at 8:05 AM, Cho KyongHo <[email protected]>
> > wrote:
> > > > Should this align with ARM System MMU bindings?
> > > > System MMU in Exynos SoC is different from ARM System MMU.
> > > > It does not follows the specifications of ARM System MMU.
> > >
> > > I'm not saying the h/w is the same or even the same spec, but how you
> > > describe a master to iommu connection needs to be done in the same
> > > way. This should be done in the same way for ALL iommu's. And if what
> > > is defined does not work for you, then we need to understand that and
> > > fix the binding now.
> >
> > +1
> >
> > All IOMMUs should use a generic IOMMU Device Tree bindings (and in
> > general, the same should be true for all Device Tree bindings).
> >
> > This means that if we already have some bindings for IOMMU, then they
> > should be reused if possible or extended if there is anything missing.
> >
> > Of course there might be things that such generic bindings can't specify.
> > In this case device-specific properties can be introduced, but this is
> > last resort.
>
> I'm also happy to discuss and/or review bindings in light of what we did for
> the ARM SMMU.
>
> Will
Rob, I now understood what you are talking about.
Do you mean the binding description is lack of details about connection
betwen System MMU and its master?
thanks.
KyongHo.
On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo <[email protected]> wrote:
> Signed-off-by: Cho KyongHo <[email protected]>
> ---
> .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> 5 files changed, 617 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
>
> diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> new file mode 100644
> index 0000000..92f0a33
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> @@ -0,0 +1,103 @@
> +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> +
> +Samsung's Exynos architecture contains System MMU that enables scattered
> +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> +
> +System MMU is a sort of IOMMU and support identical translation table format to
> +ARMv7 translation tables with minimum set of page properties including access
> +permissions, shareability and security protection. In addition, System MMU has
> +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> +latency.
> +
> +A System MMU is dedicated to a single master peripheral device. Thus, it is
> +important to specify the correct System MMU in the device node of its master
> +device. Whereas a System MMU is dedicated to a master device, the master device
> +may have more than one System MMU.
> +
> +Required properties:
> +- compatible: Should be "samsung,exynos4210-sysmmu"
> +- reg: A tuple of base address and size of System MMU registers.
> +- interrupt-parent: The phandle of the interrupt controller of System MMU
> +- interrupts: A tuple of numbers that indicates the interrupt source.
> +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> + Please refer to the following documents:
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> + Optional "master" if the clock to the System MMU is gated by
> + another gate clock other than "sysmmu". The System MMU driver
> + sets "master" the parent of "sysmmu".
> + Exynos4 SoCs, there needs no "master" clocks.
> + Exynos5 SoCs, some System MMUs must have "master" clocks.
> +- clocks: Required if the System MMU is needed to gate its clock.
> + Please refer to the documents listed above.
> +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> + Please refer to the following document:
> + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> +
> +Required properties for the master peripheral devices:
> +- iommu: phandles to the System MMUs of the device
You have not addressed my comments from the last version. We do not
need 2 (or more) different ways to describe the connection between
masters and iommu's. Use mmu-masters property here to describe the
connection.
Rob
On Mon, 07 Oct 2013 08:44:54 -0500, Rob Herring wrote:
> On Fri, Jul 26, 2013 at 6:28 AM, Cho KyongHo <[email protected]> wrote:
> > Signed-off-by: Cho KyongHo <[email protected]>
> > ---
> > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++++++
> > arch/arm/boot/dts/exynos4.dtsi | 122 ++++++++
> > arch/arm/boot/dts/exynos4210.dtsi | 25 ++
> > arch/arm/boot/dts/exynos4x12.dtsi | 76 +++++
> > arch/arm/boot/dts/exynos5250.dtsi | 291 ++++++++++++++++++++
> > 5 files changed, 617 insertions(+), 0 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > new file mode 100644
> > index 0000000..92f0a33
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
> > @@ -0,0 +1,103 @@
> > +Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
> > +
> > +Samsung's Exynos architecture contains System MMU that enables scattered
> > +physical memory chunks visible as a contiguous region to DMA-capable peripheral
> > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
> > +
> > +System MMU is a sort of IOMMU and support identical translation table format to
> > +ARMv7 translation tables with minimum set of page properties including access
> > +permissions, shareability and security protection. In addition, System MMU has
> > +another capabilities like L2 TLB or block-fetch buffers to minimize translation
> > +latency.
> > +
> > +A System MMU is dedicated to a single master peripheral device. Thus, it is
> > +important to specify the correct System MMU in the device node of its master
> > +device. Whereas a System MMU is dedicated to a master device, the master device
> > +may have more than one System MMU.
> > +
> > +Required properties:
> > +- compatible: Should be "samsung,exynos4210-sysmmu"
> > +- reg: A tuple of base address and size of System MMU registers.
> > +- interrupt-parent: The phandle of the interrupt controller of System MMU
> > +- interrupts: A tuple of numbers that indicates the interrupt source.
> > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
> > + Please refer to the following documents:
> > + Documentation/devicetree/bindings/clock/clock-bindings.txt
> > + Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> > + Optional "master" if the clock to the System MMU is gated by
> > + another gate clock other than "sysmmu". The System MMU driver
> > + sets "master" the parent of "sysmmu".
> > + Exynos4 SoCs, there needs no "master" clocks.
> > + Exynos5 SoCs, some System MMUs must have "master" clocks.
> > +- clocks: Required if the System MMU is needed to gate its clock.
> > + Please refer to the documents listed above.
> > +- samsung,power-domain: Required if the System MMU is needed to gate its power.
> > + Please refer to the following document:
> > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> > +
> > +Required properties for the master peripheral devices:
> > +- iommu: phandles to the System MMUs of the device
>
> You have not addressed my comments from the last version. We do not
> need 2 (or more) different ways to describe the connection between
> masters and iommu's. Use mmu-masters property here to describe the
> connection.
>
Sorry, I forgot to reply.
I just thought the meaning of your comment that it should be align with ARM System MMU.
I now understand and it should be changed to mmu-masters property
because it is now in the kernel.
Thank you.
> Rob