From: Robert Richter <[email protected]>
This initial patches enable Cavium Thunder SoC Family. The patches add
Kconfig and devicetree support and then add Thunder to the defconfig.
The last patch is unrelated to Thunder and enables the tmpfs mount
option for a more convinient use of defconfig with distros.
The Thunder system needs more enablement patches for subsystems and
devices, this includes network, ahci, gicv3/gicv3-its, pci, smmu, kvm.
We will send separate patch sets for these. All of them base on this
initial patches.
Patches are available here:
git://git.kernel.org/pub/scm/linux/kernel/git/rric/linux.git thunder/init
Radha Mohan Chintakuntla (3):
arm64, thunder: Add Kconfig option for Cavium Thunder SoC Family
arm64, thunder: Add initial dts for Cavium Thunder SoC
arm64, thunder: document devicetree bindings for Cavium Thunder SoC
Robert Richter (2):
arm64, defconfig: Enable Cavium Thunder SoC in defconfig
arm64, defconfig: Enable tmpfs mount option
.../devicetree/bindings/arm/cavium-thunder.txt | 10 +
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm64/Kconfig | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/thunder-88xx.dts | 387 +++++++++++++++++++++
arch/arm64/configs/defconfig | 2 +
6 files changed, 407 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder.txt
create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
--
2.0.1
From: Robert Richter <[email protected]>
This patch enables Thunder SoCs in the arm64 defconfig. This is
esp. useful to add Thunder platforms to automated builds based on
arm64 defconfig.
Signed-off-by: Robert Richter <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3421f316f5dc..26c3ab582db5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -32,6 +32,7 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_XGENE=y
CONFIG_SMP=y
--
2.0.1
From: Radha Mohan Chintakuntla <[email protected]>
Increase maximum numbers of cpus to 32. This relates to current
maximal possible cpu number. Increasing this to 64 cpus will be a
separate patch not part of this enablement patches.
Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
---
arch/arm64/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a474de346be6..e989d8cab8c7 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -128,6 +128,11 @@ source "kernel/Kconfig.freezer"
menu "Platform selection"
+config ARCH_THUNDER
+ bool "Cavium Inc. Thunder SoC Family"
+ help
+ This enables support for Cavium's Thunder Family of SoCs.
+
config ARCH_VEXPRESS
bool "ARMv8 software model (Versatile Express)"
select ARCH_REQUIRE_GPIOLIB
@@ -201,6 +206,7 @@ config NR_CPUS
range 2 32
depends on SMP
# These have to remain sorted largest to smallest
+ default "32" if ARCH_THUNDER
default "8"
config HOTPLUG_CPU
--
2.0.1
From: Robert Richter <[email protected]>
Making it more convinient to run the arm64 default kernel as distros
like Ubuntu need this option.
Signed-off-by: Robert Richter <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 26c3ab582db5..50ea69d51bb4 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -55,6 +55,7 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
--
2.0.1
From: Radha Mohan Chintakuntla <[email protected]>
Add initial device tree nodes for Cavium Thunder SoCs with support of
48 cores and gicv3. The dts file requires further changes, esp. for
pci, gicv3-its and smmu. This changes will be added later together
with the device drivers.
Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/thunder-88xx.dts | 387 +++++++++++++++++++++++++++++++++++
2 files changed, 388 insertions(+)
create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb051f66..f8001a62029c 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
diff --git a/arch/arm64/boot/dts/thunder-88xx.dts b/arch/arm64/boot/dts/thunder-88xx.dts
new file mode 100644
index 000000000000..4cf20ac9138b
--- /dev/null
+++ b/arch/arm64/boot/dts/thunder-88xx.dts
@@ -0,0 +1,387 @@
+/*
+ * Cavium Thunder DTS file
+ *
+ * Copyright (C) 2013, Cavium Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+/dts-v1/;
+
+/* Reserving first 12MB of DDR for firmware */
+/memreserve/ 0x00000000 0x00c00000;
+
+/ {
+ model = "Cavium ThunderX CN88XX Family";
+ compatible = "cavium,thunder-88xx";
+ interrupt-parent = <&gic0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uaa0;
+ serial1 = &uaa1;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@000 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x000>;
+ enable-method = "psci";
+ };
+ cpu@001 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x001>;
+ enable-method = "psci";
+ };
+ cpu@002 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x002>;
+ enable-method = "psci";
+ };
+ cpu@003 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x003>;
+ enable-method = "psci";
+ };
+ cpu@004 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x004>;
+ enable-method = "psci";
+ };
+ cpu@005 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x005>;
+ enable-method = "psci";
+ };
+ cpu@006 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x006>;
+ enable-method = "psci";
+ };
+ cpu@007 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x007>;
+ enable-method = "psci";
+ };
+ cpu@008 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x008>;
+ enable-method = "psci";
+ };
+ cpu@009 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x009>;
+ enable-method = "psci";
+ };
+ cpu@00a {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00a>;
+ enable-method = "psci";
+ };
+ cpu@00b {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00b>;
+ enable-method = "psci";
+ };
+ cpu@00c {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00c>;
+ enable-method = "psci";
+ };
+ cpu@00d {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00d>;
+ enable-method = "psci";
+ };
+ cpu@00e {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00e>;
+ enable-method = "psci";
+ };
+ cpu@00f {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x00f>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ };
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ };
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ };
+ cpu@104 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x104>;
+ enable-method = "psci";
+ };
+ cpu@105 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x105>;
+ enable-method = "psci";
+ };
+ cpu@106 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x106>;
+ enable-method = "psci";
+ };
+ cpu@107 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x107>;
+ enable-method = "psci";
+ };
+ cpu@108 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x108>;
+ enable-method = "psci";
+ };
+ cpu@109 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x109>;
+ enable-method = "psci";
+ };
+ cpu@10a {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10a>;
+ enable-method = "psci";
+ };
+ cpu@10b {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10b>;
+ enable-method = "psci";
+ };
+ cpu@10c {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10c>;
+ enable-method = "psci";
+ };
+ cpu@10d {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10d>;
+ enable-method = "psci";
+ };
+ cpu@10e {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10e>;
+ enable-method = "psci";
+ };
+ cpu@10f {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x10f>;
+ enable-method = "psci";
+ };
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x201>;
+ enable-method = "psci";
+ };
+ cpu@202 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x202>;
+ enable-method = "psci";
+ };
+ cpu@203 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x203>;
+ enable-method = "psci";
+ };
+ cpu@204 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x204>;
+ enable-method = "psci";
+ };
+ cpu@205 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x205>;
+ enable-method = "psci";
+ };
+ cpu@206 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x206>;
+ enable-method = "psci";
+ };
+ cpu@207 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x207>;
+ enable-method = "psci";
+ };
+ cpu@208 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x208>;
+ enable-method = "psci";
+ };
+ cpu@209 {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x209>;
+ enable-method = "psci";
+ };
+ cpu@20a {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20a>;
+ enable-method = "psci";
+ };
+ cpu@20b {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20b>;
+ enable-method = "psci";
+ };
+ cpu@20c {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20c>;
+ enable-method = "psci";
+ };
+ cpu@20d {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20d>;
+ enable-method = "psci";
+ };
+ cpu@20e {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20e>;
+ enable-method = "psci";
+ };
+ cpu@20f {
+ device_type = "cpu";
+ compatible = "cavium,thunder", "arm,armv8";
+ reg = <0x0 0x20f>;
+ enable-method = "psci";
+ };
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0x80000000>;
+ };
+
+ gic0: interrupt-controller@801000000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
+ <0x8010 0x80000000 0x0 0x200000>; /* GICR */
+ interrupts = <1 9 0xf04>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xff01>,
+ <1 14 0xff01>,
+ <1 11 0xff01>,
+ <1 10 0xff01>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ refclk50mhz: refclk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "refclk50mhz";
+ };
+ };
+
+ uaa0: serial@87e024000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x87e0 0x24000000 0x0 0x1000>;
+ interrupts = <1 21 4>;
+ clocks = <&refclk50mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ uaa1: serial@87e025000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x87e0 0x25000000 0x0 0x1000>;
+ interrupts = <1 22 4>;
+ clocks = <&refclk50mhz>;
+ clock-names = "apb_pclk";
+ };
+ };
+};
--
2.0.1
From: Radha Mohan Chintakuntla <[email protected]>
This patch adds documentation for the devicetree bindings used by the
DT files of Cavium Thunder SoC platforms.
Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
---
Documentation/devicetree/bindings/arm/cavium-thunder.txt | 10 ++++++++++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
2 files changed, 11 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder.txt
diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
new file mode 100644
index 000000000000..6f63a5866902
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
@@ -0,0 +1,10 @@
+Cavium Thunder platform device tree bindings
+--------------------------------------------
+
+Boards with Cavium's Thunder SoC shall have following properties.
+
+Root Node
+---------
+Required root node properties:
+
+ - compatible = "cavium,thunder-88xx";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1fe72a0778cd..922e4970309d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-r4"
"arm,cortex-r5"
"arm,cortex-r7"
+ "cavium,thunder"
"faraday,fa526"
"intel,sa110"
"intel,sa1100"
--
2.0.1
Hi,
On Wed, Jul 30, 2014 at 04:06:31PM +0100, Robert Richter wrote:
> From: Radha Mohan Chintakuntla <[email protected]>
>
> Add initial device tree nodes for Cavium Thunder SoCs with support of
> 48 cores and gicv3. The dts file requires further changes, esp. for
> pci, gicv3-its and smmu. This changes will be added later together
> with the device drivers.
>
> Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/thunder-88xx.dts | 387 +++++++++++++++++++++++++++++++++++
> 2 files changed, 388 insertions(+)
> create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index c52bdb051f66..f8001a62029c 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
> dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
>
> diff --git a/arch/arm64/boot/dts/thunder-88xx.dts b/arch/arm64/boot/dts/thunder-88xx.dts
> new file mode 100644
> index 000000000000..4cf20ac9138b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/thunder-88xx.dts
> @@ -0,0 +1,387 @@
> +/*
> + * Cavium Thunder DTS file
> + *
> + * Copyright (C) 2013, Cavium Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +/dts-v1/;
> +
> +/* Reserving first 12MB of DDR for firmware */
> +/memreserve/ 0x00000000 0x00c00000;
What exactly is this memreserve intended to protect at runtime?
The only item of runtime firmware I see in use below is PSCI on the
secure side.
How is the kernel booted on this platform? UEFI?
> +/ {
> + model = "Cavium ThunderX CN88XX Family";
> + compatible = "cavium,thunder-88xx";
Please don't use wildcards in compatible strings. Give this an absolute
name, and override as necessary.
> + interrupt-parent = <&gic0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &uaa0;
> + serial1 = &uaa1;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
Nice!
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu@000 {
> + device_type = "cpu";
> + compatible = "cavium,thunder", "arm,armv8";
> + reg = <0x0 0x000>;
> + enable-method = "psci";
> + };
Just to check: both the SoC and CPU are called thunder?
[...]
> +
> + memory@00000000 {
> + device_type = "memory";
> + reg = <0x0 0x00000000 0x0 0x80000000>;
> + };
> +
> + gic0: interrupt-controller@801000000000 {
To make this easier to read, please place a comma between 32-bit
portions of the unit address (e.g. here have 8010,00000000).
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
This has no children, so why have ranges, #address-cells, and
#size-cells?
> + interrupt-controller;
> + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
> + <0x8010 0x80000000 0x0 0x200000>; /* GICR */
> + interrupts = <1 9 0xf04>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <1 13 0xff01>,
> + <1 14 0xff01>,
> + <1 11 0xff01>,
> + <1 10 0xff01>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + refclk50mhz: refclk50mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + clock-output-names = "refclk50mhz";
> + };
> + };
Please get rid of the clocks node and just put the clocks here.
> +
> + uaa0: serial@87e024000000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x87e0 0x24000000 0x0 0x1000>;
> + interrupts = <1 21 4>;
> + clocks = <&refclk50mhz>;
> + clock-names = "apb_pclk";
Is this actually the apb_pclk, or is the the uartclk? I assume it's the
latter.
> + };
> +
> + uaa1: serial@87e025000000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x87e0 0x25000000 0x0 0x1000>;
> + interrupts = <1 22 4>;
> + clocks = <&refclk50mhz>;
> + clock-names = "apb_pclk";
Similarly?
Thanks,
Mark.
On Wed, Jul 30, 2014 at 10:46 AM, Mark Rutland <[email protected]> wrote:
> Hi,
>
> On Wed, Jul 30, 2014 at 04:06:31PM +0100, Robert Richter wrote:
>> From: Radha Mohan Chintakuntla <[email protected]>
>>
>> Add initial device tree nodes for Cavium Thunder SoCs with support of
>> 48 cores and gicv3. The dts file requires further changes, esp. for
>> pci, gicv3-its and smmu. This changes will be added later together
>> with the device drivers.
>>
>> Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
>> Signed-off-by: Robert Richter <[email protected]>
>> ---
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/thunder-88xx.dts | 387 +++++++++++++++++++++++++++++++++++
>> 2 files changed, 388 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
>>
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index c52bdb051f66..f8001a62029c 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -1,3 +1,4 @@
>> +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
>> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
>> dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
>>
>> diff --git a/arch/arm64/boot/dts/thunder-88xx.dts b/arch/arm64/boot/dts/thunder-88xx.dts
>> new file mode 100644
>> index 000000000000..4cf20ac9138b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/thunder-88xx.dts
>> @@ -0,0 +1,387 @@
>> +/*
>> + * Cavium Thunder DTS file
>> + *
>> + * Copyright (C) 2013, Cavium Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + */
You may want to reconsider if this should be BSD.
>> +/dts-v1/;
>> +
>> +/* Reserving first 12MB of DDR for firmware */
>> +/memreserve/ 0x00000000 0x00c00000;
>
> What exactly is this memreserve intended to protect at runtime?
>
> The only item of runtime firmware I see in use below is PSCI on the
> secure side.
>
> How is the kernel booted on this platform? UEFI?
>
>> +/ {
>> + model = "Cavium ThunderX CN88XX Family";
>> + compatible = "cavium,thunder-88xx";
>
> Please don't use wildcards in compatible strings. Give this an absolute
> name, and override as necessary.
>
>> + interrupt-parent = <&gic0>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + aliases {
>> + serial0 = &uaa0;
>> + serial1 = &uaa1;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-0.2";
>> + method = "smc";
>> + };
>
> Nice!
>
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu@000 {
>> + device_type = "cpu";
>> + compatible = "cavium,thunder", "arm,armv8";
>> + reg = <0x0 0x000>;
>> + enable-method = "psci";
>> + };
>
> Just to check: both the SoC and CPU are called thunder?
>
> [...]
>
>> +
>> + memory@00000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x00000000 0x0 0x80000000>;
>> + };
>> +
>> + gic0: interrupt-controller@801000000000 {
>
> To make this easier to read, please place a comma between 32-bit
> portions of the unit address (e.g. here have 8010,00000000).
Mark, perhaps a dtc or checkpatch.pl check for this?
This should also be under a bus node.
>> + compatible = "arm,gic-v3";
>> + #interrupt-cells = <3>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>
> This has no children, so why have ranges, #address-cells, and
> #size-cells?
>
>> + interrupt-controller;
>> + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
>> + <0x8010 0x80000000 0x0 0x200000>; /* GICR */
>> + interrupts = <1 9 0xf04>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <1 13 0xff01>,
>> + <1 14 0xff01>,
>> + <1 11 0xff01>,
>> + <1 10 0xff01>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clocks {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + refclk50mhz: refclk50mhz {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <50000000>;
>> + clock-output-names = "refclk50mhz";
>> + };
>> + };
>
> Please get rid of the clocks node and just put the clocks here.
>
>> +
>> + uaa0: serial@87e024000000 {
>> + compatible = "arm,pl011", "arm,primecell";
>> + reg = <0x87e0 0x24000000 0x0 0x1000>;
>> + interrupts = <1 21 4>;
>> + clocks = <&refclk50mhz>;
>> + clock-names = "apb_pclk";
>
> Is this actually the apb_pclk, or is the the uartclk? I assume it's the
> latter.
Shouldn't new bindings have both clocks here? A single clock was a
mistake I think (mine in fact).
Rob
[...]
> >> + gic0: interrupt-controller@801000000000 {
> >
> > To make this easier to read, please place a comma between 32-bit
> > portions of the unit address (e.g. here have 8010,00000000).
>
> Mark, perhaps a dtc or checkpatch.pl check for this?
Sure. Dodgy first atttempt at checkpatch below.
---->8----
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 182be0f..8aee3f5 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2136,6 +2136,14 @@ sub process {
}
}
+# check for difficult-to-read unit-addresses
+ if (defined $root &&
+ ($realfile =~ /\.dtsi?$/ && $line =~ /([a-z0-9._\-+]++@([0-9a-f]+))\s*{/gi) &&
+ (length($2) > 8)) {
+ WARN("LONG_DT_UNIT_ADDRESS",
+ "Consider splitting long unit address \"$2\" with a comma between cells\n" . $herecurr);
+ }
+
# check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
----8<----
It would also be nice to check matching unit-address and reg, but doing
that correctly requires knowing #address-cells, which sounds a little
painful.
I'm not sure where I picked up the comma convention, as it doesn't seem
to be in ePAPR. It does seem common though, and is my personal
preference:
[mark@leverpostej:~/src/linux]% git grep '@[a-z0-9]\+,[a-b0-9]\+' \
-- arch/arm/boot/dts | wc -l
254
[mark@leverpostej:~/src/linux]% git grep '@[a-z0-9]\+,[a-b0-9]\+' \
-- arch/powerpc/boot/dts | wc -l
370
[mark@leverpostej:~/src/linux]% git grep '@[a-z0-9]\+,[a-b0-9]\+' \
-- arch/*/boot/dts | wc -l
631
[...]
> >> + uaa0: serial@87e024000000 {
> >> + compatible = "arm,pl011", "arm,primecell";
> >> + reg = <0x87e0 0x24000000 0x0 0x1000>;
> >> + interrupts = <1 21 4>;
> >> + clocks = <&refclk50mhz>;
> >> + clock-names = "apb_pclk";
> >
> > Is this actually the apb_pclk, or is the the uartclk? I assume it's the
> > latter.
>
> Shouldn't new bindings have both clocks here? A single clock was a
> mistake I think (mine in fact).
I don't think we fixed it up in the end. It made drivers look a bit messy and
it dropped off my priority queue.
Cheers,
Mark.
On Wed, Jul 30, 2014 at 8:06 AM, Robert Richter <[email protected]> wrote:
> From: Radha Mohan Chintakuntla <[email protected]>
>
> Add initial device tree nodes for Cavium Thunder SoCs with support of
> 48 cores and gicv3. The dts file requires further changes, esp. for
> pci, gicv3-its and smmu. This changes will be added later together
> with the device drivers.
>
> Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/thunder-88xx.dts | 387 +++++++++++++++++++++++++++++++++++
> 2 files changed, 388 insertions(+)
> create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index c52bdb051f66..f8001a62029c 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
> dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
>
> diff --git a/arch/arm64/boot/dts/thunder-88xx.dts b/arch/arm64/boot/dts/thunder-88xx.dts
> new file mode 100644
> index 000000000000..4cf20ac9138b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/thunder-88xx.dts
> @@ -0,0 +1,387 @@
> +/*
> + * Cavium Thunder DTS file
> + *
> + * Copyright (C) 2013, Cavium Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +/dts-v1/;
> +
> +/* Reserving first 12MB of DDR for firmware */
> +/memreserve/ 0x00000000 0x00c00000;
> +
> +/ {
> + model = "Cavium ThunderX CN88XX Family";
> + compatible = "cavium,thunder-88xx";
Hmm. I take it this platform is compliant with some level of SBSA? We
should probably have a compatible value for that so that platforms can
communicate it.
Mark, are there already plans for this?
-Olof
On Wed, Jul 30, 2014 at 8:06 AM, Robert Richter <[email protected]> wrote:
> From: Radha Mohan Chintakuntla <[email protected]>
>
> Add initial device tree nodes for Cavium Thunder SoCs with support of
> 48 cores and gicv3. The dts file requires further changes, esp. for
> pci, gicv3-its and smmu. This changes will be added later together
> with the device drivers.
>
> Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/thunder-88xx.dts | 387 +++++++++++++++++++++++++++++++++++
> 2 files changed, 388 insertions(+)
> create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index c52bdb051f66..f8001a62029c 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
> dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
Oh, and:
Let's fix the mistake we made on 32-bit here (that we can't undo
unless we move all dts files now, which is too much churn), and put
each SoC vendor in its own subdirectory.
So, please add a arch/arm64/boot/dts/cavium/ directory, add a Makefile
and the dts there.
We should move vexpress under arm/ and xgene under apm/ too.
On Wed, Jul 30, 2014 at 07:12:17PM +0100, Olof Johansson wrote:
> On Wed, Jul 30, 2014 at 8:06 AM, Robert Richter <[email protected]> wrote:
> > From: Radha Mohan Chintakuntla <[email protected]>
> >
> > Add initial device tree nodes for Cavium Thunder SoCs with support of
> > 48 cores and gicv3. The dts file requires further changes, esp. for
> > pci, gicv3-its and smmu. This changes will be added later together
> > with the device drivers.
> >
> > Signed-off-by: Radha Mohan Chintakuntla <[email protected]>
> > Signed-off-by: Robert Richter <[email protected]>
> > ---
> > arch/arm64/boot/dts/Makefile | 1 +
> > arch/arm64/boot/dts/thunder-88xx.dts | 387 +++++++++++++++++++++++++++++++++++
> > 2 files changed, 388 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
> >
> > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> > index c52bdb051f66..f8001a62029c 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
> > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
> > dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
> >
> > diff --git a/arch/arm64/boot/dts/thunder-88xx.dts b/arch/arm64/boot/dts/thunder-88xx.dts
> > new file mode 100644
> > index 000000000000..4cf20ac9138b
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/thunder-88xx.dts
> > @@ -0,0 +1,387 @@
> > +/*
> > + * Cavium Thunder DTS file
> > + *
> > + * Copyright (C) 2013, Cavium Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + */
> > +/dts-v1/;
> > +
> > +/* Reserving first 12MB of DDR for firmware */
> > +/memreserve/ 0x00000000 0x00c00000;
> > +
> > +/ {
> > + model = "Cavium ThunderX CN88XX Family";
> > + compatible = "cavium,thunder-88xx";
>
> Hmm. I take it this platform is compliant with some level of SBSA? We
> should probably have a compatible value for that so that platforms can
> communicate it.
>
> Mark, are there already plans for this?
Not so far, but my monitor now has a sticky note telling me to look into
it. :)
Many of the useful properties provided by SBSA are already described
elsewhere (e.g. page and ASID size can be found in ID registers), and
hardware properties it mandates (e.g. PPI assignment for level 2
compliant systems) will be described elsewhere.
I'll have to read the spec in more detail to figure out what we can
derive from an SBSA compliance property. Regardless it probably makes
sense to have a compatible string or other property on the root node; at
worst it only costs us a few bytes.
Thanks,
Mark.
On Thu, Jul 31, 2014 at 09:41:10AM +0100, Ganapatrao Kulkarni wrote:
> On Wed, Jul 30, 2014 at 9:16 PM, Mark Rutland <[1][email protected]>
> wrote:
>
> Hi,
> On Wed, Jul 30, 2014 at 04:06:31PM +0100, Robert Richter wrote:
> > From: Radha Mohan Chintakuntla <[2][email protected]>
> >
> > Add initial device tree nodes for Cavium Thunder SoCs with support of
> > 48 cores and gicv3. The dts file requires further changes, esp. for
> > pci, gicv3-its and smmu. This changes will be added later together
> > with the device drivers.
> >
> > Signed-off-by: Radha Mohan Chintakuntla <[3][email protected]>
> > Signed-off-by: Robert Richter <[4][email protected]>
> > ---
> > arch/arm64/boot/dts/Makefile | 1 +
> > arch/arm64/boot/dts/thunder-88xx.dts | 387
> +++++++++++++++++++++++++++++++++++
> > 2 files changed, 388 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
> >
> > diff --git a/arch/arm64/boot/dts/Makefile
> b/arch/arm64/boot/dts/Makefile
> > index c52bdb051f66..f8001a62029c 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
> > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
> > dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
> >
> > diff --git a/arch/arm64/boot/dts/thunder-88xx.dts
> b/arch/arm64/boot/dts/thunder-88xx.dts
> > new file mode 100644
> > index 000000000000..4cf20ac9138b
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/thunder-88xx.dts
> > @@ -0,0 +1,387 @@
> > +/*
> > + * Cavium Thunder DTS file
> > + *
> > + * Copyright (C) 2013, Cavium Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + */
> > +/dts-v1/;
> > +
> > +/* Reserving first 12MB of DDR for firmware */
> > +/memreserve/ 0x00000000 0x00c00000;
>
> What exactly is this memreserve intended to protect at runtime?
> Yes, this 12 MB is reserved for ATF and UEFI boot and run-time services.
If booted as an EFI application Linux will use the UEFI memory map.
Anything UEFI needs to have kept around will be marked as such, so
there's no need to memreserve that.
I was under the impression that the ARM Trusted Firmware didn't need
anything resident on the non-secure side, so I don't see why that needs
a memreserve -- Linux should not be able to address anything it has
resident.
> The only item of runtime firmware I see in use below is PSCI on the
> secure side.
>
> How is the kernel booted on this platform? UEFI?
>
> Boot sequence tried is ATF->UEFI->Linux and ATF->UEFI->GRUB->Linux
As I've just had it explained to me, in either of those cases we should
enter Linux via the EFI stub. So we should be using the UEFI memory map
regardless.
Thanks,
Mark.
On Wednesday 30 July 2014, Robert Richter wrote:
> +/*
> + * Cavium Thunder DTS file
> + *
> + * Copyright (C) 2013, Cavium Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
I think it makes sense to use a permissive license for these files here,
since board vendors may want to include a copy of the binary in their
firmware, which isn't necessarily GPL compatible.
What is Cavium's interest in making this GPL?
Arnd
Rob and Arnd,
On 30.07.14 11:37:38, Rob Herring wrote:
> >> +/*
> >> + * Cavium Thunder DTS file
> >> + *
> >> + * Copyright (C) 2013, Cavium Inc.
> >> + *
> >> + * This program is free software; you can redistribute it and/or
> >> + * modify it under the terms of the GNU General Public License as
> >> + * published by the Free Software Foundation; either version 2 of
> >> + * the License, or (at your option) any later version.
> >> + */
>
> You may want to reconsider if this should be BSD.
I understand that this is an issue for the inclusion in firmware
binaries. Though, we just followed common practice here which is
gplv2.
I looked through existing dts files in arch/arm*/dts/* and about 590
of 720 have a gplv2 statement in. The other files don't have any and
thus following the COPYING file which is gplv2 too.
It is my understanding that the kernel requires licensing under gplv2.
So an option would be to dual license the dts file, e.g. with BSD. How
is this typically handled? Are there other repositories where dts
files are included with a different license model than gplv2?
Thanks,
-Robert
Please send plain text rather than HTML email; this is becoming painful
to reply to.
On Thu, Jul 31, 2014 at 12:12:33PM +0100, Ganapatrao Kulkarni wrote:
> On Thu, Jul 31, 2014 at 3:23 PM, Mark Rutland <[1][email protected]>
> wrote:
>
> On Thu, Jul 31, 2014 at 09:41:10AM +0100, Ganapatrao Kulkarni wrote:
> > On Wed, Jul 30, 2014 at 9:16 PM, Mark Rutland
> <[1][2][email protected]>
> > wrote:
> >
> > Hi,
> > On Wed, Jul 30, 2014 at 04:06:31PM +0100, Robert Richter wrote:
> > > From: Radha Mohan Chintakuntla <[2][3][email protected]>
> > >
> > > Add initial device tree nodes for Cavium Thunder SoCs with
> support of
> > > 48 cores and gicv3. The dts file requires further changes, esp.
> for
> > > pci, gicv3-its and smmu. This changes will be added later
> together
> > > with the device drivers.
> > >
> > > Signed-off-by: Radha Mohan Chintakuntla
> <[3][4][email protected]>
> > > Signed-off-by: Robert Richter <[4][5][email protected]>
> > > ---
> > > arch/arm64/boot/dts/Makefile | 1 +
> > > arch/arm64/boot/dts/thunder-88xx.dts | 387
> > +++++++++++++++++++++++++++++++++++
> > > 2 files changed, 388 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/thunder-88xx.dts
> > >
> > > diff --git a/arch/arm64/boot/dts/Makefile
> > b/arch/arm64/boot/dts/Makefile
> > > index c52bdb051f66..f8001a62029c 100644
> > > --- a/arch/arm64/boot/dts/Makefile
> > > +++ b/arch/arm64/boot/dts/Makefile
> > > @@ -1,3 +1,4 @@
> > > +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
> > > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
> foundation-v8.dtb
> > > dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
> > >
> > > diff --git a/arch/arm64/boot/dts/thunder-88xx.dts
> > b/arch/arm64/boot/dts/thunder-88xx.dts
> > > new file mode 100644
> > > index 000000000000..4cf20ac9138b
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/thunder-88xx.dts
> > > @@ -0,0 +1,387 @@
> > > +/*
> > > + * Cavium Thunder DTS file
> > > + *
> > > + * Copyright (C) 2013, Cavium Inc.
> > > + *
> > > + * This program is free software; you can redistribute it
> and/or
> > > + * modify it under the terms of the GNU General Public License
> as
> > > + * published by the Free Software Foundation; either version 2
> of
> > > + * the License, or (at your option) any later version.
> > > + */
> > > +/dts-v1/;
> > > +
> > > +/* Reserving first 12MB of DDR for firmware */
> > > +/memreserve/ 0x00000000 0x00c00000;
> >
> > What exactly is this memreserve intended to protect at runtime?
> > Yes, this 12 MB is reserved for ATF and UEFI boot and run-time
> services.
>
> If booted as an EFI application Linux will use the UEFI memory map.
> Anything UEFI needs to have kept around will be marked as such, so
> there's no need to memreserve that.
>
> We are loading ATF and UEFI from flash(which is not XIP) within 12MB of
> DDR.
> I dont see UEFI stub freeing RAM address where UEFI image is loaded.
Therefore we don't need the memreserve, then?
> I was under the impression that the ARM Trusted Firmware didn't need
> anything resident on the non-secure side, so I don't see why that needs
> a memreserve -- Linux should not be able to address anything it has
> resident.
>
> We mark RAM used by ATF as secure-RAM, however we don't support
> secure/non-secure address aliasing.
> i.e, a DRAM address that can be referenced from both a secure PA and a
> non-secure PA is not allowed.
What exactly do you mean by "not allowed"?
If Linux maps that memory, what happens?
What if Linux tried to read or write to it?
If Linux should not map that memory, it should not be described in the
memory map to begin with.
Thanks,
Mark.
On 31.07.14 12:24:13, Arnd Bergmann wrote:
> On Wednesday 30 July 2014, Robert Richter wrote:
> > +/*
> > + * Cavium Thunder DTS file
> > + *
> > + * Copyright (C) 2013, Cavium Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + */
>
> I think it makes sense to use a permissive license for these files here,
> since board vendors may want to include a copy of the binary in their
> firmware, which isn't necessarily GPL compatible.
>
> What is Cavium's interest in making this GPL?
See my response to Rob's mail on this.
-Robert
On 30.07.14 11:37:38, Rob Herring wrote:
> On Wed, Jul 30, 2014 at 10:46 AM, Mark Rutland <[email protected]> wrote:
> > On Wed, Jul 30, 2014 at 04:06:31PM +0100, Robert Richter wrote:
> >> From: Radha Mohan Chintakuntla <[email protected]>
> >> +/ {
> >> + model = "Cavium ThunderX CN88XX Family";
> >> + compatible = "cavium,thunder-88xx";
> >
> > Please don't use wildcards in compatible strings. Give this an absolute
> > name, and override as necessary.
The naming 88xx refers to the processor family and arn't actually
wildcards. In the future we might need another dts file for 87xx, but
so far all SoCs of 88xx family should use the same dts files. In this
sense the naming is very specific.
> >> + cpus {
> >> + #address-cells = <2>;
> >> + #size-cells = <0>;
> >> +
> >> + cpu@000 {
> >> + device_type = "cpu";
> >> + compatible = "cavium,thunder", "arm,armv8";
> >> + reg = <0x0 0x000>;
> >> + enable-method = "psci";
> >> + };
> >
> > Just to check: both the SoC and CPU are called thunder?
The soc is called thunder-88xx, the cpu thunder. E.g. an 87xx soc will
have the same core in which is thunder.
> >> + memory@00000000 {
> >> + device_type = "memory";
> >> + reg = <0x0 0x00000000 0x0 0x80000000>;
> >> + };
> >> +
> >> + gic0: interrupt-controller@801000000000 {
> >
> > To make this easier to read, please place a comma between 32-bit
> > portions of the unit address (e.g. here have 8010,00000000).
Changed this.
>
> Mark, perhaps a dtc or checkpatch.pl check for this?
>
> This should also be under a bus node.
Will do.
>
> >> + compatible = "arm,gic-v3";
> >> + #interrupt-cells = <3>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges;
> >
> > This has no children, so why have ranges, #address-cells, and
> > #size-cells?
Right, this is a leftover from a change in a follow on patch that
introduces a child for its. Will remove #address-cells, #size-cells
and ranges in this patch and move the change to the later patch.
> >
> >> + interrupt-controller;
> >> + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
> >> + <0x8010 0x80000000 0x0 0x200000>; /* GICR */
> >> + interrupts = <1 9 0xf04>;
> >> + };
> >> + clocks {
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges;
> >> +
> >> + refclk50mhz: refclk50mhz {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + clock-frequency = <50000000>;
> >> + clock-output-names = "refclk50mhz";
> >> + };
> >> + };
> >
> > Please get rid of the clocks node and just put the clocks here.
Will do.
> >
> >> +
> >> + uaa0: serial@87e024000000 {
> >> + compatible = "arm,pl011", "arm,primecell";
> >> + reg = <0x87e0 0x24000000 0x0 0x1000>;
> >> + interrupts = <1 21 4>;
> >> + clocks = <&refclk50mhz>;
> >> + clock-names = "apb_pclk";
> >
> > Is this actually the apb_pclk, or is the the uartclk? I assume it's the
> > latter.
>
> Shouldn't new bindings have both clocks here? A single clock was a
> mistake I think (mine in fact).
Do you mean
clock-names = "uartclk", "apb_pclk";
here?
Thanks,
-Robert
On Thu, Jul 31, 2014 at 7:34 AM, Robert Richter <[email protected]> wrote:
> On 30.07.14 11:37:38, Rob Herring wrote:
>> On Wed, Jul 30, 2014 at 10:46 AM, Mark Rutland <[email protected]> wrote:
>> > On Wed, Jul 30, 2014 at 04:06:31PM +0100, Robert Richter wrote:
>> >> From: Radha Mohan Chintakuntla <[email protected]>
>
>> >> +/ {
>> >> + model = "Cavium ThunderX CN88XX Family";
>> >> + compatible = "cavium,thunder-88xx";
>> >
>> > Please don't use wildcards in compatible strings. Give this an absolute
>> > name, and override as necessary.
>
> The naming 88xx refers to the processor family and arn't actually
> wildcards. In the future we might need another dts file for 87xx, but
> so far all SoCs of 88xx family should use the same dts files. In this
> sense the naming is very specific.
Yes, but each implementation can have its own errata. You might not
need to distinguish them now, but you could in the future.
However, if the family is really all the same die and different parts
are just marketing, then the name is fine. Or if you can easily probe
the exact part and revision it's probably fine.
>
>
>> >> + cpus {
>> >> + #address-cells = <2>;
>> >> + #size-cells = <0>;
>> >> +
>> >> + cpu@000 {
>> >> + device_type = "cpu";
>> >> + compatible = "cavium,thunder", "arm,armv8";
>> >> + reg = <0x0 0x000>;
>> >> + enable-method = "psci";
>> >> + };
>> >
>> > Just to check: both the SoC and CPU are called thunder?
>
> The soc is called thunder-88xx, the cpu thunder. E.g. an 87xx soc will
> have the same core in which is thunder.
And the next version of the core would be called something else?
thunder-v2? lightning? As long as they are distinguishable they should
be fine.
Rob
>
>
>> >> + memory@00000000 {
>> >> + device_type = "memory";
>> >> + reg = <0x0 0x00000000 0x0 0x80000000>;
>> >> + };
>> >> +
>> >> + gic0: interrupt-controller@801000000000 {
>> >
>> > To make this easier to read, please place a comma between 32-bit
>> > portions of the unit address (e.g. here have 8010,00000000).
>
> Changed this.
>
>>
>> Mark, perhaps a dtc or checkpatch.pl check for this?
>>
>> This should also be under a bus node.
>
> Will do.
>
>>
>> >> + compatible = "arm,gic-v3";
>> >> + #interrupt-cells = <3>;
>> >> + #address-cells = <2>;
>> >> + #size-cells = <2>;
>> >> + ranges;
>> >
>> > This has no children, so why have ranges, #address-cells, and
>> > #size-cells?
>
> Right, this is a leftover from a change in a follow on patch that
> introduces a child for its. Will remove #address-cells, #size-cells
> and ranges in this patch and move the change to the later patch.
>
>> >
>> >> + interrupt-controller;
>> >> + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
>> >> + <0x8010 0x80000000 0x0 0x200000>; /* GICR */
>> >> + interrupts = <1 9 0xf04>;
>> >> + };
>
>> >> + clocks {
>> >> + #address-cells = <2>;
>> >> + #size-cells = <2>;
>> >> + ranges;
>> >> +
>> >> + refclk50mhz: refclk50mhz {
>> >> + compatible = "fixed-clock";
>> >> + #clock-cells = <0>;
>> >> + clock-frequency = <50000000>;
>> >> + clock-output-names = "refclk50mhz";
>> >> + };
>> >> + };
>> >
>> > Please get rid of the clocks node and just put the clocks here.
>
> Will do.
>
>> >
>> >> +
>> >> + uaa0: serial@87e024000000 {
>> >> + compatible = "arm,pl011", "arm,primecell";
>> >> + reg = <0x87e0 0x24000000 0x0 0x1000>;
>> >> + interrupts = <1 21 4>;
>> >> + clocks = <&refclk50mhz>;
>> >> + clock-names = "apb_pclk";
>> >
>> > Is this actually the apb_pclk, or is the the uartclk? I assume it's the
>> > latter.
>>
>> Shouldn't new bindings have both clocks here? A single clock was a
>> mistake I think (mine in fact).
>
> Do you mean
> clock-names = "uartclk", "apb_pclk";
> here?
Yes, but Mark said this change never happened so maybe it is fine. In
any case, follow the pl011 binding documentation.
Rob
On 31.07.14 10:22:19, Rob Herring wrote:
> On Thu, Jul 31, 2014 at 7:34 AM, Robert Richter <[email protected]> wrote:
> > On 30.07.14 11:37:38, Rob Herring wrote:
> >> On Wed, Jul 30, 2014 at 10:46 AM, Mark Rutland <[email protected]> wrote:
> >> > On Wed, Jul 30, 2014 at 04:06:31PM +0100, Robert Richter wrote:
> >> >> From: Radha Mohan Chintakuntla <[email protected]>
> >
> >> >> +/ {
> >> >> + model = "Cavium ThunderX CN88XX Family";
> >> >> + compatible = "cavium,thunder-88xx";
> >> >
> >> > Please don't use wildcards in compatible strings. Give this an absolute
> >> > name, and override as necessary.
> >
> > The naming 88xx refers to the processor family and arn't actually
> > wildcards. In the future we might need another dts file for 87xx, but
> > so far all SoCs of 88xx family should use the same dts files. In this
> > sense the naming is very specific.
>
> Yes, but each implementation can have its own errata. You might not
> need to distinguish them now, but you could in the future.
>
> However, if the family is really all the same die and different parts
> are just marketing, then the name is fine. Or if you can easily probe
> the exact part and revision it's probably fine.
Yes, this relates to the same soc.
>
> >
> >
> >> >> + cpus {
> >> >> + #address-cells = <2>;
> >> >> + #size-cells = <0>;
> >> >> +
> >> >> + cpu@000 {
> >> >> + device_type = "cpu";
> >> >> + compatible = "cavium,thunder", "arm,armv8";
> >> >> + reg = <0x0 0x000>;
> >> >> + enable-method = "psci";
> >> >> + };
> >> >
> >> > Just to check: both the SoC and CPU are called thunder?
> >
> > The soc is called thunder-88xx, the cpu thunder. E.g. an 87xx soc will
> > have the same core in which is thunder.
>
> And the next version of the core would be called something else?
> thunder-v2? lightning? As long as they are distinguishable they should
> be fine.
Same here, the name relates to the same core.
-Robert