Add binding documentation for the MT8167 SoC. The SoC needs
an additional clock compared to the already supported SoC: mipi26m.
Signed-off-by: Fabien Parent <[email protected]>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..10ae6be7225e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,12 +7,13 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
+- clock-names: must contain "engine", "digital", "hs"
+ Can optionnally also contain "mipi26m"
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy"
- port: Output port node with endpoint definitions as described in
@@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
Hi Chun-Kuang,
On Wed, Oct 21, 2020 at 7:01 PM Chun-Kuang Hu <[email protected]> wrote:
>
> Hi, Fabien:
>
> Fabien Parent <[email protected]> 於 2020年10月21日 週三 上午1:43寫道：
> >
> > Add binding documentation for the MT8167 SoC. The SoC needs
> > an additional clock compared to the already supported SoC: mipi26m.
> >
> > Signed-off-by: Fabien Parent <[email protected]>
> > ---
> > .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > index f06f24d405a5..10ae6be7225e 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > @@ -7,12 +7,13 @@ channel output.
> >
> > Required properties:
> > - compatible: "mediatek,<chip>-dsi"
> > -- the supported chips are mt2701, mt7623, mt8173 and mt8183.
> > +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> > - reg: Physical base address and length of the controller's registers
> > - interrupts: The interrupt signal from the function block.
> > - clocks: device clocks
> > See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> > -- clock-names: must contain "engine", "digital", and "hs"
> > +- clock-names: must contain "engine", "digital", "hs"
> > + Can optionnally also contain "mipi26m"
>
> It seems that mipi26m is the clock of mipi-tx. In mt8173.dtsi [1],
> mipi-tx's clock is 26m.
>
> mipi_tx0: mipi-dphy@10215000 {
> compatible = "mediatek,mt8173-mipi-tx";
> reg = <0 0x10215000 0 0x1000>;
> clocks = <&clk26m>;
> clock-output-names = "mipi_tx0_pll";
> #clock-cells = <0>;
> #phy-cells = <0>;
> status = "disabled";
> };
>
> If this is the clock of mipi-tx, it should be controlled by mipi-tx driver.
Thanks, I will fix that in v2.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.9
>
> Regards,
> Chun-Kuang.
>
> > - phys: phandle link to the MIPI D-PHY controller.
> > - phy-names: must contain "dphy"
> > - port: Output port node with endpoint definitions as described in
> > @@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
> >
> > Required properties:
> > - compatible: "mediatek,<chip>-mipi-tx"
> > -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> > +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
> > - reg: Physical base address and length of the controller's registers
> > - clocks: PLL reference clock
> > - clock-output-names: name of the output clock line to the DSI encoder
> > --
> > 2.28.0
> >
Hi, Fabien:
Fabien Parent <[email protected]> 於 2020年10月21日 週三 上午1:43寫道：
>
> Add binding documentation for the MT8167 SoC. The SoC needs
> an additional clock compared to the already supported SoC: mipi26m.
>
> Signed-off-by: Fabien Parent <[email protected]>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> index f06f24d405a5..10ae6be7225e 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> @@ -7,12 +7,13 @@ channel output.
>
> Required properties:
> - compatible: "mediatek,<chip>-dsi"
> -- the supported chips are mt2701, mt7623, mt8173 and mt8183.
> +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - interrupts: The interrupt signal from the function block.
> - clocks: device clocks
> See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> -- clock-names: must contain "engine", "digital", and "hs"
> +- clock-names: must contain "engine", "digital", "hs"
> + Can optionnally also contain "mipi26m"
It seems that mipi26m is the clock of mipi-tx. In mt8173.dtsi [1],
mipi-tx's clock is 26m.
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
If this is the clock of mipi-tx, it should be controlled by mipi-tx driver.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.9
Regards,
Chun-Kuang.
> - phys: phandle link to the MIPI D-PHY controller.
> - phy-names: must contain "dphy"
> - port: Output port node with endpoint definitions as described in
> @@ -26,7 +27,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
>
> Required properties:
> - compatible: "mediatek,<chip>-mipi-tx"
> -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - clocks: PLL reference clock
> - clock-output-names: name of the output clock line to the DSI encoder
> --
> 2.28.0
>