On Tue, 14 Nov 2023 at 11:23, Sai Krishna Potthuri
<[email protected]> wrote:
>
> From: Swati Agarwal <[email protected]>
>
> Add gate property in example node for Xilinx platforms which will be used
> to ungate the DLL clock. DLL clock is required for higher frequencies like
> 50MHz, 100MHz and 200MHz.
> DLL clock is automatically selected by the SD controller when the SD
> output clock frequency is more than 25 MHz.
>
> Signed-off-by: Swati Agarwal <[email protected]>
> Co-developed-by: Sai Krishna Potthuri <[email protected]>
> Signed-off-by: Sai Krishna Potthuri <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Note: This patch only updates the example nodes with the gate property for
> Xilinx platforms.
>
> Changes in v2:
> - Updated subject prefix to match with the subsystem.
>
> Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> index 3e99801f77d2..9075add020bf 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> @@ -226,8 +226,8 @@ examples:
> interrupt-parent = <&gic>;
> interrupts = <0 48 4>;
> reg = <0xff160000 0x1000>;
> - clocks = <&clk200>, <&clk200>;
> - clock-names = "clk_xin", "clk_ahb";
> + clocks = <&clk200>, <&clk200>, <&clk1200>;
> + clock-names = "clk_xin", "clk_ahb", "gate";
> clock-output-names = "clk_out_sd0", "clk_in_sd0";
> #clock-cells = <1>;
> clk-phase-sd-hs = <63>, <72>;
> @@ -239,8 +239,8 @@ examples:
> interrupt-parent = <&gic>;
> interrupts = <0 126 4>;
> reg = <0xf1040000 0x10000>;
> - clocks = <&clk200>, <&clk200>;
> - clock-names = "clk_xin", "clk_ahb";
> + clocks = <&clk200>, <&clk200>, <&clk1200>;
> + clock-names = "clk_xin", "clk_ahb", "gate";
> clock-output-names = "clk_out_sd0", "clk_in_sd0";
> #clock-cells = <1>;
> clk-phase-sd-hs = <132>, <60>;
> --
> 2.25.1
>