Depends on the simple cleanup patches from:
https://lore.kernel.org/linux-spi/[email protected]/
A slightly different version of the google,gs101-spi support was sent at:
https://lore.kernel.org/linux-spi/[email protected]/
Let's add support for gs101-spi so that I have a testing base for the
driver rework patches that will follow.
Tudor Ambarus (4):
spi: s3c64xx: explicitly include <linux/types.h>
spi: dt-bindings: samsung: add google,gs101-spi compatible
spi: s3c64xx: add s3c64xx_iowrite{8,16}_32_rep accessors
spi: s3c64xx: add support for google,gs101-spi
.../devicetree/bindings/spi/samsung,spi.yaml | 1 +
drivers/spi/spi-s3c64xx.c | 89 +++++++++++++++----
2 files changed, 75 insertions(+), 15 deletions(-)
--
2.43.0.594.gd9cf4e227d-goog
Add "google,gs101-spi" dedicated compatible for representing SPI of
Google GS101 SoC.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Andi Shyti <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
index f71099852653..2f0a0835ecfb 100644
--- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml
+++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
oneOf:
- enum:
+ - google,gs101-spi
- samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
- samsung,s3c6410-spi
- samsung,s5pv210-spi # for S5PV210 and S5PC110
--
2.43.0.594.gd9cf4e227d-goog
Allow SoCs that require 32 bits register accesses to write data in
chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses
is the google gs101. The operation is rare, thus open code it in the
driver rather than making it generic (through asm-generic/io.h)
Signed-off-by: Tudor Ambarus <[email protected]>
---
drivers/spi/spi-s3c64xx.c | 70 +++++++++++++++++++++++++++++++--------
1 file changed, 56 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index c15ca6a910dc..cb45ad615f3d 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -142,6 +142,7 @@ struct s3c64xx_spi_dma_data {
* prescaler unit.
* @clk_ioclk: True if clock is present on this device
* @has_loopback: True if loopback mode can be supported
+ * @use_32bit_io: True if the SoC allows just 32-bit register accesses.
*
* The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
* differ in some aspects such as the size of the fifo and spi bus clock
@@ -158,6 +159,7 @@ struct s3c64xx_spi_port_config {
bool clk_from_cmu;
bool clk_ioclk;
bool has_loopback;
+ bool use_32bit_io;
};
/**
@@ -412,6 +414,59 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
return false;
}
+static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr,
+ const void *buffer, unsigned int count)
+{
+ if (count) {
+ const u8 *buf = buffer;
+
+ do {
+ __raw_writel(*buf++, addr);
+ } while (--count);
+ }
+}
+
+static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr,
+ const void *buffer, unsigned int count)
+{
+ if (count) {
+ const u16 *buf = buffer;
+
+ do {
+ __raw_writel(*buf++, addr);
+ } while (--count);
+ }
+}
+
+static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd,
+ struct spi_transfer *xfer)
+{
+ void __iomem *regs = sdd->regs;
+
+ switch (sdd->cur_bpw) {
+ case 32:
+ iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
+ xfer->tx_buf, xfer->len / 4);
+ break;
+ case 16:
+ if (sdd->port_conf->use_32bit_io)
+ s3c64xx_iowrite16_32_rep(regs + S3C64XX_SPI_TX_DATA,
+ xfer->tx_buf, xfer->len / 2);
+ else
+ iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
+ xfer->tx_buf, xfer->len / 2);
+ break;
+ default:
+ if (sdd->port_conf->use_32bit_io)
+ s3c64xx_iowrite8_32_rep(regs + S3C64XX_SPI_TX_DATA,
+ xfer->tx_buf, xfer->len);
+ else
+ iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
+ xfer->tx_buf, xfer->len);
+ break;
+ }
+}
+
static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
struct spi_transfer *xfer, int dma_mode)
{
@@ -445,20 +500,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
} else {
- switch (sdd->cur_bpw) {
- case 32:
- iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
- xfer->tx_buf, xfer->len / 4);
- break;
- case 16:
- iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
- xfer->tx_buf, xfer->len / 2);
- break;
- default:
- iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
- xfer->tx_buf, xfer->len);
- break;
- }
+ s3c64xx_iowrite_rep(sdd, xfer);
}
}
--
2.43.0.594.gd9cf4e227d-goog
Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64
bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a
Serror Interrupt is raised. Do the write reg accesses in 32 bits.
Signed-off-by: Tudor Ambarus <[email protected]>
---
drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index cb45ad615f3d..9ad0d513fb30 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -19,7 +19,7 @@
#include <linux/spi/spi.h>
#include <linux/types.h>
-#define MAX_SPI_PORTS 12
+#define MAX_SPI_PORTS 16
#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
#define AUTOSUSPEND_TIMEOUT 2000
@@ -1538,6 +1538,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
};
+static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .clk_div = 4,
+ .high_speed = true,
+ .clk_from_cmu = true,
+ .has_loopback = true,
+ .use_32bit_io = true,
+ .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
+};
+
static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
{
.name = "s3c2443-spi",
@@ -1550,6 +1563,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
};
static const struct of_device_id s3c64xx_spi_dt_match[] = {
+ { .compatible = "google,gs101-spi",
+ .data = &gs101_spi_port_config,
+ },
{ .compatible = "samsung,s3c2443-spi",
.data = &s3c2443_spi_port_config,
},
--
2.43.0.594.gd9cf4e227d-goog
On Tue, 6 Feb 2024 at 08:52, Tudor Ambarus <[email protected]> wrote:
>
> Add "google,gs101-spi" dedicated compatible for representing SPI of
> Google GS101 SoC.
>
> Reviewed-by: Sam Protsenko <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Acked-by: Andi Shyti <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Peter Griffin <[email protected]>
> Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
> index f71099852653..2f0a0835ecfb 100644
> --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml
> @@ -17,6 +17,7 @@ properties:
> compatible:
> oneOf:
> - enum:
> + - google,gs101-spi
> - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
> - samsung,s3c6410-spi
> - samsung,s5pv210-spi # for S5PV210 and S5PC110
> --
> 2.43.0.594.gd9cf4e227d-goog
>
Hi Tudor,
On Tue, 6 Feb 2024 at 08:52, Tudor Ambarus <[email protected]> wrote:
>
> Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64
> bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a
> Serror Interrupt is raised. Do the write reg accesses in 32 bits.
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
The patch ordering seems a bit off with this series..I believe it should be
1) dt-bindings patch (docs first)
2) Add the use_32bit_io flag / functionality
3) gs101 support (this patch) that uses the use_32bit_io functionality
Peter.
> drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index cb45ad615f3d..9ad0d513fb30 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -19,7 +19,7 @@
> #include <linux/spi/spi.h>
> #include <linux/types.h>
>
> -#define MAX_SPI_PORTS 12
> +#define MAX_SPI_PORTS 16
> #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
> #define AUTOSUSPEND_TIMEOUT 2000
>
> @@ -1538,6 +1538,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
> .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> };
>
> +static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
> + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .clk_div = 4,
> + .high_speed = true,
> + .clk_from_cmu = true,
> + .has_loopback = true,
> + .use_32bit_io = true,
> + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> +};
> +
> static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
> {
> .name = "s3c2443-spi",
> @@ -1550,6 +1563,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
> };
>
> static const struct of_device_id s3c64xx_spi_dt_match[] = {
> + { .compatible = "google,gs101-spi",
> + .data = &gs101_spi_port_config,
> + },
> { .compatible = "samsung,s3c2443-spi",
> .data = &s3c2443_spi_port_config,
> },
> --
> 2.43.0.594.gd9cf4e227d-goog
>
On Tue, Feb 06, 2024 at 10:12:30AM +0000, Peter Griffin wrote:
> The patch ordering seems a bit off with this series..I believe it should be
> 1) dt-bindings patch (docs first)
> 2) Add the use_32bit_io flag / functionality
> 3) gs101 support (this patch) that uses the use_32bit_io functionality
That's the ordering the series has? There's a random cleanup patch
tacked on the front but that really ought to be separate anyway.
On 2/6/24 11:04, Mark Brown wrote:
> On Tue, Feb 06, 2024 at 10:12:30AM +0000, Peter Griffin wrote:
>
>> The patch ordering seems a bit off with this series..I believe it should be
>> 1) dt-bindings patch (docs first)
>> 2) Add the use_32bit_io flag / functionality
>> 3) gs101 support (this patch) that uses the use_32bit_io functionality
>
> That's the ordering the series has? There's a random cleanup patch
> tacked on the front but that really ought to be separate anyway.
I put the include <linux/types.h> patch first because I considered it a
fix (driver is using u32) and because I need types.h in patch 3/4. Fixes
first, then bindings, then driver.
Was I wrong?
On Tue, 6 Feb 2024 at 11:19, Tudor Ambarus <[email protected]> wrote:
>
>
>
> On 2/6/24 11:04, Mark Brown wrote:
> > On Tue, Feb 06, 2024 at 10:12:30AM +0000, Peter Griffin wrote:
> >
> >> The patch ordering seems a bit off with this series..I believe it should be
> >> 1) dt-bindings patch (docs first)
> >> 2) Add the use_32bit_io flag / functionality
> >> 3) gs101 support (this patch) that uses the use_32bit_io functionality
> >
> > That's the ordering the series has? There's a random cleanup patch
> > tacked on the front but that really ought to be separate anyway.
>
> I put the include <linux/types.h> patch first because I considered it a
> fix (driver is using u32) and because I need types.h in patch 3/4. Fixes
> first, then bindings, then driver.
>
> Was I wrong?
No my mistake, sorry for the noise. Gmail showed this driver change as
the first patch after the cover letter but the subject was hidden so
it wasn't obvious it was [4/4]
On Tue, Feb 6, 2024 at 2:52 AM Tudor Ambarus <[email protected]> wrote:
>
> Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64
> bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a
> Serror Interrupt is raised. Do the write reg accesses in 32 bits.
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index cb45ad615f3d..9ad0d513fb30 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -19,7 +19,7 @@
> #include <linux/spi/spi.h>
> #include <linux/types.h>
>
> -#define MAX_SPI_PORTS 12
> +#define MAX_SPI_PORTS 16
> #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
> #define AUTOSUSPEND_TIMEOUT 2000
>
> @@ -1538,6 +1538,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
> .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> };
>
> +static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
> + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .clk_div = 4,
> + .high_speed = true,
> + .clk_from_cmu = true,
> + .has_loopback = true,
> + .use_32bit_io = true,
> + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> +};
> +
> static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
> {
> .name = "s3c2443-spi",
> @@ -1550,6 +1563,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
> };
>
> static const struct of_device_id s3c64xx_spi_dt_match[] = {
> + { .compatible = "google,gs101-spi",
> + .data = &gs101_spi_port_config,
> + },
> { .compatible = "samsung,s3c2443-spi",
> .data = &s3c2443_spi_port_config,
> },
> --
> 2.43.0.594.gd9cf4e227d-goog
>
On Tue, Feb 6, 2024 at 2:52 AM Tudor Ambarus <[email protected]> wrote:
>
> Depends on the simple cleanup patches from:
> https://lore.kernel.org/linux-spi/[email protected]/
>
> A slightly different version of the google,gs101-spi support was sent at:
> https://lore.kernel.org/linux-spi/[email protected]/
>
> Let's add support for gs101-spi so that I have a testing base for the
> driver rework patches that will follow.
>
> Tudor Ambarus (4):
> spi: s3c64xx: explicitly include <linux/types.h>
> spi: dt-bindings: samsung: add google,gs101-spi compatible
> spi: s3c64xx: add s3c64xx_iowrite{8,16}_32_rep accessors
> spi: s3c64xx: add support for google,gs101-spi
>
Just a grumpy note: I wish this series (except for the [PATCH 1/4],
which I'd argue doesn't belong here) was submitted before the rest of
SPI cleanups and reworkings. Would've made reviewing much easier,
because this series doesn't apply without SPI cleanup series that has
to be applied prior to that. There are other benefits to that approach
too, as was discussed earlier.
> .../devicetree/bindings/spi/samsung,spi.yaml | 1 +
> drivers/spi/spi-s3c64xx.c | 89 +++++++++++++++----
> 2 files changed, 75 insertions(+), 15 deletions(-)
>
> --
> 2.43.0.594.gd9cf4e227d-goog
>
On Tue, Feb 6, 2024 at 2:52 AM Tudor Ambarus <[email protected]> wrote:
>
> Allow SoCs that require 32 bits register accesses to write data in
> chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses
> is the google gs101. The operation is rare, thus open code it in the
> driver rather than making it generic (through asm-generic/io.h)
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> drivers/spi/spi-s3c64xx.c | 70 +++++++++++++++++++++++++++++++--------
> 1 file changed, 56 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index c15ca6a910dc..cb45ad615f3d 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -142,6 +142,7 @@ struct s3c64xx_spi_dma_data {
> * prescaler unit.
> * @clk_ioclk: True if clock is present on this device
> * @has_loopback: True if loopback mode can be supported
> + * @use_32bit_io: True if the SoC allows just 32-bit register accesses.
A matter of taste, but: just -> only.
> *
> * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
> * differ in some aspects such as the size of the fifo and spi bus clock
> @@ -158,6 +159,7 @@ struct s3c64xx_spi_port_config {
> bool clk_from_cmu;
> bool clk_ioclk;
> bool has_loopback;
> + bool use_32bit_io;
> };
>
> /**
> @@ -412,6 +414,59 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
> return false;
> }
>
> +static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr,
> + const void *buffer, unsigned int count)
> +{
> + if (count) {
> + const u8 *buf = buffer;
> +
> + do {
> + __raw_writel(*buf++, addr);
> + } while (--count);
> + }
How about:
while (count--)
__raw_writel(*buf++, addr);
This way "if" condition is not needed. The same goes for the function below.
> +}
> +
> +static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr,
> + const void *buffer, unsigned int count)
> +{
> + if (count) {
> + const u16 *buf = buffer;
> +
> + do {
> + __raw_writel(*buf++, addr);
> + } while (--count);
> + }
> +}
> +
> +static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd,
> + struct spi_transfer *xfer)
> +{
> + void __iomem *regs = sdd->regs;
Suggest declaring aliases here, like this:
void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA;
const void *buf = xfer->tx_buf;
unsigned int len = xfer->len;
Using those in the code below makes it more compact and easier to read.
> +
> + switch (sdd->cur_bpw) {
> + case 32:
> + iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
> + xfer->tx_buf, xfer->len / 4);
> + break;
> + case 16:
> + if (sdd->port_conf->use_32bit_io)
> + s3c64xx_iowrite16_32_rep(regs + S3C64XX_SPI_TX_DATA,
> + xfer->tx_buf, xfer->len / 2);
> + else
> + iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
> + xfer->tx_buf, xfer->len / 2);
> + break;
> + default:
> + if (sdd->port_conf->use_32bit_io)
> + s3c64xx_iowrite8_32_rep(regs + S3C64XX_SPI_TX_DATA,
> + xfer->tx_buf, xfer->len);
> + else
> + iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
> + xfer->tx_buf, xfer->len);
> + break;
> + }
> +}
> +
> static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
> struct spi_transfer *xfer, int dma_mode)
> {
> @@ -445,20 +500,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
> modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
> ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
> } else {
> - switch (sdd->cur_bpw) {
> - case 32:
> - iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
> - xfer->tx_buf, xfer->len / 4);
> - break;
> - case 16:
> - iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
> - xfer->tx_buf, xfer->len / 2);
> - break;
> - default:
> - iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
> - xfer->tx_buf, xfer->len);
> - break;
> - }
> + s3c64xx_iowrite_rep(sdd, xfer);
This extraction (with no functional change yet) could've been a
preceding separate patch, preparing things for this rework.
> }
> }
>
> --
> 2.43.0.594.gd9cf4e227d-goog
>
On 2/6/24 18:44, Sam Protsenko wrote:
> On Tue, Feb 6, 2024 at 2:52 AM Tudor Ambarus <[email protected]> wrote:
>>
>> Allow SoCs that require 32 bits register accesses to write data in
>> chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses
>> is the google gs101. The operation is rare, thus open code it in the
>> driver rather than making it generic (through asm-generic/io.h)
>>
>> Signed-off-by: Tudor Ambarus <[email protected]>
>> ---
>> drivers/spi/spi-s3c64xx.c | 70 +++++++++++++++++++++++++++++++--------
>> 1 file changed, 56 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
>> index c15ca6a910dc..cb45ad615f3d 100644
>> --- a/drivers/spi/spi-s3c64xx.c
>> +++ b/drivers/spi/spi-s3c64xx.c
>> @@ -142,6 +142,7 @@ struct s3c64xx_spi_dma_data {
>> * prescaler unit.
>> * @clk_ioclk: True if clock is present on this device
>> * @has_loopback: True if loopback mode can be supported
>> + * @use_32bit_io: True if the SoC allows just 32-bit register accesses.
>
> A matter of taste, but: just -> only.
ok, will change if I send a new version.
>
>> *
>> * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
>> * differ in some aspects such as the size of the fifo and spi bus clock
>> @@ -158,6 +159,7 @@ struct s3c64xx_spi_port_config {
>> bool clk_from_cmu;
>> bool clk_ioclk;
>> bool has_loopback;
>> + bool use_32bit_io;
>> };
>>
>> /**
>> @@ -412,6 +414,59 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
>> return false;
>> }
>>
>> +static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr,
>> + const void *buffer, unsigned int count)
>> +{
>> + if (count) {
>> + const u8 *buf = buffer;
>> +
>> + do {
>> + __raw_writel(*buf++, addr);
>> + } while (--count);
>> + }
>
> How about:
>
> while (count--)
> __raw_writel(*buf++, addr);
>
> This way "if" condition is not needed. The same goes for the function below.
count will overflow, but shouldn't matter as it's not used afterwards.
But I would keep the style as it is, if you don't mind, it follows other
similar implementations from include/asm-generic/io.h. I'd like to be
consistent with the coding style of the generic implementations.
>
>> +}
>> +
>> +static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr,
>> + const void *buffer, unsigned int count)
>> +{
>> + if (count) {
>> + const u16 *buf = buffer;
>> +
>> + do {
>> + __raw_writel(*buf++, addr);
>> + } while (--count);
>> + }
>> +}
>> +
>> +static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd,
>> + struct spi_transfer *xfer)
>> +{
>> + void __iomem *regs = sdd->regs;
>
> Suggest declaring aliases here, like this:
>
> void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA;
> const void *buf = xfer->tx_buf;
> unsigned int len = xfer->len;
>
> Using those in the code below makes it more compact and easier to read.
Ok, will add the local variables if I send again. I hope you're fine
with adding the local variables when introducing the method.
>
>> +
>> + switch (sdd->cur_bpw) {
>> + case 32:
>> + iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
>> + xfer->tx_buf, xfer->len / 4);
>> + break;
>> + case 16:
>> + if (sdd->port_conf->use_32bit_io)
>> + s3c64xx_iowrite16_32_rep(regs + S3C64XX_SPI_TX_DATA,
>> + xfer->tx_buf, xfer->len / 2);
>> + else
>> + iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
>> + xfer->tx_buf, xfer->len / 2);
>> + break;
>> + default:
>> + if (sdd->port_conf->use_32bit_io)
>> + s3c64xx_iowrite8_32_rep(regs + S3C64XX_SPI_TX_DATA,
>> + xfer->tx_buf, xfer->len);
>> + else
>> + iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
>> + xfer->tx_buf, xfer->len);
>> + break;
>> + }
>> +}
>> +
>> static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
>> struct spi_transfer *xfer, int dma_mode)
>> {
>> @@ -445,20 +500,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
>> modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
>> ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
>> } else {
>> - switch (sdd->cur_bpw) {
>> - case 32:
>> - iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
>> - xfer->tx_buf, xfer->len / 4);
>> - break;
>> - case 16:
>> - iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
>> - xfer->tx_buf, xfer->len / 2);
>> - break;
>> - default:
>> - iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
>> - xfer->tx_buf, xfer->len);
>> - break;
>> - }
>> + s3c64xx_iowrite_rep(sdd, xfer);
>
> This extraction (with no functional change yet) could've been a
> preceding separate patch, preparing things for this rework.
>
I'm not a fan of having preparation patches for small changes like this,
it hides the scope. As the patch is now one can see that the logic
extends and would have made the indentation horrible if not introducing
a dedicated method. No preparation patch, please.
On 2/6/24 18:59, Sam Protsenko wrote:
> On Tue, Feb 6, 2024 at 2:52 AM Tudor Ambarus <[email protected]> wrote:
>>
>> Depends on the simple cleanup patches from:
>> https://lore.kernel.org/linux-spi/[email protected]/
>>
>> A slightly different version of the google,gs101-spi support was sent at:
>> https://lore.kernel.org/linux-spi/[email protected]/
>>
>> Let's add support for gs101-spi so that I have a testing base for the
>> driver rework patches that will follow.
>>
>> Tudor Ambarus (4):
>> spi: s3c64xx: explicitly include <linux/types.h>
>> spi: dt-bindings: samsung: add google,gs101-spi compatible
>> spi: s3c64xx: add s3c64xx_iowrite{8,16}_32_rep accessors
>> spi: s3c64xx: add support for google,gs101-spi
>>
>
> Just a grumpy note: I wish this series (except for the [PATCH 1/4],
> which I'd argue doesn't belong here) was submitted before the rest of
> SPI cleanups and reworkings. Would've made reviewing much easier,
> because this series doesn't apply without SPI cleanup series that has
> to be applied prior to that. There are other benefits to that approach
> too, as was discussed earlier.
>
I feel we're bike-shedding, it drains my energy. Your reasons were:
1/ easier review
2/ easier backporting of gs101 if that's ever wanted
3/ driver rework takes more review time and I risk not having gs101
integrated for next release
2/ is not true right now, I could cherry-pick the iowrite and gs101
patches on top of v6.7. With 1/ I don't agree as the gs101 patches are
the same with or without the simple cleanup.
3/ is my responsibility and I'm ok with it, I feel there's enough time
for all
What matters, as I specified in the cover letter, is to have the gs101
patches before the functional driver rework which will follow, so that I
can test each functional patch with gs101.
I give up however, I'll do as you want. Will respin all.