This patch series enables the Arm Statistical
Profiling Extension (SPE) on ACPI platforms.
This is possible because ACPI 6.3 uses a previously
reserved field in the MADT to store the SPE interrupt
number, similarly to how the normal PMU is
described. If a consistent valid interrupt exists
across all the cores in the system, a platform
device is registered. That then triggers the SPE module,
which runs as normal.
Jeremy Linton (3):
ACPICA: ACPI 6.3: Add MADT/GICC/SPE extension.
arm_pmu: acpi: spe: Add initial MADT/SPE probing
perf: arm_spe: Enable ACPI/Platform automatic module loading
arch/arm64/include/asm/acpi.h | 4 +++
drivers/perf/arm_pmu_acpi.c | 67 +++++++++++++++++++++++++++++++++++
drivers/perf/arm_spe_pmu.c | 11 ++++--
include/acpi/actbl2.h | 5 +--
4 files changed, 83 insertions(+), 4 deletions(-)
--
2.17.2
[Placeholder patch for upstream ACPICA commit]
Add just ACPI 6.3 changes associated with the arm64 SPE.
Signed-off-by: Jeremy Linton <[email protected]>
---
include/acpi/actbl2.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index c50ef7e6b942..4b58eb6cf64e 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -623,7 +623,7 @@ struct acpi_madt_local_x2apic_nmi {
u8 reserved[3]; /* reserved - must be zero */
};
-/* 11: Generic Interrupt (ACPI 5.0 + ACPI 6.0 changes) */
+/* 11: Generic Interrupt (ACPI 5.0 + 6.0 + 6.3 changes) */
struct acpi_madt_generic_interrupt {
struct acpi_subtable_header header;
@@ -641,7 +641,8 @@ struct acpi_madt_generic_interrupt {
u64 gicr_base_address;
u64 arm_mpidr;
u8 efficiency_class;
- u8 reserved2[3];
+ u8 reserved2;
+ u16 spe_overflow_interrupt;
};
/* Masks for Flags field above */
--
2.17.2
ACPI 6.3 adds additional fields to the MADT GICC
structure to describe SPE PPI's. We pick these out
of the cached reference to the madt_gicc structure
similarly to the core PMU code. We then create a platform
device referring to the IRQ and let the user/module loader
decide whether to load the SPE driver.
Signed-off-by: Jeremy Linton <[email protected]>
---
arch/arm64/include/asm/acpi.h | 3 ++
drivers/perf/arm_pmu_acpi.c | 67 +++++++++++++++++++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 2def77ec14be..f9f9f2eb5d54 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -40,6 +40,9 @@
(!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
(unsigned long)(entry) + (entry)->header.length > (end))
+#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \
+ spe_overflow_interrupt) + sizeof(u16))
+
/* Basic configuration for ACPI */
#ifdef CONFIG_ACPI
pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);
diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
index 0f197516d708..725d413b47dc 100644
--- a/drivers/perf/arm_pmu_acpi.c
+++ b/drivers/perf/arm_pmu_acpi.c
@@ -74,6 +74,71 @@ static void arm_pmu_acpi_unregister_irq(int cpu)
acpi_unregister_gsi(gsi);
}
+static struct resource spe_resources[] = {
+ {
+ /* irq */
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device spe_dev = {
+ .name = "arm,spe-v1",
+ .id = -1,
+ .resource = spe_resources,
+ .num_resources = ARRAY_SIZE(spe_resources)
+};
+
+/*
+ * For lack of a better place, hook the normal PMU MADT walk
+ * and create a SPE device if we detect a recent MADT with
+ * a homogeneous PPI mapping.
+ */
+static int arm_spe_acpi_parse_irqs(void)
+{
+ int cpu, ret, irq;
+ u16 gsi = 0;
+ bool first = true;
+
+ struct acpi_madt_generic_interrupt *gicc;
+
+ /*
+ * sanity check all the GICC tables for the same interrupt number
+ * for now we only support homogeneous ACPI/SPE machines.
+ */
+ for_each_possible_cpu(cpu) {
+ gicc = acpi_cpu_get_madt_gicc(cpu);
+
+ if (gicc->header.length < ACPI_MADT_GICC_SPE)
+ return -ENODEV;
+
+ if (first) {
+ gsi = gicc->spe_overflow_interrupt;
+ if (!gsi)
+ return -ENODEV;
+ first = false;
+ } else if (gsi != gicc->spe_overflow_interrupt) {
+ pr_warn("ACPI: SPE must have homogeneous interrupts\n");
+ return -EINVAL;
+ }
+ }
+
+ irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE,
+ ACPI_ACTIVE_HIGH);
+ if (irq < 0) {
+ pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi);
+ return irq;
+ }
+
+ spe_resources[0].start = irq;
+ ret = platform_device_register(&spe_dev);
+ if (ret < 0) {
+ pr_warn("ACPI: SPE: Unable to register device\n");
+ acpi_unregister_gsi(gsi);
+ }
+
+ return ret;
+}
+
static int arm_pmu_acpi_parse_irqs(void)
{
int irq, cpu, irq_cpu, err;
@@ -279,6 +344,8 @@ static int arm_pmu_acpi_init(void)
if (acpi_disabled)
return 0;
+ arm_spe_acpi_parse_irqs(); /* failures are expected */
+
ret = arm_pmu_acpi_parse_irqs();
if (ret)
return ret;
--
2.17.2
Lets add the MODULE_TABLE and platform id_table entries so that
the SPE driver can attach to the ACPI platform device created by
the core pmu code.
Signed-off-by: Jeremy Linton <[email protected]>
---
drivers/perf/arm_spe_pmu.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index 8e46a9dad2fa..9be11d814fa5 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -1176,7 +1176,13 @@ static const struct of_device_id arm_spe_pmu_of_match[] = {
};
MODULE_DEVICE_TABLE(of, arm_spe_pmu_of_match);
-static int arm_spe_pmu_device_dt_probe(struct platform_device *pdev)
+static const struct platform_device_id arm_spe_match[] = {
+ { "arm,spe-v1", 0},
+ { }
+};
+MODULE_DEVICE_TABLE(platform, arm_spe_match);
+
+static int arm_spe_pmu_device_probe(struct platform_device *pdev)
{
int ret;
struct arm_spe_pmu *spe_pmu;
@@ -1236,11 +1242,12 @@ static int arm_spe_pmu_device_remove(struct platform_device *pdev)
}
static struct platform_driver arm_spe_pmu_driver = {
+ .id_table = arm_spe_match,
.driver = {
.name = DRVNAME,
.of_match_table = of_match_ptr(arm_spe_pmu_of_match),
},
- .probe = arm_spe_pmu_device_dt_probe,
+ .probe = arm_spe_pmu_device_probe,
.remove = arm_spe_pmu_device_remove,
};
--
2.17.2
On Fri, Feb 08, 2019 at 06:47:18PM -0600, Jeremy Linton wrote:
> Lets add the MODULE_TABLE and platform id_table entries so that
> the SPE driver can attach to the ACPI platform device created by
> the core pmu code.
>
Reviewed-by: Sudeep Holla <[email protected]>
On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:
> ACPI 6.3 adds additional fields to the MADT GICC
> structure to describe SPE PPI's. We pick these out
> of the cached reference to the madt_gicc structure
> similarly to the core PMU code. We then create a platform
> device referring to the IRQ and let the user/module loader
> decide whether to load the SPE driver.
>
> Signed-off-by: Jeremy Linton <[email protected]>
> ---
> arch/arm64/include/asm/acpi.h | 3 ++
> drivers/perf/arm_pmu_acpi.c | 67 +++++++++++++++++++++++++++++++++++
> 2 files changed, 70 insertions(+)
>
> diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
> index 2def77ec14be..f9f9f2eb5d54 100644
> --- a/arch/arm64/include/asm/acpi.h
> +++ b/arch/arm64/include/asm/acpi.h
> @@ -40,6 +40,9 @@
> (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
> (unsigned long)(entry) + (entry)->header.length > (end))
>
> +#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \
> + spe_overflow_interrupt) + sizeof(u16))
> +
[Nit] Does it make sense to add _OFFSET in the name ? Otherwise it may
sound like the actual interrupt number than the offset.
Other than that, this looks good to me:
Reviewed-by: Sudeep Holla <[email protected]>
Regards,
Sudeep
> -----Original Message-----
> From: Jeremy Linton [mailto:[email protected]]
> Sent: Friday, February 8, 2019 4:47 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; Moore, Robert <[email protected]>;
> Schmauss, Erik <[email protected]>; Wysocki, Rafael J
> <[email protected]>; [email protected]; Jeremy Linton
> <[email protected]>
> Subject: [RFC 1/3] ACPICA: ACPI 6.3: Add MADT/GICC/SPE extension.
>
Hi Jeremy,
> [Placeholder patch for upstream ACPICA commit]
FYI: we are planning on releasing ACPICA patches by the end of this week at the latest.
Erik
>
> Add just ACPI 6.3 changes associated with the arm64 SPE.
>
> Signed-off-by: Jeremy Linton <[email protected]>
> ---
> include/acpi/actbl2.h | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index
> c50ef7e6b942..4b58eb6cf64e 100644
> --- a/include/acpi/actbl2.h
> +++ b/include/acpi/actbl2.h
> @@ -623,7 +623,7 @@ struct acpi_madt_local_x2apic_nmi {
> u8 reserved[3]; /* reserved - must be zero */
> };
>
> -/* 11: Generic Interrupt (ACPI 5.0 + ACPI 6.0 changes) */
> +/* 11: Generic Interrupt (ACPI 5.0 + 6.0 + 6.3 changes) */
>
> struct acpi_madt_generic_interrupt {
> struct acpi_subtable_header header;
> @@ -641,7 +641,8 @@ struct acpi_madt_generic_interrupt {
> u64 gicr_base_address;
> u64 arm_mpidr;
> u8 efficiency_class;
> - u8 reserved2[3];
> + u8 reserved2;
> + u16 spe_overflow_interrupt;
> };
>
> /* Masks for Flags field above */
> --
> 2.17.2
Hi Jeremy,
On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:
> ACPI 6.3 adds additional fields to the MADT GICC
> structure to describe SPE PPI's. We pick these out
> of the cached reference to the madt_gicc structure
> similarly to the core PMU code. We then create a platform
> device referring to the IRQ and let the user/module loader
> decide whether to load the SPE driver.
>
> Signed-off-by: Jeremy Linton <[email protected]>
> ---
> arch/arm64/include/asm/acpi.h | 3 ++
> drivers/perf/arm_pmu_acpi.c | 67 +++++++++++++++++++++++++++++++++++
> 2 files changed, 70 insertions(+)
>
> diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
> index 2def77ec14be..f9f9f2eb5d54 100644
> --- a/arch/arm64/include/asm/acpi.h
> +++ b/arch/arm64/include/asm/acpi.h
> @@ -40,6 +40,9 @@
> (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
> (unsigned long)(entry) + (entry)->header.length > (end))
>
> +#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \
> + spe_overflow_interrupt) + sizeof(u16))
> +
> /* Basic configuration for ACPI */
> #ifdef CONFIG_ACPI
> pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);
> diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
> index 0f197516d708..725d413b47dc 100644
> --- a/drivers/perf/arm_pmu_acpi.c
> +++ b/drivers/perf/arm_pmu_acpi.c
> @@ -74,6 +74,71 @@ static void arm_pmu_acpi_unregister_irq(int cpu)
> acpi_unregister_gsi(gsi);
> }
>
> +static struct resource spe_resources[] = {
> + {
> + /* irq */
> + .flags = IORESOURCE_IRQ,
> + }
> +};
> +
> +static struct platform_device spe_dev = {
> + .name = "arm,spe-v1",
> + .id = -1,
> + .resource = spe_resources,
> + .num_resources = ARRAY_SIZE(spe_resources)
> +};
> +
> +/*
> + * For lack of a better place, hook the normal PMU MADT walk
> + * and create a SPE device if we detect a recent MADT with
> + * a homogeneous PPI mapping.
> + */
> +static int arm_spe_acpi_parse_irqs(void)
> +{
> + int cpu, ret, irq;
> + u16 gsi = 0;
> + bool first = true;
> +
> + struct acpi_madt_generic_interrupt *gicc;
> +
> + /*
> + * sanity check all the GICC tables for the same interrupt number
> + * for now we only support homogeneous ACPI/SPE machines.
> + */
> + for_each_possible_cpu(cpu) {
> + gicc = acpi_cpu_get_madt_gicc(cpu);
> +
> + if (gicc->header.length < ACPI_MADT_GICC_SPE)
> + return -ENODEV;
> +
> + if (first) {
> + gsi = gicc->spe_overflow_interrupt;
> + if (!gsi)
> + return -ENODEV;
> + first = false;
> + } else if (gsi != gicc->spe_overflow_interrupt) {
> + pr_warn("ACPI: SPE must have homogeneous interrupts\n");
> + return -EINVAL;
> + }
Unfortunately, I don't think this is sufficient to detect a homogeneous
system: we'll have to check the MIDRs instead, which is nasty. I would
personally be in favour of enforcing homogeneity for ACPI systems when we
bring up secondary CPUs, but I suspect others would disagree.
Will
Hi,
Thanks for taking a look at this..
On 2/14/19 11:11 AM, Will Deacon wrote:
> Hi Jeremy,
>
> On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:
>> ACPI 6.3 adds additional fields to the MADT GICC
>> structure to describe SPE PPI's. We pick these out
>> of the cached reference to the madt_gicc structure
>> similarly to the core PMU code. We then create a platform
>> device referring to the IRQ and let the user/module loader
>> decide whether to load the SPE driver.
>>
>> Signed-off-by: Jeremy Linton <[email protected]>
>> ---
>> arch/arm64/include/asm/acpi.h | 3 ++
>> drivers/perf/arm_pmu_acpi.c | 67 +++++++++++++++++++++++++++++++++++
>> 2 files changed, 70 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
>> index 2def77ec14be..f9f9f2eb5d54 100644
>> --- a/arch/arm64/include/asm/acpi.h
>> +++ b/arch/arm64/include/asm/acpi.h
>> @@ -40,6 +40,9 @@
>> (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
>> (unsigned long)(entry) + (entry)->header.length > (end))
>>
>> +#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \
>> + spe_overflow_interrupt) + sizeof(u16))
>> +
>> /* Basic configuration for ACPI */
>> #ifdef CONFIG_ACPI
>> pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);
>> diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
>> index 0f197516d708..725d413b47dc 100644
>> --- a/drivers/perf/arm_pmu_acpi.c
>> +++ b/drivers/perf/arm_pmu_acpi.c
>> @@ -74,6 +74,71 @@ static void arm_pmu_acpi_unregister_irq(int cpu)
>> acpi_unregister_gsi(gsi);
>> }
>>
>> +static struct resource spe_resources[] = {
>> + {
>> + /* irq */
>> + .flags = IORESOURCE_IRQ,
>> + }
>> +};
>> +
>> +static struct platform_device spe_dev = {
>> + .name = "arm,spe-v1",
>> + .id = -1,
>> + .resource = spe_resources,
>> + .num_resources = ARRAY_SIZE(spe_resources)
>> +};
>> +
>> +/*
>> + * For lack of a better place, hook the normal PMU MADT walk
>> + * and create a SPE device if we detect a recent MADT with
>> + * a homogeneous PPI mapping.
>> + */
>> +static int arm_spe_acpi_parse_irqs(void)
>> +{
>> + int cpu, ret, irq;
>> + u16 gsi = 0;
>> + bool first = true;
>> +
>> + struct acpi_madt_generic_interrupt *gicc;
>> +
>> + /*
>> + * sanity check all the GICC tables for the same interrupt number
>> + * for now we only support homogeneous ACPI/SPE machines.
>> + */
>> + for_each_possible_cpu(cpu) {
>> + gicc = acpi_cpu_get_madt_gicc(cpu);
>> +
>> + if (gicc->header.length < ACPI_MADT_GICC_SPE)
>> + return -ENODEV;
>> +
>> + if (first) {
>> + gsi = gicc->spe_overflow_interrupt;
>> + if (!gsi)
>> + return -ENODEV;
>> + first = false;
>> + } else if (gsi != gicc->spe_overflow_interrupt) {
>> + pr_warn("ACPI: SPE must have homogeneous interrupts\n");
>> + return -EINVAL;
>> + }
>
> Unfortunately, I don't think this is sufficient to detect a homogeneous
> system: we'll have to check the MIDRs instead, which is nasty. I would
> personally be in favour of enforcing homogeneity for ACPI systems when we
> bring up secondary CPUs, but I suspect others would disagree.
Given that all the SPE capable machines i'm aware of at the moment are
homogeneous, are we ok with just doing an online CPU MIDR check for now,
and cleaning that up if/when someone builds a machine and complains?
Thanks,
On Thu, Feb 14, 2019 at 12:03:57PM -0600, Jeremy Linton wrote:
> On 2/14/19 11:11 AM, Will Deacon wrote:
> > On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:
> > > +/*
> > > + * For lack of a better place, hook the normal PMU MADT walk
> > > + * and create a SPE device if we detect a recent MADT with
> > > + * a homogeneous PPI mapping.
> > > + */
> > > +static int arm_spe_acpi_parse_irqs(void)
> > > +{
> > > + int cpu, ret, irq;
> > > + u16 gsi = 0;
> > > + bool first = true;
> > > +
> > > + struct acpi_madt_generic_interrupt *gicc;
> > > +
> > > + /*
> > > + * sanity check all the GICC tables for the same interrupt number
> > > + * for now we only support homogeneous ACPI/SPE machines.
> > > + */
> > > + for_each_possible_cpu(cpu) {
> > > + gicc = acpi_cpu_get_madt_gicc(cpu);
> > > +
> > > + if (gicc->header.length < ACPI_MADT_GICC_SPE)
> > > + return -ENODEV;
> > > +
> > > + if (first) {
> > > + gsi = gicc->spe_overflow_interrupt;
> > > + if (!gsi)
> > > + return -ENODEV;
> > > + first = false;
> > > + } else if (gsi != gicc->spe_overflow_interrupt) {
> > > + pr_warn("ACPI: SPE must have homogeneous interrupts\n");
> > > + return -EINVAL;
> > > + }
> >
> > Unfortunately, I don't think this is sufficient to detect a homogeneous
> > system: we'll have to check the MIDRs instead, which is nasty. I would
> > personally be in favour of enforcing homogeneity for ACPI systems when we
> > bring up secondary CPUs, but I suspect others would disagree.
>
> Given that all the SPE capable machines i'm aware of at the moment are
> homogeneous, are we ok with just doing an online CPU MIDR check for now, and
> cleaning that up if/when someone builds a machine and complains?
Yeah, I think we added a new bit to the PPTT to tell you that the machine is
homogenous, so just check that first and bail if it's not set.
Will
Hi,
On 2/15/19 9:00 AM, Will Deacon wrote:
> On Thu, Feb 14, 2019 at 12:03:57PM -0600, Jeremy Linton wrote:
>> On 2/14/19 11:11 AM, Will Deacon wrote:
>>> On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:
>>>> +/*
>>>> + * For lack of a better place, hook the normal PMU MADT walk
>>>> + * and create a SPE device if we detect a recent MADT with
>>>> + * a homogeneous PPI mapping.
>>>> + */
>>>> +static int arm_spe_acpi_parse_irqs(void)
>>>> +{
>>>> + int cpu, ret, irq;
>>>> + u16 gsi = 0;
>>>> + bool first = true;
>>>> +
>>>> + struct acpi_madt_generic_interrupt *gicc;
>>>> +
>>>> + /*
>>>> + * sanity check all the GICC tables for the same interrupt number
>>>> + * for now we only support homogeneous ACPI/SPE machines.
>>>> + */
>>>> + for_each_possible_cpu(cpu) {
>>>> + gicc = acpi_cpu_get_madt_gicc(cpu);
>>>> +
>>>> + if (gicc->header.length < ACPI_MADT_GICC_SPE)
>>>> + return -ENODEV;
>>>> +
>>>> + if (first) {
>>>> + gsi = gicc->spe_overflow_interrupt;
>>>> + if (!gsi)
>>>> + return -ENODEV;
>>>> + first = false;
>>>> + } else if (gsi != gicc->spe_overflow_interrupt) {
>>>> + pr_warn("ACPI: SPE must have homogeneous interrupts\n");
>>>> + return -EINVAL;
>>>> + }
>>>
>>> Unfortunately, I don't think this is sufficient to detect a homogeneous
>>> system: we'll have to check the MIDRs instead, which is nasty. I would
>>> personally be in favour of enforcing homogeneity for ACPI systems when we
>>> bring up secondary CPUs, but I suspect others would disagree.
>>
>> Given that all the SPE capable machines i'm aware of at the moment are
>> homogeneous, are we ok with just doing an online CPU MIDR check for now, and
>> cleaning that up if/when someone builds a machine and complains?
>
> Yeah, I think we added a new bit to the PPTT to tell you that the machine is
> homogenous, so just check that first and bail if it's not set.
Yes of course, 100% better plan. Although its probably going to have to
be more of a case of walking all the possible cores and assuring they
have the same flag level (similar to how the socket flag is handled). Of
course that information is useful enough it should probably just be done
as part of the normal cpu topology walk. Then the people who have to
back port these patches end up with a big dependent set... <chuckle>