From: Konstantin Porotchkin <[email protected]>
This patch series contains the following changes/fixes:
1. Add support for Armada CN913x Development Board topology "B"
2. Add support for Armada CN913x Reference Design boards (CRB)
3. Fixes the CP11X references in PHY binding document
4. Fixes the NAND paritioninig scheme in DTS eliminating gap between
consecutive partitions
All above changes are already intergated into Marvell official SDK sources
v2:
- extract common nodes from DB boards to separate DTSI files
- disable eth2 on CRB boards until the required phy mode support is added
- mention the switch part ID in CRB board description
v3:
- do not rename setup A DTS files for DB variants
- fix a couple of wrong include names
v4:
- Rebase on top of Linus master branch (v5.11-rc7)
- Remove HS400 timing from CRB AP SDHCI (not supported by connected eMMC)
- Add cd-gpio entry to CP0 SDHCI for SD card support
- Add a comment to CN9130-CRB patch about the required defconfig
changes for supporting the onboard i2c expander
- Add Stefan's patch to enable 10G port on CN9130-DB platforms
Grzegorz Jaszczyk (1):
Documentation/bindings: phy: update references to cp11x
Konstantin Porotchkin (3):
arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
arm64: dts: cn913x: add device trees for topology B boards
arm64: dts: add support for Marvell cn9130-crb platform
Stefan Chulski (1):
dts: marvell: Enable 10G interface on 9130-DB board
.../bindings/phy/phy-mvebu-comphy.txt | 12 +-
arch/arm64/boot/dts/marvell/Makefile | 5 +
arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38 ++
arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46 ++
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 221 ++++++++++
arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 +
arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 +----------------
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 402 ++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 +
arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 +--------
arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 201 +++++++++
arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 +
arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 +--------
arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 220 ++++++++++
14 files changed, 1223 insertions(+), 784 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi
--
2.17.1
From: Konstantin Porotchkin <[email protected]>
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.
Signed-off-by: Konstantin Porotchkin <[email protected]>
---
arch/arm64/boot/dts/marvell/Makefile | 3 +
arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 +------------------
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 402 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 +---------
arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 201 ++++++++++
arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 +---------
arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 220 +++++++++++
10 files changed, 910 insertions(+), 778 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 34efe0fb6f37..5e39f9774e68 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -16,5 +16,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
new file mode 100644
index 000000000000..57e41cacd483
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board (setup "B").
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index d24294888400..994f347f2973 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -5,399 +5,18 @@
* Device tree for the CN9130-DB board.
*/
-#include "cn9130.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
+#include "cn9130-db.dtsi"
/ {
- model = "Marvell Armada CN9130-DB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- gpio1 = &cp0_gpio1;
- gpio2 = &cp0_gpio2;
- i2c0 = &cp0_i2c0;
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth2;
- spi1 = &cp0_spi0;
- spi2 = &cp0_spi1;
- };
-
- memory@00000000 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- ap0_reg_sd_vccq: ap0_sd_vccq@0 {
- compatible = "regulator-gpio";
- regulator-name = "ap0_sd_vccq";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1 3300000 0x0>;
- };
-
- cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
- compatible = "regulator-fixed";
- regulator-name = "cp0-xhci0-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_usb3_0_phy0: cp0_usb3_phy@0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_vbus0>;
- };
-
- cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
- compatible = "regulator-fixed";
- regulator-name = "cp0-xhci1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_usb3_0_phy1: cp0_usb3_phy@1 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_vbus1>;
- };
-
- cp0_reg_sd_vccq: cp0_sd_vccq@0 {
- compatible = "regulator-gpio";
- regulator-name = "cp0_sd_vccq";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1
- 3300000 0x0>;
- };
-
- cp0_reg_sd_vcc: cp0_sd_vcc@0 {
- compatible = "regulator-fixed";
- regulator-name = "cp0_sd_vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- cp0_sfp_eth0: sfp-eth@0 {
- compatible = "sff,sfp";
- i2c-bus = <&cp0_sfpp0_i2c>;
- los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
- /*
- * SFP cages are unconnected on early PCBs because of an the I2C
- * lanes not being connected. Prevent the port for being
- * unusable by disabling the SFP node.
- */
- status = "disabled";
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-/* on-board eMMC - U9 */
-&ap_sdhci0 {
- pinctrl-names = "default";
- bus-width = <8>;
- vqmmc-supply = <&ap0_reg_sd_vccq>;
- status = "okay";
+ model = "Marvell Armada CN9130-DB setup A";
};
-&cp0_crypto {
- status = "disabled";
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp0_eth0 {
- status = "disabled";
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy4 0>;
- managed = "in-band-status";
- sfp = <&cp0_sfp_eth0>;
-};
-
-/* CON56 */
-&cp0_eth1 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
-};
-
-/* CON57 */
-&cp0_eth2 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
-};
-
-&cp0_gpio1 {
- status = "okay";
-};
-
-&cp0_gpio2 {
- status = "okay";
-};
-
-&cp0_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c0_pins>;
- clock-frequency = <100000>;
-
- /* U36 */
- expander0: pca953x@21 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x21>;
- status = "okay";
- };
-
- /* U42 */
- eeprom0: eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- pagesize = <0x20>;
- };
-
- /* U38 */
- eeprom1: eeprom@57 {
- compatible = "atmel,24c64";
- reg = <0x57>;
- pagesize = <0x20>;
- };
-};
-
-&cp0_i2c1 {
- status = "okay";
- clock-frequency = <100000>;
-
- /* SLM-1521-V2 - U3 */
- i2c-mux@72 { /* verify address - depends on dpr */
- compatible = "nxp,pca9544";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x72>;
- cp0_sfpp0_i2c: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- /* U12 */
- cp0_module_expander1: pca9555@21 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x21>;
- };
-
- };
- };
-};
-
-&cp0_mdio {
- status = "okay";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-/* U54 */
-&cp0_nand_controller {
- pinctrl-names = "default";
- pinctrl-0 = <&nand_pins &nand_rb>;
-
- nand@0 {
- reg = <0>;
- label = "main-storage";
- nand-rb = <0>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
- nand-ecc-strength = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition@200000 {
- label = "Linux";
- reg = <0x200000 0xe00000>;
- };
- partition@1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
- };
- };
- };
-};
-
-/* SLM-1521-V2, CON6 */
-&cp0_pcie0 {
- status = "okay";
- num-lanes = <4>;
- num-viewport = <8>;
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy0 0
- &cp0_comphy1 0
- &cp0_comphy2 0
- &cp0_comphy3 0>;
-};
-
-&cp0_sata0 {
- status = "okay";
-
- /* SLM-1521-V2, CON2 */
- sata-port@1 {
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp0_comphy5 1>;
- };
-};
-
-/* CON 28 */
-&cp0_sdhci0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_sdhci_pins
- &cp0_sdhci_cd_pins>;
- bus-width = <4>;
- cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- vqmmc-supply = <&cp0_reg_sd_vccq>;
- vmmc-supply = <&cp0_reg_sd_vcc>;
-};
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
+ */
-/* U55 */
&cp0_spi1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi0_pins>;
- reg = <0x700680 0x50>;
-
- spi-flash@0 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- /* On-board MUX does not allow higher frequencies */
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot-0";
- reg = <0x0 0x200000>;
- };
-
- partition@400000 {
- label = "Filesystem-0";
- reg = <0x200000 0xe00000>;
- };
- };
- };
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
-
- cp0_i2c0_pins: cp0-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp0_i2c1_pins: cp0-i2c-pins-1 {
- marvell,pins = "mpp35", "mpp36";
- marvell,function = "i2c1";
- };
- cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
- marvell,pins = "mpp0", "mpp1", "mpp2",
- "mpp3", "mpp4", "mpp5",
- "mpp6", "mpp7", "mpp8",
- "mpp9", "mpp10", "mpp11";
- marvell,function = "ge0";
- };
- cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
- marvell,pins = "mpp44", "mpp45", "mpp46",
- "mpp47", "mpp48", "mpp49",
- "mpp50", "mpp51", "mpp52",
- "mpp53", "mpp54", "mpp55";
- marvell,function = "ge1";
- };
- cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
- cp0_sdhci_pins: cp0-sdhi-pins-0 {
- marvell,pins = "mpp56", "mpp57", "mpp58",
- "mpp59", "mpp60", "mpp61";
- marvell,function = "sdio";
- };
- cp0_spi0_pins: cp0-spi-pins-0 {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- nand_pins: nand-pins {
- marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
- "mpp19", "mpp20", "mpp21", "mpp22",
- "mpp23", "mpp24", "mpp25", "mpp26",
- "mpp27";
- marvell,function = "dev";
- };
- nand_rb: nand-rb {
- marvell,pins = "mpp13";
- marvell,function = "nf";
- };
- };
-};
-
-&cp0_usb3_0 {
- status = "okay";
- usb-phy = <&cp0_usb3_0_phy0>;
- phy-names = "usb";
};
-&cp0_usb3_1 {
- status = "okay";
- usb-phy = <&cp0_usb3_0_phy1>;
- phy-names = "usb";
-};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
new file mode 100644
index 000000000000..8de3a552b806
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -0,0 +1,402 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board.
+ */
+
+#include "cn9130.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ap0_reg_sd_vccq: ap0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy0: cp0_usb3_phy@0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus0>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy1: cp0_usb3_phy@1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
+ };
+
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ cp0_sfp_eth0: sfp-eth@0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_sfpp0_i2c>;
+ los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ vqmmc-supply = <&ap0_reg_sd_vccq>;
+ status = "okay";
+};
+
+&cp0_crypto {
+ status = "disabled";
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "disabled";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp0_sfp_eth0>;
+};
+
+/* CON56 */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+/* CON57 */
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+
+ /* U36 */
+ expander0: pca953x@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ status = "okay";
+ };
+
+ /* U42 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U38 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
+};
+
+&cp0_i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 { /* verify address - depends on dpr */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp0_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp0_module_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ };
+ };
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+/* U54 */
+&cp0_nand_controller {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins &nand_rb>;
+
+ nand@0 {
+ reg = <0>;
+ label = "main-storage";
+ nand-rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xe00000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+};
+
+&cp0_sata0 {
+ status = "okay";
+
+ /* SLM-1521-V2, CON2 */
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy5 1>;
+ };
+};
+
+/* CON 28 */
+&cp0_sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+};
+
+/* U55 */
+&cp0_spi1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>;
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot-0";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem-0";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = "mpp44", "mpp45", "mpp46",
+ "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52",
+ "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ nand_pins: nand-pins {
+ marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
+ "mpp19", "mpp20", "mpp21", "mpp22",
+ "mpp23", "mpp24", "mpp25", "mpp26",
+ "mpp27";
+ marvell,function = "dev";
+ };
+ nand_rb: nand-rb {
+ marvell,pins = "mpp13";
+ marvell,function = "nf";
+ };
+ };
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-B.dts b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts
new file mode 100644
index 000000000000..183b1ec8b1f0
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board (setup "B").
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9131-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dts
index 3c975f98b2a3..a60fdee79bf8 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -5,198 +5,18 @@
* Device tree for the CN9131-DB board.
*/
-#include "cn9130-db.dts"
+#include "cn9131-db.dtsi"
/ {
- model = "Marvell Armada CN9131-DB";
- compatible = "marvell,cn9131", "marvell,cn9130",
- "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
- aliases {
- gpio3 = &cp1_gpio1;
- gpio4 = &cp1_gpio2;
- ethernet3 = &cp1_eth0;
- ethernet4 = &cp1_eth1;
- };
-
- cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_xhci0_vbus_pins>;
- regulator-name = "cp1-xhci0-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-
- cp1_usb3_0_phy0: cp1_usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp1_reg_usb3_vbus0>;
- };
-
- cp1_sfp_eth1: sfp-eth1 {
- compatible = "sff,sfp";
- i2c-bus = <&cp1_i2c0>;
- los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_sfp_pins>;
- /*
- * SFP cages are unconnected on early PCBs because of an the I2C
- * lanes not being connected. Prevent the port for being
- * unusable by disabling the SFP node.
- */
- status = "disabled";
- };
+ model = "Marvell Armada CN9131-DB setup A";
};
-/*
- * Instantiate the first slave CP115
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
*/
-#define CP11X_NAME cp1
-#define CP11X_BASE f4000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE f4600000
-#define CP11X_PCIE1_BASE f4620000
-#define CP11X_PCIE2_BASE f4640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp1_crypto {
- status = "disabled";
-};
-
-&cp1_ethernet {
- status = "okay";
-};
-
-/* CON50 */
-&cp1_eth0 {
- status = "disabled";
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy4 0>;
- managed = "in-band-status";
- sfp = <&cp1_sfp_eth1>;
-};
-
-&cp1_gpio1 {
- status = "okay";
-};
-
-&cp1_gpio2 {
- status = "okay";
-};
-
-&cp1_i2c0 {
+&cp0_spi1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_i2c0_pins>;
- clock-frequency = <100000>;
};
-/* CON40 */
-&cp1_pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_pcie_reset_pins>;
- num-lanes = <2>;
- num-viewport = <8>;
- marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy0 0
- &cp1_comphy1 0>;
-};
-
-&cp1_sata0 {
- status = "okay";
-
- /* CON32 */
- sata-port@1 {
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy5 1>;
- };
-};
-
-/* U24 */
-&cp1_spi1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_spi0_pins>;
- reg = <0x700680 0x50>;
-
- spi-flash@0 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- /* On-board MUX does not allow higher frequencies */
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot-1";
- reg = <0x0 0x200000>;
- };
-
- partition@400000 {
- label = "Filesystem-1";
- reg = <0x200000 0xe00000>;
- };
- };
- };
-
-};
-
-&cp1_syscon0 {
- cp1_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
-
- cp1_i2c0_pins: cp1-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp1_spi0_pins: cp1-spi-pins-0 {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
- marvell,pins = "mpp3";
- marvell,function = "gpio";
- };
- cp1_sfp_pins: sfp-pins {
- marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
- marvell,function = "gpio";
- };
- cp1_pcie_reset_pins: cp1-pcie-reset-pins {
- marvell,pins = "mpp0";
- marvell,function = "gpio";
- };
- };
-};
-
-/* CON58 */
-&cp1_usb3_1 {
- status = "okay";
- usb-phy = <&cp1_usb3_0_phy0>;
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy3 1>;
- phy-names = "usb";
-};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
new file mode 100644
index 000000000000..82471a83ad6d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ compatible = "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ ethernet3 = &cp1_eth0;
+ ethernet4 = &cp1_eth1;
+ };
+
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp1_usb3_0_phy0: cp1_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus0>;
+ };
+
+ cp1_sfp_eth1: sfp-eth1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp1_i2c0>;
+ los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfp_pins>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+/*
+ * Instantiate the first slave CP115
+ */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp1_crypto {
+ status = "disabled";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+ status = "disabled";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp1_sfp_eth1>;
+};
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c0_pins>;
+ clock-frequency = <100000>;
+};
+
+/* CON40 */
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_pcie_reset_pins>;
+ num-lanes = <2>;
+ num-viewport = <8>;
+ marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy0 0
+ &cp1_comphy1 0>;
+};
+
+&cp1_sata0 {
+ status = "okay";
+
+ /* CON32 */
+ sata-port@1 {
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy5 1>;
+ };
+};
+
+/* U24 */
+&cp1_spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_spi0_pins>;
+ reg = <0x700680 0x50>;
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot-1";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem-1";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp1_i2c0_pins: cp1-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp1_spi0_pins: cp1-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+ cp1_sfp_pins: sfp-pins {
+ marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
+ cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+/* CON58 */
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-B.dts b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts
new file mode 100644
index 000000000000..7137a6f22d0f
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9132-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dts
index 4ef0df3097ca..1f2e6377afc3 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dts
@@ -5,217 +5,18 @@
* Device tree for the CN9132-DB board.
*/
-#include "cn9131-db.dts"
+#include "cn9132-db.dtsi"
/ {
- model = "Marvell Armada CN9132-DB";
- compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
- "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
- aliases {
- gpio5 = &cp2_gpio1;
- gpio6 = &cp2_gpio2;
- ethernet5 = &cp2_eth0;
- };
-
- cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
- compatible = "regulator-fixed";
- regulator-name = "cp2-xhci0-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
- };
-
- cp2_usb3_0_phy0: cp2_usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp2_reg_usb3_vbus0>;
- };
-
- cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
- compatible = "regulator-fixed";
- regulator-name = "cp2-xhci1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-
- cp2_usb3_0_phy1: cp2_usb3_phy1 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp2_reg_usb3_vbus1>;
- };
-
- cp2_reg_sd_vccq: cp2_sd_vccq@0 {
- compatible = "regulator-gpio";
- regulator-name = "cp2_sd_vcc";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1 3300000 0x0>;
- };
-
- cp2_sfp_eth0: sfp-eth0 {
- compatible = "sff,sfp";
- i2c-bus = <&cp2_sfpp0_i2c>;
- los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
- /*
- * SFP cages are unconnected on early PCBs because of an the I2C
- * lanes not being connected. Prevent the port for being
- * unusable by disabling the SFP node.
- */
- status = "disabled";
- };
+ model = "Marvell Armada CN9132-DB setup A";
};
-/*
- * Instantiate the second slave CP115
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
*/
-#define CP11X_NAME cp2
-#define CP11X_BASE f6000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE f6600000
-#define CP11X_PCIE1_BASE f6620000
-#define CP11X_PCIE2_BASE f6640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp2_crypto {
- status = "disabled";
-};
-
-&cp2_ethernet {
- status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp2_eth0 {
- status = "disabled";
- phy-mode = "10gbase-kr";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy4 0>;
- managed = "in-band-status";
- sfp = <&cp2_sfp_eth0>;
-};
-
-&cp2_gpio1 {
- status = "okay";
-};
-
-&cp2_gpio2 {
- status = "okay";
-};
-
-&cp2_i2c0 {
- clock-frequency = <100000>;
-
- /* SLM-1521-V2 - U3 */
- i2c-mux@72 {
- compatible = "nxp,pca9544";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x72>;
- cp2_sfpp0_i2c: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- /* U12 */
- cp2_module_expander1: pca9555@21 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x21>;
- };
- };
- };
-};
-
-/* SLM-1521-V2, CON6 */
-&cp2_pcie0 {
- status = "okay";
- num-lanes = <2>;
- num-viewport = <8>;
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy0 0
- &cp2_comphy1 0>;
-};
-
-/* SLM-1521-V2, CON8 */
-&cp2_pcie2 {
- status = "okay";
- num-lanes = <1>;
- num-viewport = <8>;
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy5 2>;
-};
-
-&cp2_sata0 {
+&cp0_spi1 {
status = "okay";
-
- /* SLM-1521-V2, CON4 */
- sata-port@0 {
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy2 0>;
- };
};
-/* CON 2 on SLM-1683 - microSD */
-&cp2_sdhci0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp2_sdhci_pins>;
- bus-width = <4>;
- cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&cp2_reg_sd_vccq>;
-};
-
-&cp2_syscon0 {
- cp2_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
-
- cp2_i2c0_pins: cp2-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp2_sdhci_pins: cp2-sdhi-pins-0 {
- marvell,pins = "mpp56", "mpp57", "mpp58",
- "mpp59", "mpp60", "mpp61";
- marvell,function = "sdio";
- };
- };
-};
-
-&cp2_usb3_0 {
- status = "okay";
- usb-phy = <&cp2_usb3_0_phy0>;
- phy-names = "usb";
-};
-
-/* SLM-1521-V2, CON11 */
-&cp2_usb3_1 {
- status = "okay";
- usb-phy = <&cp2_usb3_0_phy1>;
- phy-names = "usb";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy3 1>;
-};
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
new file mode 100644
index 000000000000..0c2d9f57318b
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ ethernet5 = &cp2_eth0;
+ };
+
+ cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy0: cp2_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus0>;
+ };
+
+ cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy1: cp2_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus1>;
+ };
+
+ cp2_reg_sd_vccq: cp2_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp2_sd_vcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp2_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp2_sfpp0_i2c>;
+ los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+/*
+ * Instantiate the second slave CP115
+ */
+
+#define CP11X_NAME cp2
+#define CP11X_BASE f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f6600000
+#define CP11X_PCIE1_BASE f6620000
+#define CP11X_PCIE2_BASE f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp2_crypto {
+ status = "disabled";
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
+ status = "disabled";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp2_sfp_eth0>;
+};
+
+&cp2_gpio1 {
+ status = "okay";
+};
+
+&cp2_gpio2 {
+ status = "okay";
+};
+
+&cp2_i2c0 {
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp2_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp2_module_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+ };
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp2_pcie0 {
+ status = "okay";
+ num-lanes = <2>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy0 0
+ &cp2_comphy1 0>;
+};
+
+/* SLM-1521-V2, CON8 */
+&cp2_pcie2 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy5 2>;
+};
+
+&cp2_sata0 {
+ status = "okay";
+
+ /* SLM-1521-V2, CON4 */
+ sata-port@0 {
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy2 0>;
+ };
+};
+
+/* CON 2 on SLM-1683 - microSD */
+&cp2_sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_sdhci_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <&cp2_reg_sd_vccq>;
+};
+
+&cp2_syscon0 {
+ cp2_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp2_i2c0_pins: cp2-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp2_sdhci_pins: cp2-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ };
+};
+
+&cp2_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+/* SLM-1521-V2, CON11 */
+&cp2_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy1>;
+ phy-names = "usb";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy3 1>;
+};
--
2.17.1
Hello,
> From: Konstantin Porotchkin <[email protected]>
>
> This patch series contains the following changes/fixes:
> 1. Add support for Armada CN913x Development Board topology "B"
> 2. Add support for Armada CN913x Reference Design boards (CRB)
> 3. Fixes the CP11X references in PHY binding document
> 4. Fixes the NAND paritioninig scheme in DTS eliminating gap between
> consecutive partitions
> All above changes are already intergated into Marvell official SDK sources
>
> v2:
> - extract common nodes from DB boards to separate DTSI files
> - disable eth2 on CRB boards until the required phy mode support is added
> - mention the switch part ID in CRB board description
>
> v3:
> - do not rename setup A DTS files for DB variants
> - fix a couple of wrong include names
>
> v4:
> - Rebase on top of Linus master branch (v5.11-rc7)
> - Remove HS400 timing from CRB AP SDHCI (not supported by connected eMMC)
> - Add cd-gpio entry to CP0 SDHCI for SD card support
> - Add a comment to CN9130-CRB patch about the required defconfig
> changes for supporting the onboard i2c expander
> - Add Stefan's patch to enable 10G port on CN9130-DB platforms
>
> Grzegorz Jaszczyk (1):
> Documentation/bindings: phy: update references to cp11x
>
> Konstantin Porotchkin (3):
> arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
> arm64: dts: cn913x: add device trees for topology B boards
> arm64: dts: add support for Marvell cn9130-crb platform
>
> Stefan Chulski (1):
> dts: marvell: Enable 10G interface on 9130-DB board
>
I've applied patches 1 and 2, but I have issue with patch 3, there was some
changes around the phys and I am not sure of the correct way to modify
the patch.
Could you rebase it on v5.13-c1 and fix the merge issue ?
Thanks,
Gregory
> .../bindings/phy/phy-mvebu-comphy.txt | 12 +-
> arch/arm64/boot/dts/marvell/Makefile | 5 +
> arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38 ++
> arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46 ++
> arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 221 ++++++++++
> arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 +
> arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 +----------------
> arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 402 ++++++++++++++++++
> arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 +
> arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 +--------
> arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 201 +++++++++
> arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 +
> arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 +--------
> arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 220 ++++++++++
> 14 files changed, 1223 insertions(+), 784 deletions(-)
> create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
> create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
> create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
> create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
> create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
> create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi
>
> --
> 2.17.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Hi, Gregory,
The last series was v5. I will rebase on top of Linus 5.13-rcx and then post new v6 set.
Regards
Kosta
> -----Original Message-----
> From: Gregory CLEMENT <[email protected]>
> Sent: Thursday, June 17, 2021 18:40
> To: Kostya Porotchkin <[email protected]>; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Nadav Haklai
> <[email protected]>; Stefan Chulski <[email protected]>; Ben Peled
> <[email protected]>; Kostya Porotchkin <[email protected]>
> Subject: [EXT] Re: [PATCH v4 0/5] DTS updates for Marvell Armada CN913x
> platforms
>
> External Email
>
> ----------------------------------------------------------------------
> Hello,
>
> > From: Konstantin Porotchkin <[email protected]>
> >
> > This patch series contains the following changes/fixes:
> > 1. Add support for Armada CN913x Development Board topology "B"
> > 2. Add support for Armada CN913x Reference Design boards (CRB) 3.
> > Fixes the CP11X references in PHY binding document 4. Fixes the NAND
> > paritioninig scheme in DTS eliminating gap between consecutive
> > partitions All above changes are already intergated into Marvell
> > official SDK sources
> >
> > v2:
> > - extract common nodes from DB boards to separate DTSI files
> > - disable eth2 on CRB boards until the required phy mode support is
> > added
> > - mention the switch part ID in CRB board description
> >
> > v3:
> > - do not rename setup A DTS files for DB variants
> > - fix a couple of wrong include names
> >
> > v4:
> > - Rebase on top of Linus master branch (v5.11-rc7)
> > - Remove HS400 timing from CRB AP SDHCI (not supported by connected
> > eMMC)
> > - Add cd-gpio entry to CP0 SDHCI for SD card support
> > - Add a comment to CN9130-CRB patch about the required defconfig
> > changes for supporting the onboard i2c expander
> > - Add Stefan's patch to enable 10G port on CN9130-DB platforms
> >
> > Grzegorz Jaszczyk (1):
> > Documentation/bindings: phy: update references to cp11x
> >
> > Konstantin Porotchkin (3):
> > arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
> > arm64: dts: cn913x: add device trees for topology B boards
> > arm64: dts: add support for Marvell cn9130-crb platform
> >
> > Stefan Chulski (1):
> > dts: marvell: Enable 10G interface on 9130-DB board
> >
>
> I've applied patches 1 and 2, but I have issue with patch 3, there was some
> changes around the phys and I am not sure of the correct way to modify the
> patch.
>
> Could you rebase it on v5.13-c1 and fix the merge issue ?
>
> Thanks,
>
> Gregory
>
> > .../bindings/phy/phy-mvebu-comphy.txt | 12 +-
> > arch/arm64/boot/dts/marvell/Makefile | 5 +
> > arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38 ++
> > arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46 ++
> > arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 221 ++++++++++
> > arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 +
> > arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 +----------------
> > arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 402 ++++++++++++++++++
> > arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 +
> > arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 +--------
> > arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 201 +++++++++
> > arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 +
> > arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 +--------
> > arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 220 ++++++++++
> > 14 files changed, 1223 insertions(+), 784 deletions(-) create mode
> > 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
> > create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi
> >
> > --
> > 2.17.1
> >
>
> --
> Gregory Clement, Bootlin
> Embedded Linux and Kernel engineering
> https://urldefense.proofpoint.com/v2/url?u=http-
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