SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
bindings and the example to match.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Eric Biggers <[email protected]>
Reviewed-by: Iskren Chernev <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index b5fc686cb3a1..04baa98bf7e4 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -119,7 +119,6 @@ allOf:
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- - qcom,sm8450-ufshc
- qcom,sm8550-ufshc
then:
properties:
@@ -150,6 +149,7 @@ allOf:
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
+ - qcom,sm8450-ufshc
then:
properties:
clocks:
@@ -275,7 +275,9 @@ examples:
ufs@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>;
+ reg = <0 0x01d84000 0 0x3000>,
+ <0 0x01d88000 0 0x8000>;
+ reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -303,7 +305,8 @@ examples:
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
+ "rx_lane1_sync_clk",
+ "ice_core_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -311,7 +314,8 @@ examples:
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz = <75000000 300000000>,
<0 0>,
<0 0>,
@@ -319,6 +323,7 @@ examples:
<75000000 300000000>,
<0 0>,
<0 0>,
- <0 0>;
+ <0 0>,
+ <75000000 300000000>;
};
};
--
2.41.0
On 26/06/2023 10:15, Luca Weiss wrote:
> SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
> bindings and the example to match.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Eric Biggers <[email protected]>
> Reviewed-by: Iskren Chernev <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
SM8450 should be rather converted to qcom,ice.
Best regards,
Krzysztof
On Mon, 26 Jun 2023 10:15:59 +0200, Luca Weiss wrote:
> SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
> bindings and the example to match.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Eric Biggers <[email protected]>
> Reviewed-by: Iskren Chernev <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/ufs/qcom,ufs.example.dtb: ufs@1d84000: Unevaluated properties are not allowed ('reg-names' was unexpected)
from schema $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Mon Jun 26, 2023 at 10:27 AM CEST, Krzysztof Kozlowski wrote:
> On 26/06/2023 10:15, Luca Weiss wrote:
> > SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
> > bindings and the example to match.
> >
> > Reviewed-by: Krzysztof Kozlowski <[email protected]>
> > Reviewed-by: Eric Biggers <[email protected]>
> > Reviewed-by: Iskren Chernev <[email protected]>
> > Signed-off-by: Luca Weiss <[email protected]>
>
> SM8450 should be rather converted to qcom,ice.
In v5 sm8450 is now using ICE, both in dtsi and binding example. But I
guess you could also argue reg-names should be purged from dtsi and
binding completely and to convert all existing dtsi to use the
standalone ice node, right?
But I'd also like for this series to finally land at some point, we can
do this later, okay?
Regards
Luca
>
> Best regards,
> Krzysztof
On 27/06/2023 10:29, Luca Weiss wrote:
> On Mon Jun 26, 2023 at 10:27 AM CEST, Krzysztof Kozlowski wrote:
>> On 26/06/2023 10:15, Luca Weiss wrote:
>>> SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
>>> bindings and the example to match.
>>>
>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>> Reviewed-by: Eric Biggers <[email protected]>
>>> Reviewed-by: Iskren Chernev <[email protected]>
>>> Signed-off-by: Luca Weiss <[email protected]>
>>
>> SM8450 should be rather converted to qcom,ice.
>
> In v5 sm8450 is now using ICE, both in dtsi and binding example. But I
> guess you could also argue reg-names should be purged from dtsi and
> binding completely and to convert all existing dtsi to use the
> standalone ice node, right?
It would be good, but that's no exactly my goal. My goal is to have
dtbs_check without errors.
>
> But I'd also like for this series to finally land at some point, we can
> do this later, okay?
I need to look at v5 then.
Best regards,
Krzysztof