2020-08-13 03:42:02

by Qiu Wenbo

Subject: [PATCH v2] riscv: Setup exception vector for nommu platform

Exception vector is missing on nommu platform and that is an issue.
This patch is tested in Sipeed Maix Bit Dev Board.

Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
Suggested-by: Anup Patel <[email protected]>
Suggested-by: Atish Patra <[email protected]>
Signed-off-by: Qiu Wenbo <[email protected]>
---
arch/riscv/kernel/head.S | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index d0c5c316e9bb..0a4e81b8dc79 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -77,16 +77,10 @@ relocate:
csrw CSR_SATP, a0
.align 2
1:
- /* Set trap vector to exception handler */
- la a0, handle_exception
+ /* Set trap vector to spin forever to help debug */
+ la a0, .Lsecondary_park
csrw CSR_TVEC, a0

- /*
- * Set sup0 scratch register to 0, indicating to exception vector that
- * we are presently executing in kernel.
- */
- csrw CSR_SCRATCH, zero
-
/* Reload the global pointer */
.option push
.option norelax
@@ -144,9 +138,23 @@ secondary_start_common:
la a0, swapper_pg_dir
call relocate
#endif
+ call setup_trap_vector
tail smp_callin
#endif /* CONFIG_SMP */

+.align 2
+setup_trap_vector:
+ /* Set trap vector to exception handler */
+ la a0, handle_exception
+ csrw CSR_TVEC, a0
+
+ /*
+ * Set sup0 scratch register to 0, indicating to exception vector that
+ * we are presently executing in kernel.
+ */
+ csrw CSR_SCRATCH, zero
+ ret
+
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
@@ -240,6 +248,7 @@ clear_bss_done:
call relocate
#endif /* CONFIG_MMU */

+ call setup_trap_vector
/* Restore C environment */
la tp, init_task
sw zero, TASK_TI_CPU(tp)
--
2.28.0

2020-08-13 05:45:34

by Damien Le Moal

Subject: Re: [PATCH v2] riscv: Setup exception vector for nommu platform

On 2020/08/13 12:40, Qiu Wenbo wrote:
> Exception vector is missing on nommu platform and that is an issue.
> This patch is tested in Sipeed Maix Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Suggested-by: Anup Patel <[email protected]>
> Suggested-by: Atish Patra <[email protected]>
> Signed-off-by: Qiu Wenbo <[email protected]>

Please add a cc stable #5.8 tag. Kendryte support is in 5.8 stable.

> ---
> arch/riscv/kernel/head.S | 25 +++++++++++++++++--------
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index d0c5c316e9bb..0a4e81b8dc79 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -77,16 +77,10 @@ relocate:
> csrw CSR_SATP, a0
> .align 2
> 1:
> - /* Set trap vector to exception handler */
> - la a0, handle_exception
> + /* Set trap vector to spin forever to help debug */
> + la a0, .Lsecondary_park
> csrw CSR_TVEC, a0
>
> - /*
> - * Set sup0 scratch register to 0, indicating to exception vector that
> - * we are presently executing in kernel.
> - */
> - csrw CSR_SCRATCH, zero
> -
> /* Reload the global pointer */
> .option push
> .option norelax
> @@ -144,9 +138,23 @@ secondary_start_common:
> la a0, swapper_pg_dir
> call relocate
> #endif
> + call setup_trap_vector
> tail smp_callin
> #endif /* CONFIG_SMP */
>
> +.align 2
> +setup_trap_vector:
> + /* Set trap vector to exception handler */
> + la a0, handle_exception
> + csrw CSR_TVEC, a0
> +
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector that
> + * we are presently executing in kernel.
> + */
> + csrw CSR_SCRATCH, zero
> + ret
> +
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
> @@ -240,6 +248,7 @@ clear_bss_done:
> call relocate
> #endif /* CONFIG_MMU */
>
> + call setup_trap_vector
> /* Restore C environment */
> la tp, init_task
> sw zero, TASK_TI_CPU(tp)
>


--
Damien Le Moal
Western Digital Research

2020-08-13 05:46:22

by Atish Patra

Subject: Re: [PATCH v2] riscv: Setup exception vector for nommu platform

On Wed, Aug 12, 2020 at 8:40 PM Qiu Wenbo <[email protected]> wrote:
>
> Exception vector is missing on nommu platform and that is an issue.
> This patch is tested in Sipeed Maix Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Suggested-by: Anup Patel <[email protected]>
> Suggested-by: Atish Patra <[email protected]>
> Signed-off-by: Qiu Wenbo <[email protected]>
> ---
> arch/riscv/kernel/head.S | 25 +++++++++++++++++--------
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index d0c5c316e9bb..0a4e81b8dc79 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -77,16 +77,10 @@ relocate:
> csrw CSR_SATP, a0
> .align 2
> 1:
> - /* Set trap vector to exception handler */
> - la a0, handle_exception
> + /* Set trap vector to spin forever to help debug */
> + la a0, .Lsecondary_park
> csrw CSR_TVEC, a0
>
> - /*
> - * Set sup0 scratch register to 0, indicating to exception vector that
> - * we are presently executing in kernel.
> - */
> - csrw CSR_SCRATCH, zero
> -
> /* Reload the global pointer */
> .option push
> .option norelax
> @@ -144,9 +138,23 @@ secondary_start_common:
> la a0, swapper_pg_dir
> call relocate
> #endif
> + call setup_trap_vector
> tail smp_callin
> #endif /* CONFIG_SMP */
>
> +.align 2
> +setup_trap_vector:
> + /* Set trap vector to exception handler */
> + la a0, handle_exception
> + csrw CSR_TVEC, a0
> +
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector that
> + * we are presently executing in kernel.
> + */
> + csrw CSR_SCRATCH, zero
> + ret
> +
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
> @@ -240,6 +248,7 @@ clear_bss_done:
> call relocate
> #endif /* CONFIG_MMU */
>
> + call setup_trap_vector
> /* Restore C environment */
> la tp, init_task
> sw zero, TASK_TI_CPU(tp)
> --
> 2.28.0
>
@palmer: Can you queue this for the next part2 PR ?

Reviewed-by: Atish Patra <[email protected]>
--
Regards,
Atish

2020-08-13 06:47:59

by Atish Patra

Subject: Re: [PATCH v2] riscv: Setup exception vector for nommu platform

On Wed, Aug 12, 2020 at 10:44 PM Damien Le Moal <[email protected]> wrote:
>
> On 2020/08/13 12:40, Qiu Wenbo wrote:
> > Exception vector is missing on nommu platform and that is an issue.
> > This patch is tested in Sipeed Maix Bit Dev Board.
> >
> > Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> > Suggested-by: Anup Patel <[email protected]>
> > Suggested-by: Atish Patra <[email protected]>
> > Signed-off-by: Qiu Wenbo <[email protected]>
>
> Please add a cc stable #5.8 tag. Kendryte support is in 5.8 stable.
>

That won't be necessary as the patch that broke nommu (79b1feba5455) was
part of the 1st PR sent towards 5.9-rc1.


> > ---
> > arch/riscv/kernel/head.S | 25 +++++++++++++++++--------
> > 1 file changed, 17 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> > index d0c5c316e9bb..0a4e81b8dc79 100644
> > --- a/arch/riscv/kernel/head.S
> > +++ b/arch/riscv/kernel/head.S
> > @@ -77,16 +77,10 @@ relocate:
> > csrw CSR_SATP, a0
> > .align 2
> > 1:
> > - /* Set trap vector to exception handler */
> > - la a0, handle_exception
> > + /* Set trap vector to spin forever to help debug */
> > + la a0, .Lsecondary_park
> > csrw CSR_TVEC, a0
> >
> > - /*
> > - * Set sup0 scratch register to 0, indicating to exception vector that
> > - * we are presently executing in kernel.
> > - */
> > - csrw CSR_SCRATCH, zero
> > -
> > /* Reload the global pointer */
> > .option push
> > .option norelax
> > @@ -144,9 +138,23 @@ secondary_start_common:
> > la a0, swapper_pg_dir
> > call relocate
> > #endif
> > + call setup_trap_vector
> > tail smp_callin
> > #endif /* CONFIG_SMP */
> >
> > +.align 2
> > +setup_trap_vector:
> > + /* Set trap vector to exception handler */
> > + la a0, handle_exception
> > + csrw CSR_TVEC, a0
> > +
> > + /*
> > + * Set sup0 scratch register to 0, indicating to exception vector that
> > + * we are presently executing in kernel.
> > + */
> > + csrw CSR_SCRATCH, zero
> > + ret
> > +
> > .Lsecondary_park:
> > /* We lack SMP support or have too many harts, so park this hart */
> > wfi
> > @@ -240,6 +248,7 @@ clear_bss_done:
> > call relocate
> > #endif /* CONFIG_MMU */
> >
> > + call setup_trap_vector
> > /* Restore C environment */
> > la tp, init_task
> > sw zero, TASK_TI_CPU(tp)
> >
>
>
> --
> Damien Le Moal
> Western Digital Research



--
Regards,
Atish

2020-08-13 07:05:11

by Damien Le Moal

Subject: Re: [PATCH v2] riscv: Setup exception vector for nommu platform

On 2020/08/13 15:45, Atish Patra wrote:
> On Wed, Aug 12, 2020 at 10:44 PM Damien Le Moal <[email protected]> wrote:
>>
>> On 2020/08/13 12:40, Qiu Wenbo wrote:
>>> Exception vector is missing on nommu platform and that is an issue.
>>> This patch is tested in Sipeed Maix Bit Dev Board.
>>>
>>> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
>>> Suggested-by: Anup Patel <[email protected]>
>>> Suggested-by: Atish Patra <[email protected]>
>>> Signed-off-by: Qiu Wenbo <[email protected]>
>>
>> Please add a cc stable #5.8 tag. Kendryte support is in 5.8 stable.
>>
>
> That won't be necessary as the patch that broke nommu (79b1feba5455) was
> part of the 1st PR sent towards 5.9-rc1.

Oops. Yes indeed. Thanks !



--
Damien Le Moal
Western Digital Research

2020-08-13 08:51:55

by Anup Patel

Subject: Re: [PATCH v2] riscv: Setup exception vector for nommu platform

On Thu, Aug 13, 2020 at 9:10 AM Qiu Wenbo <[email protected]> wrote:
>
> Exception vector is missing on nommu platform and that is an issue.
> This patch is tested in Sipeed Maix Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Suggested-by: Anup Patel <[email protected]>
> Suggested-by: Atish Patra <[email protected]>
> Signed-off-by: Qiu Wenbo <[email protected]>
> ---
> arch/riscv/kernel/head.S | 25 +++++++++++++++++--------
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index d0c5c316e9bb..0a4e81b8dc79 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -77,16 +77,10 @@ relocate:
> csrw CSR_SATP, a0
> .align 2
> 1:
> - /* Set trap vector to exception handler */
> - la a0, handle_exception
> + /* Set trap vector to spin forever to help debug */
> + la a0, .Lsecondary_park
> csrw CSR_TVEC, a0
>
> - /*
> - * Set sup0 scratch register to 0, indicating to exception vector that
> - * we are presently executing in kernel.
> - */
> - csrw CSR_SCRATCH, zero
> -
> /* Reload the global pointer */
> .option push
> .option norelax
> @@ -144,9 +138,23 @@ secondary_start_common:
> la a0, swapper_pg_dir
> call relocate
> #endif
> + call setup_trap_vector
> tail smp_callin
> #endif /* CONFIG_SMP */
>
> +.align 2
> +setup_trap_vector:
> + /* Set trap vector to exception handler */
> + la a0, handle_exception
> + csrw CSR_TVEC, a0
> +
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector that
> + * we are presently executing in kernel.
> + */
> + csrw CSR_SCRATCH, zero
> + ret
> +
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
> @@ -240,6 +248,7 @@ clear_bss_done:
> call relocate
> #endif /* CONFIG_MMU */
>
> + call setup_trap_vector
> /* Restore C environment */
> la tp, init_task
> sw zero, TASK_TI_CPU(tp)
> --
> 2.28.0
>

Looks good to me.

Reviewed-by: Anup Patel <[email protected]>

Regards,
Anup

2020-08-14 23:27:40

by Palmer Dabbelt

Subject: Re: [PATCH v2] riscv: Setup exception vector for nommu platform

On Thu, 13 Aug 2020 01:49:44 PDT (-0700), [email protected] wrote:
> On Thu, Aug 13, 2020 at 9:10 AM Qiu Wenbo <[email protected]> wrote:
>>
>> Exception vector is missing on nommu platform and that is an issue.
>> This patch is tested in Sipeed Maix Bit Dev Board.
>>
>> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
>> Suggested-by: Anup Patel <[email protected]>
>> Suggested-by: Atish Patra <[email protected]>
>> Signed-off-by: Qiu Wenbo <[email protected]>
>> ---
>> arch/riscv/kernel/head.S | 25 +++++++++++++++++--------
>> 1 file changed, 17 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
>> index d0c5c316e9bb..0a4e81b8dc79 100644
>> --- a/arch/riscv/kernel/head.S
>> +++ b/arch/riscv/kernel/head.S
>> @@ -77,16 +77,10 @@ relocate:
>> csrw CSR_SATP, a0
>> .align 2
>> 1:
>> - /* Set trap vector to exception handler */
>> - la a0, handle_exception
>> + /* Set trap vector to spin forever to help debug */
>> + la a0, .Lsecondary_park
>> csrw CSR_TVEC, a0
>>
>> - /*
>> - * Set sup0 scratch register to 0, indicating to exception vector that
>> - * we are presently executing in kernel.
>> - */
>> - csrw CSR_SCRATCH, zero
>> -
>> /* Reload the global pointer */
>> .option push
>> .option norelax
>> @@ -144,9 +138,23 @@ secondary_start_common:
>> la a0, swapper_pg_dir
>> call relocate
>> #endif
>> + call setup_trap_vector
>> tail smp_callin
>> #endif /* CONFIG_SMP */
>>
>> +.align 2
>> +setup_trap_vector:
>> + /* Set trap vector to exception handler */
>> + la a0, handle_exception
>> + csrw CSR_TVEC, a0
>> +
>> + /*
>> + * Set sup0 scratch register to 0, indicating to exception vector that
>> + * we are presently executing in kernel.
>> + */
>> + csrw CSR_SCRATCH, zero
>> + ret
>> +
>> .Lsecondary_park:
>> /* We lack SMP support or have too many harts, so park this hart */
>> wfi
>> @@ -240,6 +248,7 @@ clear_bss_done:
>> call relocate
>> #endif /* CONFIG_MMU */
>>
>> + call setup_trap_vector
>> /* Restore C environment */
>> la tp, init_task
>> sw zero, TASK_TI_CPU(tp)
>> --
>> 2.28.0
>>
>
> Looks good to me.
>
> Reviewed-by: Anup Patel <[email protected]>
>
> Regards,
> Anup

Thanks, this is on fixes.