2022-07-12 23:39:41

by Kirill A. Shutemov

[permalink] [raw]
Subject: [PATCHv5 01/13] x86/mm: Fix CR3_ADDR_MASK

The mask must not include bits above physical address mask. These bits
are reserved and can be used for other things. Bits 61 and 62 are used
for Linear Address Masking.

Signed-off-by: Kirill A. Shutemov <[email protected]>
Reviewed-by: Rick Edgecombe <[email protected]>
---
arch/x86/include/asm/processor-flags.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
index 02c2cbda4a74..a7f3d9100adb 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -35,7 +35,7 @@
*/
#ifdef CONFIG_X86_64
/* Mask off the address space ID and SME encryption bits. */
-#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
+#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK)
#define CR3_PCID_MASK 0xFFFull
#define CR3_NOFLUSH BIT_ULL(63)

--
2.35.1


2022-07-21 13:22:29

by Alexander Potapenko

[permalink] [raw]
Subject: Re: [PATCHv5 01/13] x86/mm: Fix CR3_ADDR_MASK

On Wed, Jul 13, 2022 at 1:13 AM Kirill A. Shutemov
<[email protected]> wrote:
>
> The mask must not include bits above physical address mask. These bits
> are reserved and can be used for other things. Bits 61 and 62 are used
> for Linear Address Masking.
>
> Signed-off-by: Kirill A. Shutemov <[email protected]>
> Reviewed-by: Rick Edgecombe <[email protected]>
Reviewed-by: Alexander Potapenko <[email protected]>
Tested-by: Alexander Potapenko <[email protected]>

> ---
> arch/x86/include/asm/processor-flags.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
> index 02c2cbda4a74..a7f3d9100adb 100644
> --- a/arch/x86/include/asm/processor-flags.h
> +++ b/arch/x86/include/asm/processor-flags.h
> @@ -35,7 +35,7 @@
> */
> #ifdef CONFIG_X86_64
> /* Mask off the address space ID and SME encryption bits. */
> -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
> +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK)
> #define CR3_PCID_MASK 0xFFFull
> #define CR3_NOFLUSH BIT_ULL(63)
>
> --
> 2.35.1
>


--
Alexander Potapenko
Software Engineer

Google Germany GmbH
Erika-Mann-Straße, 33
80636 München

Geschäftsführer: Paul Manicle, Liana Sebastian
Registergericht und -nummer: Hamburg, HRB 86891
Sitz der Gesellschaft: Hamburg

2022-07-29 04:23:06

by Hu, Robert

[permalink] [raw]
Subject: RE: [PATCHv5 01/13] x86/mm: Fix CR3_ADDR_MASK

> -----Original Message-----
> From: Kirill A. Shutemov <[email protected]>
> Sent: Wednesday, July 13, 2022 07:13
> To: Dave Hansen <[email protected]>; Lutomirski, Andy
> <[email protected]>; Peter Zijlstra <[email protected]>
> Cc: [email protected]; Kostya Serebryany <[email protected]>; Andrey Ryabinin
> <[email protected]>; Andrey Konovalov <[email protected]>;
> Alexander Potapenko <[email protected]>; Taras Madan
> <[email protected]>; Dmitry Vyukov <[email protected]>; H . J . Lu
> <[email protected]>; Andi Kleen <[email protected]>; Edgecombe, Rick P
> <[email protected]>; [email protected]; linux-
> [email protected]; Kirill A. Shutemov <[email protected]>
> Subject: [PATCHv5 01/13] x86/mm: Fix CR3_ADDR_MASK
>
> The mask must not include bits above physical address mask. These bits are
> reserved and can be used for other things. Bits 61 and 62 are used for Linear
> Address Masking.
>
> Signed-off-by: Kirill A. Shutemov <[email protected]>
> Reviewed-by: Rick Edgecombe <[email protected]>
> ---
> arch/x86/include/asm/processor-flags.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/processor-flags.h
> b/arch/x86/include/asm/processor-flags.h
> index 02c2cbda4a74..a7f3d9100adb 100644
> --- a/arch/x86/include/asm/processor-flags.h
> +++ b/arch/x86/include/asm/processor-flags.h
> @@ -35,7 +35,7 @@
> */
[Hu, Robert]
The comments above these #define's, explaining CR3 layout, can be updated on
the new CR3 bits as well?

> #ifdef CONFIG_X86_64
> /* Mask off the address space ID and SME encryption bits. */
> -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull)
> +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK)
> #define CR3_PCID_MASK 0xFFFull
> #define CR3_NOFLUSH BIT_ULL(63)
>
> --
> 2.35.1