Add i.MX8QXP CPU opp table to support cpufreq.
Signed-off-by: Anson Huang <[email protected]>
---
No change since V2.
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4c3dd95..1e08387 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -34,6 +34,10 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_A35_CLK>;
+ clock-latency = <61036>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&a35_0_opp_table>;
};
A35_1: cpu@1 {
@@ -42,6 +46,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ operating-points-v2 = <&a35_0_opp_table>;
};
A35_2: cpu@2 {
@@ -50,6 +55,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ operating-points-v2 = <&a35_0_opp_table>;
};
A35_3: cpu@3 {
@@ -58,6 +64,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ operating-points-v2 = <&a35_0_opp_table>;
};
A35_L2: l2-cache0 {
@@ -65,6 +72,24 @@
};
};
+ a35_0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
--
2.7.4
On NXP's i.MX SoCs with system controller inside, CPU frequency
scaling can ONLY be done by system controller firmware, and it
can ONLY be requested from secure mode, so Linux kernel has to
call ARM SMC to trap to ARM-Trusted-Firmware to request system
controller firmware to do CPU frequency scaling.
This patch adds i.MX system controller CPU frequency scaling support,
it reuses cpufreq-dt driver and implement the CPU frequency scaling
inside SCU clock driver.
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V2:
- remove ifdef CONFIG_CPUFREQ_DT as it is NOT that critical and has mistake in V2;
- put the CPU clock check and SMC call in a separate function.
--
drivers/clk/imx/clk-scu.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index 7ccf7ed..885bf33 100644
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -4,14 +4,30 @@
* Dong Aisheng <[email protected]>
*/
+#include <linux/arm-smccc.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/slab.h>
#include "clk-scu.h"
+#define IMX_SIP_CPUFREQ 0xC2000001
+#define IMX_SIP_SET_CPUFREQ 0x00
+
static struct imx_sc_ipc *ccm_ipc_handle;
+struct imx_sc_cpufreq {
+ const char *clk_name;
+ u32 cluster_id;
+};
+
+static const struct imx_sc_cpufreq imx_sc_cpufreq_data[] = {
+ {
+ .clk_name = "a35_clk",
+ .cluster_id = 0,
+ },
+};
+
/*
* struct clk_scu - Description of one SCU clock
* @hw: the common clk_hw
@@ -145,6 +161,39 @@ static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
return rate;
}
+static bool clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate)
+{
+ struct clk_scu *clk = to_clk_scu(hw);
+ struct arm_smccc_res res;
+ unsigned int cluster_id;
+ int i;
+
+ /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
+ if (clk->clk_type == IMX_SC_PM_CLK_CPU) {
+ for (i = 0; i < ARRAY_SIZE(imx_sc_cpufreq_data); i++) {
+ if (!strcmp(clk_hw_get_name(hw),
+ imx_sc_cpufreq_data[i].clk_name)) {
+ cluster_id = imx_sc_cpufreq_data[i].cluster_id;
+ break;
+ }
+ }
+
+ /*
+ * As some other clock types have same value as
+ * IMX_SC_PM_CLK_CPU, so we need to double check
+ * the clock being scaled is indeed CPU clock which
+ * matches the table we define.
+ */
+ if (i < ARRAY_SIZE(imx_sc_cpufreq_data)) {
+ arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ,
+ cluster_id, rate, 0, 0, 0, 0, &res);
+ return true;
+ }
+ }
+
+ return false;
+}
+
/*
* clk_scu_set_rate - Set rate for a SCU clock
* @hw: clock to change rate for
@@ -161,6 +210,10 @@ static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate,
struct imx_sc_msg_req_set_clock_rate msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ /* check if it is CPU frequency scaling */
+ if (clk_scu_atf_set_cpu_rate(hw, rate))
+ return 0;
+
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PM;
hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;
--
2.7.4
Quoting Anson Huang (2019-02-13 07:59:32)
> @@ -145,6 +161,39 @@ static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
> return rate;
> }
>
> +static bool clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate)
> +{
> + struct clk_scu *clk = to_clk_scu(hw);
> + struct arm_smccc_res res;
> + unsigned int cluster_id;
> + int i;
> +
> + /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
> + if (clk->clk_type == IMX_SC_PM_CLK_CPU) {
> + for (i = 0; i < ARRAY_SIZE(imx_sc_cpufreq_data); i++) {
> + if (!strcmp(clk_hw_get_name(hw),
> + imx_sc_cpufreq_data[i].clk_name)) {
> + cluster_id = imx_sc_cpufreq_data[i].cluster_id;
> + break;
> + }
> + }
Is there some reason why these clks can't be determined once at boot
time? It would be a good idea to avoid doing any sort of string
comparison here, instead just calling the right arm_smccc_smc with the
right arguments based on code that registers those types of clks.
Best Regards!
Anson Huang
> -----Original Message-----
> From: Stephen Boyd [mailto:[email protected]]
> Sent: 2019年2月14日 1:43
> To: [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Aisheng Dong
> <[email protected]>; Anson Huang <[email protected]>; Daniel
> Baluta <[email protected]>
> Cc: dl-linux-imx <[email protected]>
> Subject: Re: [PATCH V3 2/2] clk: imx: scu: add cpu frequency scaling support
>
> Quoting Anson Huang (2019-02-13 07:59:32)
> > @@ -145,6 +161,39 @@ static long clk_scu_round_rate(struct clk_hw *hw,
> unsigned long rate,
> > return rate;
> > }
> >
> > +static bool clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long
> > +rate) {
> > + struct clk_scu *clk = to_clk_scu(hw);
> > + struct arm_smccc_res res;
> > + unsigned int cluster_id;
> > + int i;
> > +
> > + /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware
> */
> > + if (clk->clk_type == IMX_SC_PM_CLK_CPU) {
> > + for (i = 0; i < ARRAY_SIZE(imx_sc_cpufreq_data); i++) {
> > + if (!strcmp(clk_hw_get_name(hw),
> > + imx_sc_cpufreq_data[i].clk_name)) {
> > + cluster_id = imx_sc_cpufreq_data[i].cluster_id;
> > + break;
> > + }
> > + }
>
> Is there some reason why these clks can't be determined once at boot time?
> It would be a good idea to avoid doing any sort of string comparison here,
> instead just calling the right arm_smccc_smc with the right arguments based
> on code that registers those types of clks.
Agree, I can avoid string comparison in runtime, in V4 patch I just sent, I add another
clk ops for CPU clock, and use resource ID to determine the CPU clk ops and cluster id,
thus we can save the runtime check and string comparison.
Thanks,
Anson.