From: Peng Fan <[email protected]>
Add flexspi, cm33, thermal, cpuidle, reserved memory nodes
Enable flexspi, lpi2c7, spi-nor, cm33 for i.MX8ULP-EVK
Set default clock for SDHC
Haibo Chen (3):
arm64: dts: imx8ulp: add flexspi node
arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC
arm64: dts: imx8ulp-evk: enable lpi2c7 bus
Han Xu (1):
arm64: dts: imx8ulp-evk: add spi-nor device support
Peng Fan (6):
arm64: dts: imx8ulp: add cm33 node
arm64: dts: imx8ulp: set default clock for SDHC
arm64: dts: imx8ulp: add thermal node
arm64: dts: imx8ulp: add cpuidle node
arm64: dts: imx8ulp-evk: add reserved memory for cma
arm64: dts: imx8ulp-evk: enable CM33 node
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 147 ++++++++++++++++--
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 72 ++++++++-
2 files changed, 206 insertions(+), 13 deletions(-)
--
2.37.1
From: Haibo Chen <[email protected]>
Add flexspi node, flexspi has a special memory region mapped to
0x60000000~0x6fffffff. This region is for AHB usage. So add this region
to SoC ranges.
Signed-off-by: Haibo Chen <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 16906c20bce9..4d317029490c 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -194,7 +194,8 @@ soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x40000000>;
+ ranges = <0x0 0x0 0x0 0x40000000>,
+ <0x60000000 0x0 0x60000000 0x1000000>;
s4muap: mailbox@27020000 {
compatible = "fsl,imx8ulp-mu-s4";
@@ -349,6 +350,21 @@ pcc4: clock-controller@29800000 {
#reset-cells = <1>;
};
+ flexspi2: spi@29810000 {
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
+ <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
+ status = "disabled";
+ };
+
lpi2c6: i2c@29840000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29840000 0x10000>;
--
2.37.1
From: Peng Fan <[email protected]>
Enable CM33 node to support rpmsg feature. To use rpmsg, also need
to enable mu node for mailbox doorbell and reserved memory node
for vring, and data buffer. And reserved a piece DRAM memory for case
that m33 images loaded in DRAM.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index e171390a1888..d66e31cf83fe 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -31,6 +31,42 @@ linux,cma {
size = <0 0x28000000>;
linux,cma-default;
};
+
+ m33_reserved: noncacheable-section@a8600000 {
+ reg = <0 0xa8600000 0 0x1000000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@1fff8000{
+ reg = <0 0x1fff8000 0 0x1000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@aff00000 {
+ reg = <0 0xaff00000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@aff08000 {
+ reg = <0 0xaff08000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@aff10000 {
+ reg = <0 0xaff10000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@aff18000 {
+ reg = <0 0xaff18000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a8400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa8400000 0 0x100000>;
+ no-map;
+ };
};
clock_ext_rmii: clock-ext-rmii {
@@ -49,6 +85,16 @@ clock_ext_ts: clock-ext-ts {
};
};
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu 0 1>,
+ <&mu 1 1>,
+ <&mu 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
&lpuart5 {
/* console */
pinctrl-names = "default", "sleep";
@@ -92,6 +138,10 @@ ethphy: ethernet-phy@1 {
};
};
+&mu {
+ status = "okay";
+};
+
&iomuxc1 {
pinctrl_enet: enetgrp {
fsl,pins = <
--
2.37.1
From: Haibo Chen <[email protected]>
Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode
to config the eMMC work at HS400ES mode.
Also update to use Standard Drive Strength for USDHC pad to get a better
signal quality per Hardware team suggests.
Reviewed-by: Sherry Sun <[email protected]>
Signed-off-by: Haibo Chen <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26 ++++++++++---------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index e459dc35e469..ab7af705bbca 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -121,9 +121,11 @@ &lpuart5 {
};
&usdhc0 {
- pinctrl-names = "default", "sleep";
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
non-removable;
bus-width = <8>;
status = "okay";
@@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
- MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
- MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
- MX8ULP_PAD_PTD10__SDHC0_D0 0x43
- MX8ULP_PAD_PTD9__SDHC0_D1 0x43
- MX8ULP_PAD_PTD8__SDHC0_D2 0x43
- MX8ULP_PAD_PTD7__SDHC0_D3 0x43
- MX8ULP_PAD_PTD6__SDHC0_D4 0x43
- MX8ULP_PAD_PTD5__SDHC0_D5 0x43
- MX8ULP_PAD_PTD4__SDHC0_D6 0x43
- MX8ULP_PAD_PTD3__SDHC0_D7 0x43
- MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
+ MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
+ MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
+ MX8ULP_PAD_PTD10__SDHC0_D0 0x3
+ MX8ULP_PAD_PTD9__SDHC0_D1 0x3
+ MX8ULP_PAD_PTD8__SDHC0_D2 0x3
+ MX8ULP_PAD_PTD7__SDHC0_D3 0x3
+ MX8ULP_PAD_PTD6__SDHC0_D4 0x3
+ MX8ULP_PAD_PTD5__SDHC0_D5 0x3
+ MX8ULP_PAD_PTD4__SDHC0_D6 0x3
+ MX8ULP_PAD_PTD3__SDHC0_D7 0x3
+ MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
>;
};
};
--
2.37.1
On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> From: Haibo Chen <[email protected]>
>
> Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode
> to config the eMMC work at HS400ES mode.
>
> Also update to use Standard Drive Strength for USDHC pad to get a better
> signal quality per Hardware team suggests.
>
> Reviewed-by: Sherry Sun <[email protected]>
> Signed-off-by: Haibo Chen <[email protected]>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26 ++++++++++---------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index e459dc35e469..ab7af705bbca 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -121,9 +121,11 @@ &lpuart5 {
> };
>
> &usdhc0 {
> - pinctrl-names = "default", "sleep";
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> pinctrl-0 = <&pinctrl_usdhc0>;
> pinctrl-1 = <&pinctrl_usdhc0>;
> + pinctrl-2 = <&pinctrl_usdhc0>;
> + pinctrl-3 = <&pinctrl_usdhc0>;
All three speed modes use the same pinctrl?
Shawn
> non-removable;
> bus-width = <8>;
> status = "okay";
> @@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
>
> pinctrl_usdhc0: usdhc0grp {
> fsl,pins = <
> - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
> - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
> - MX8ULP_PAD_PTD10__SDHC0_D0 0x43
> - MX8ULP_PAD_PTD9__SDHC0_D1 0x43
> - MX8ULP_PAD_PTD8__SDHC0_D2 0x43
> - MX8ULP_PAD_PTD7__SDHC0_D3 0x43
> - MX8ULP_PAD_PTD6__SDHC0_D4 0x43
> - MX8ULP_PAD_PTD5__SDHC0_D5 0x43
> - MX8ULP_PAD_PTD4__SDHC0_D6 0x43
> - MX8ULP_PAD_PTD3__SDHC0_D7 0x43
> - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
> + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
> + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
> + MX8ULP_PAD_PTD10__SDHC0_D0 0x3
> + MX8ULP_PAD_PTD9__SDHC0_D1 0x3
> + MX8ULP_PAD_PTD8__SDHC0_D2 0x3
> + MX8ULP_PAD_PTD7__SDHC0_D3 0x3
> + MX8ULP_PAD_PTD6__SDHC0_D4 0x3
> + MX8ULP_PAD_PTD5__SDHC0_D5 0x3
> + MX8ULP_PAD_PTD4__SDHC0_D6 0x3
> + MX8ULP_PAD_PTD3__SDHC0_D7 0x3
> + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
> >;
> };
> };
> --
> 2.37.1
>
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: 2023??7??18?? 11:32
> To: Peng Fan (OSS) <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected]; Bough
> Chen <[email protected]>; Sherry Sun <[email protected]>; Peng Fan
> <[email protected]>
> Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz
> pinctrl setting for eMMC
>
> On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> > From: Haibo Chen <[email protected]>
> >
> > Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus
> > mode to config the eMMC work at HS400ES mode.
> >
> > Also update to use Standard Drive Strength for USDHC pad to get a
> > better signal quality per Hardware team suggests.
> >
> > Reviewed-by: Sherry Sun <[email protected]>
> > Signed-off-by: Haibo Chen <[email protected]>
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26
> > ++++++++++---------
> > 1 file changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > index e459dc35e469..ab7af705bbca 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > @@ -121,9 +121,11 @@ &lpuart5 {
> > };
> >
> > &usdhc0 {
> > - pinctrl-names = "default", "sleep";
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> > pinctrl-0 = <&pinctrl_usdhc0>;
> > pinctrl-1 = <&pinctrl_usdhc0>;
> > + pinctrl-2 = <&pinctrl_usdhc0>;
> > + pinctrl-3 = <&pinctrl_usdhc0>;
>
> All three speed modes use the same pinctrl?
Yes, the IOMUX on imx8ulp do not support config different drive strength. So here use the same pinctrl.
Best Regards
Haibo Chen
>
> Shawn
>
> > non-removable;
> > bus-width = <8>;
> > status = "okay";
> > @@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
> >
> > pinctrl_usdhc0: usdhc0grp {
> > fsl,pins = <
> > - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
> > - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
> > - MX8ULP_PAD_PTD10__SDHC0_D0 0x43
> > - MX8ULP_PAD_PTD9__SDHC0_D1 0x43
> > - MX8ULP_PAD_PTD8__SDHC0_D2 0x43
> > - MX8ULP_PAD_PTD7__SDHC0_D3 0x43
> > - MX8ULP_PAD_PTD6__SDHC0_D4 0x43
> > - MX8ULP_PAD_PTD5__SDHC0_D5 0x43
> > - MX8ULP_PAD_PTD4__SDHC0_D6 0x43
> > - MX8ULP_PAD_PTD3__SDHC0_D7 0x43
> > - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
> > + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
> > + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
> > + MX8ULP_PAD_PTD10__SDHC0_D0 0x3
> > + MX8ULP_PAD_PTD9__SDHC0_D1 0x3
> > + MX8ULP_PAD_PTD8__SDHC0_D2 0x3
> > + MX8ULP_PAD_PTD7__SDHC0_D3 0x3
> > + MX8ULP_PAD_PTD6__SDHC0_D4 0x3
> > + MX8ULP_PAD_PTD5__SDHC0_D5 0x3
> > + MX8ULP_PAD_PTD4__SDHC0_D6 0x3
> > + MX8ULP_PAD_PTD3__SDHC0_D7 0x3
> > + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
> > >;
> > };
> > };
> > --
> > 2.37.1
> >
On Mon, Jul 24, 2023 at 06:51:17AM +0000, Bough Chen wrote:
> > -----Original Message-----
> > From: Shawn Guo <[email protected]>
> > Sent: 2023年7月18日 11:32
> > To: Peng Fan (OSS) <[email protected]>
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > dl-linux-imx <[email protected]>; [email protected];
> > [email protected]; [email protected]; Bough
> > Chen <[email protected]>; Sherry Sun <[email protected]>; Peng Fan
> > <[email protected]>
> > Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz
> > pinctrl setting for eMMC
> >
> > On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> > > From: Haibo Chen <[email protected]>
> > >
> > > Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus
> > > mode to config the eMMC work at HS400ES mode.
> > >
> > > Also update to use Standard Drive Strength for USDHC pad to get a
> > > better signal quality per Hardware team suggests.
> > >
> > > Reviewed-by: Sherry Sun <[email protected]>
> > > Signed-off-by: Haibo Chen <[email protected]>
> > > Signed-off-by: Peng Fan <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26
> > > ++++++++++---------
> > > 1 file changed, 14 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > index e459dc35e469..ab7af705bbca 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > @@ -121,9 +121,11 @@ &lpuart5 {
> > > };
> > >
> > > &usdhc0 {
> > > - pinctrl-names = "default", "sleep";
> > > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> > > pinctrl-0 = <&pinctrl_usdhc0>;
> > > pinctrl-1 = <&pinctrl_usdhc0>;
> > > + pinctrl-2 = <&pinctrl_usdhc0>;
> > > + pinctrl-3 = <&pinctrl_usdhc0>;
> >
> > All three speed modes use the same pinctrl?
>
> Yes, the IOMUX on imx8ulp do not support config different drive strength. So here use the same pinctrl.
Mention that in the commit log or with a comment would be helpful.
Shawn