LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He <[email protected]>
---
change in v2:
- Convert bindings to YAML format
.../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.yaml
diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
new file mode 100644
index 000000000000..32274e94aafc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
+
+maintainers:
+ - Wen He <[email protected]>
+
+description: |
+ NXP LS1028A has a clock domain PXLCLK0 used for the Display output
+ interface in the display core, as implemented in TSMC CLN28HPM PLL.
+ which generate and offers pixel clocks to Display.
+
+properties:
+ compatible:
+ const: fsl,ls1028a-plldig
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+examples:
+ # Display PIXEL Clock node:
+ - |
+ dpclk: clock-display@f1f0000 {
+ compatible = "fsl,ls1028a-plldig";
+ reg = <0x0 0xf1f0000 0x0 0xffff>;
+ #clock-cells = <0>;
+ clocks = <&osc_27m>;
+ };
+
+...
--
2.17.1
Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: Wen He <[email protected]>
---
change in v2:
- replace OF archticure register API to platform APIs
- according the maintainer comments correction some typo
drivers/clk/Kconfig | 10 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-plldig.c | 278 +++++++++++++++++++++++++++++++++++++++
3 files changed, 289 insertions(+)
create mode 100644 drivers/clk/clk-plldig.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 801fa1cd0321..3c95d8ec31d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -223,6 +223,16 @@ config CLK_QORIQ
This adds the clock driver support for Freescale QorIQ platforms
using common clock framework.
+config CLK_LS1028A_PLLDIG
+ bool "Clock driver for LS1028A Display output"
+ depends on (ARCH_LAYERSCAPE || COMPILE_TEST) && OF
+ default ARCH_LAYERSCAPE
+ help
+ This driver support the Display output interfaces(LCD, DPHY) pixel clocks
+ of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
+ features of the PLL are currently supported by the driver. By default,
+ configured bypass mode with this PLL.
+
config COMMON_CLK_XGENE
bool "Clock driver for APM XGene SoC"
default ARCH_XGENE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..c8e22a764c4d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
+obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o
obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c
new file mode 100644
index 000000000000..60988b0ea20a
--- /dev/null
+++ b/drivers/clk/clk-plldig.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+/*
+ * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/* PLLDIG register offsets and bit masks */
+#define PLLDIG_REG_PLLSR 0x24
+#define PLLDIG_REG_PLLDV 0x28
+#define PLLDIG_REG_PLLFM 0x2c
+#define PLLDIG_REG_PLLFD 0x30
+#define PLLDIG_REG_PLLCAL1 0x38
+#define PLLDIG_REG_PLLCAL2 0x3c
+#define PLLDIG_DEFAULE_MULT 0x2c
+#define PLLDIG_LOCK_MASK BIT(2)
+#define PLLDIG_SSCGBYP_ENABLE BIT(30)
+#define PLLDIG_FDEN BIT(30)
+#define PLLDIG_DTHRCTL (0x3 << 16)
+
+/* macro to get/set values into register */
+#define PLLDIG_GET_MULT(x) (((x) & ~(0xffffff00)) << 0)
+#define PLLDIG_GET_RFDPHI1(x) ((u32)(x) >> 25)
+#define PLLDIG_SET_RFDPHI1(x) ((u32)(x) << 25)
+
+struct clk_plldig {
+ struct clk_hw hw;
+ void __iomem *regs;
+ struct device *dev;
+};
+#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw)
+#define LOCK_TIMEOUT_US USEC_PER_MSEC
+
+static int plldig_enable(struct clk_hw *hw)
+{
+ struct clk_plldig *data = to_clk_plldig(hw);
+ u32 val;
+
+ val = readl(data->regs + PLLDIG_REG_PLLFM);
+ /*
+ * Use Bypass mode with PLL off by default, the frequency overshoot
+ * detector output was disable. SSCG Bypass mode should be enable.
+ */
+ val |= PLLDIG_SSCGBYP_ENABLE;
+ writel(val, data->regs + PLLDIG_REG_PLLFM);
+
+ val = readl(data->regs + PLLDIG_REG_PLLFD);
+ /* Disable dither and Sigma delta modulation in bypass mode */
+ val |= (PLLDIG_FDEN | PLLDIG_DTHRCTL);
+ writel(val, data->regs + PLLDIG_REG_PLLFD);
+
+ return 0;
+}
+
+static void plldig_disable(struct clk_hw *hw)
+{
+ struct clk_plldig *data = to_clk_plldig(hw);
+ u32 val;
+
+ val = readl(data->regs + PLLDIG_REG_PLLFM);
+
+ val &= ~PLLDIG_SSCGBYP_ENABLE;
+ writel(val, data->regs + PLLDIG_REG_PLLFM);
+}
+
+static int plldig_is_enabled(struct clk_hw *hw)
+{
+ struct clk_plldig *data = to_clk_plldig(hw);
+
+ return (readl(data->regs + PLLDIG_REG_PLLFM) & PLLDIG_SSCGBYP_ENABLE);
+}
+
+/*
+ * Clock configuration relationship between the PHI1 frequency(fpll_phi) and
+ * the output frequency of the PLL is determined by the PLLDV, according to
+ * the following equation:
+ * pxlclk = fpll_phi / RFDPHI1 = (pll_ref x PLLDV[MFD]) / PLLDV[RFDPHI1].
+ */
+static bool plldig_is_valid_range(unsigned long rate, unsigned long parent_rate,
+ unsigned int *mult, unsigned int *rfdphi1,
+ unsigned long *round_rate_base)
+{
+ u32 div, div_temp, mfd = PLLDIG_DEFAULE_MULT;
+ unsigned long round_rate;
+
+ round_rate = parent_rate * mfd;
+
+ /* Range of the divider for driving the PHI1 output clock */
+ for (div = 1; div <= 63; div++) {
+ /* Checking match with default mult number at first */
+ if (round_rate / div == rate) {
+ *rfdphi1 = div;
+ *round_rate_base = round_rate;
+ *mult = mfd;
+ return true;
+ }
+ }
+
+ for (div = 1; div <= 63; div++) {
+ mfd = (div * rate) / parent_rate;
+ /*
+ * Range of the muliplicationthe factor applied to the
+ * output reference frequency
+ */
+ if ((mfd >= 10) && (mfd <= 150)) {
+ div_temp = (parent_rate * mfd) / rate;
+ if ((div_temp * rate) == (mfd * parent_rate)) {
+ *rfdphi1 = div_temp;
+ *mult = mfd;
+ *round_rate_base = mfd * parent_rate;
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+static unsigned long plldig_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_plldig *data = to_clk_plldig(hw);
+ u32 mult, div, val;
+
+ val = readl(data->regs + PLLDIG_REG_PLLDV);
+
+ /* Check if PLL is bypassed */
+ if (val & PLLDIG_SSCGBYP_ENABLE)
+ return parent_rate;
+
+ /* Checkout multiplication factor divider value */
+ mult = val;
+ mult = PLLDIG_GET_MULT(mult);
+
+ /* Checkout divider value of the output frequency */
+ div = val;
+ div = PLLDIG_GET_RFDPHI1(div);
+
+ return (parent_rate * mult) / div;
+}
+
+static long plldig_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent)
+{
+ unsigned long parent_rate = *parent;
+ unsigned long round_rate;
+ u32 mult = 0, rfdphi1 = 0;
+ bool found = false;
+
+ found = plldig_is_valid_range(rate, parent_rate, &mult,
+ &rfdphi1, &round_rate);
+ if (!found) {
+ pr_warn("%s: unable to round rate %lu, parent rate :%lu\n",
+ clk_hw_get_name(hw), rate, parent_rate);
+ return 0;
+ }
+
+ return round_rate / rfdphi1;
+}
+
+static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_plldig *data = to_clk_plldig(hw);
+ bool valid = false;
+ unsigned long round_rate = 0;
+ u32 rfdphi1 = 0, val, mult = 0, cond = 0;
+ int ret = -ETIMEDOUT;
+
+ valid = plldig_is_valid_range(rate, parent_rate, &mult,
+ &rfdphi1, &round_rate);
+ if (!valid) {
+ pr_warn("%s: unable to support rate %lu, parent_rate: %lu\n",
+ clk_hw_get_name(hw), rate, parent_rate);
+ return -EINVAL;
+ }
+
+ val = readl(data->regs + PLLDIG_REG_PLLDV);
+ val = mult;
+ rfdphi1 = PLLDIG_SET_RFDPHI1(rfdphi1);
+ val |= rfdphi1;
+
+ writel(val, data->regs + PLLDIG_REG_PLLDV);
+
+ /* delay 200us make sure that old lock state is cleared */
+ udelay(200);
+
+ /* Wait until PLL is locked or timeout (maximum 1000 usecs) */
+ ret = readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,
+ cond & PLLDIG_LOCK_MASK, 0,
+ USEC_PER_MSEC);
+
+ return ret;
+}
+
+static const struct clk_ops plldig_clk_ops = {
+ .enable = plldig_enable,
+ .disable = plldig_disable,
+ .is_enabled = plldig_is_enabled,
+ .recalc_rate = plldig_recalc_rate,
+ .round_rate = plldig_round_rate,
+ .set_rate = plldig_set_rate,
+};
+
+static int plldig_clk_probe(struct platform_device *pdev)
+{
+ struct clk_plldig *data;
+ struct resource *mem;
+ const char *parent_name;
+ struct clk_init_data init = {};
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->regs = devm_ioremap_resource(dev, mem);
+ if (IS_ERR(data->regs))
+ return PTR_ERR(data->regs);
+
+ init.name = dev->of_node->name;
+ init.ops = &plldig_clk_ops;
+ parent_name = of_clk_get_parent_name(dev->of_node, 0);
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ data->hw.init = &init;
+ data->dev = dev;
+
+ ret = devm_clk_hw_register(dev, &data->hw);
+ if (ret) {
+ dev_err(dev, "failed to register %s clock\n", init.name);
+ return ret;
+ }
+
+ return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
+ &data->hw);
+}
+
+static int plldig_clk_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
+ return 0;
+}
+
+static const struct of_device_id plldig_clk_id[] = {
+ { .compatible = "fsl,ls1028a-plldig", .data = NULL},
+ { }
+};
+
+static struct platform_driver plldig_clk_driver = {
+ .driver = {
+ .name = "plldig-clock",
+ .of_match_table = plldig_clk_id,
+ },
+ .probe = plldig_clk_probe,
+ .remove = plldig_clk_remove,
+};
+module_platform_driver(plldig_clk_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Wen He <[email protected]>");
+MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver");
+MODULE_ALIAS("platform:ls1028a-plldig");
--
2.17.1
The LS1028A has a clock domain PXLCLK0 used for the Display output
interface in the display core, independent of the system bus frequency,
for flexible clock design. This display core has its own pixel clock.
This patch enable the pixel clock provider on the LS1028A.
Signed-off-by: Wen He <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2d31e1c09e74..5218d65588c3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -70,11 +70,18 @@
clock-output-names = "sysclk";
};
- dpclk: clock-dp {
+ osc_27m: clock-osc-27m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
- clock-output-names= "dpclk";
+ clock-output-names = "phy_27m";
+ };
+
+ dpclk: clock-display@f1f0000 {
+ compatible = "fsl,ls1028a-plldig";
+ reg = <0x0 0xf1f0000 0x0 0xffff>;
+ #clock-cells = <0>;
+ clocks = <&osc_27m>;
};
aclk: clock-axi {
--
2.17.1
On Thu, Aug 15, 2019 at 4:26 AM Wen He <[email protected]> wrote:
>
> LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
> output interface. Add a YAML schema for this.
>
> Signed-off-by: Wen He <[email protected]>
> ---
> change in v2:
> - Convert bindings to YAML format
>
> .../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.yaml
Reviewed-by: Rob Herring <[email protected]>
Quoting Wen He (2019-08-15 03:16:11)
> LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
> output interface. Add a YAML schema for this.
>
> Signed-off-by: Wen He <[email protected]>
> ---
Patch looks good. Please send multi-patch series with a cover letter
next time when you resend and pick up Rob's review.
> change in v2:
> - Convert bindings to YAML format
>
Quoting Wen He (2019-08-15 03:16:12)
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 801fa1cd0321..3c95d8ec31d4 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -223,6 +223,16 @@ config CLK_QORIQ
> This adds the clock driver support for Freescale QorIQ platforms
> using common clock framework.
>
> +config CLK_LS1028A_PLLDIG
> + bool "Clock driver for LS1028A Display output"
> + depends on (ARCH_LAYERSCAPE || COMPILE_TEST) && OF
Where is the OF dependency to build anything? Doesn't this still compile
without CONFIG_OF set?
> + default ARCH_LAYERSCAPE
> + help
> + This driver support the Display output interfaces(LCD, DPHY) pixel clocks
> + of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
> + features of the PLL are currently supported by the driver. By default,
> + configured bypass mode with this PLL.
These lines look sort of long. Are they under 80 columns?
> +
> config COMMON_CLK_XGENE
> bool "Clock driver for APM XGene SoC"
> default ARCH_XGENE
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 0cad76021297..c8e22a764c4d 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
> obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
> obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
> obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
> +obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o
> obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
> obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o
> obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
> diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c
> new file mode 100644
> index 000000000000..60988b0ea20a
> --- /dev/null
> +++ b/drivers/clk/clk-plldig.c
> @@ -0,0 +1,278 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright 2019 NXP
> +
> +/*
> + * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
[...]
> +
> +static int plldig_clk_probe(struct platform_device *pdev)
> +{
> + struct clk_plldig *data;
> + struct resource *mem;
> + const char *parent_name;
> + struct clk_init_data init = {};
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->regs = devm_ioremap_resource(dev, mem);
> + if (IS_ERR(data->regs))
> + return PTR_ERR(data->regs);
> +
> + init.name = dev->of_node->name;
> + init.ops = &plldig_clk_ops;
> + parent_name = of_clk_get_parent_name(dev->of_node, 0);
> + init.parent_names = &parent_name;
Can you use the new way of specifying clk parents with the parent_data
member of clk_init?
> + init.num_parents = 1;
> +
> + data->hw.init = &init;
> + data->dev = dev;
> +
> + ret = devm_clk_hw_register(dev, &data->hw);
> + if (ret) {
> + dev_err(dev, "failed to register %s clock\n", init.name);
> + return ret;
> + }
> +
> + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
Use devm? So that driver remove frees this.
> + &data->hw);
> +}
> +
> +static int plldig_clk_remove(struct platform_device *pdev)
> +{
> + of_clk_del_provider(pdev->dev.of_node);
> + return 0;
> +}
> +
> +static const struct of_device_id plldig_clk_id[] = {
> + { .compatible = "fsl,ls1028a-plldig", .data = NULL},
> + { }
> +};
Add a MODULE_DEVICE_TABLE(of, plldig_clk_id) here.
> +
> +static struct platform_driver plldig_clk_driver = {
> + .driver = {
> + .name = "plldig-clock",
> + .of_match_table = plldig_clk_id,
> + },
> + .probe = plldig_clk_probe,
> + .remove = plldig_clk_remove,
> +};
> +module_platform_driver(plldig_clk_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Wen He <[email protected]>");
> +MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver");
> +MODULE_ALIAS("platform:ls1028a-plldig");
Drop MODULE_ALIAS, it's not useful.
> -----Original Message-----
> From: Stephen Boyd <[email protected]>
> Sent: 2019年8月17日 1:47
> To: Mark Rutland <[email protected]>; Michael Turquette
> <[email protected]>; Rob Herring <[email protected]>; Shawn Guo
> <[email protected]>; Wen He <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: Leo Li <[email protected]>; [email protected]; Wen He
> <[email protected]>
> Subject: [EXT] Re: [v2 1/3] dt/bindings: clk: Add YAML schemas for LS1028A
> Display Clock bindings
>
> Caution: EXT Email
>
> Quoting Wen He (2019-08-15 03:16:11)
> > LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to
> > Display output interface. Add a YAML schema for this.
> >
> > Signed-off-by: Wen He <[email protected]>
> > ---
>
> Patch looks good. Please send multi-patch series with a cover letter next time
> when you resend and pick up Rob's review.
Understand, Thank you for the review.
Best Regards,
Wen
>
> > change in v2:
> > - Convert bindings to YAML format
> >
> -----Original Message-----
> From: Stephen Boyd <[email protected]>
> Sent: 2019年8月17日 1:46
> To: Mark Rutland <[email protected]>; Michael Turquette
> <[email protected]>; Rob Herring <[email protected]>; Shawn Guo
> <[email protected]>; Wen He <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: Leo Li <[email protected]>; [email protected]; Wen He
> <[email protected]>
> Subject: [EXT] Re: [v2 2/3] clk: ls1028a: Add clock driver for Display output
> interface
>
> Caution: EXT Email
>
> Quoting Wen He (2019-08-15 03:16:12)
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> > 801fa1cd0321..3c95d8ec31d4 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -223,6 +223,16 @@ config CLK_QORIQ
> > This adds the clock driver support for Freescale QorIQ platforms
> > using common clock framework.
> >
> > +config CLK_LS1028A_PLLDIG
> > + bool "Clock driver for LS1028A Display output"
> > + depends on (ARCH_LAYERSCAPE || COMPILE_TEST) && OF
>
> Where is the OF dependency to build anything? Doesn't this still compile
> without CONFIG_OF set?
Yes, current included some APIs of the OF, like of_get_parent_name()
>
> > + default ARCH_LAYERSCAPE
> > + help
> > + This driver support the Display output interfaces(LCD, DPHY)
> pixel clocks
> > + of the QorIQ Layerscape LS1028A, as implemented TSMC
> CLN28HPM PLL. Not all
> > + features of the PLL are currently supported by the driver. By
> default,
> > + configured bypass mode with this PLL.
>
> These lines look sort of long. Are they under 80 columns?
>
Yes, they had been checked by the checkpatch.pl.
> > +
> > config COMMON_CLK_XGENE
> > bool "Clock driver for APM XGene SoC"
> > default ARCH_XGENE
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> > 0cad76021297..c8e22a764c4d 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS)
> += clk-oxnas.o
> > obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
> > obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
> > obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
> > +obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o
> > obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
> > obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o
> > obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
> > diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c new
> > file mode 100644 index 000000000000..60988b0ea20a
> > --- /dev/null
> > +++ b/drivers/clk/clk-plldig.c
> > @@ -0,0 +1,278 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright 2019 NXP
> > +
> > +/*
> > + * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/device.h>
> > +#include <linux/module.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/of.h>
> [...]
> > +
> > +static int plldig_clk_probe(struct platform_device *pdev) {
> > + struct clk_plldig *data;
> > + struct resource *mem;
> > + const char *parent_name;
> > + struct clk_init_data init = {};
> > + struct device *dev = &pdev->dev;
> > + int ret;
> > +
> > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > + if (!data)
> > + return -ENOMEM;
> > +
> > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + data->regs = devm_ioremap_resource(dev, mem);
> > + if (IS_ERR(data->regs))
> > + return PTR_ERR(data->regs);
> > +
> > + init.name = dev->of_node->name;
> > + init.ops = &plldig_clk_ops;
> > + parent_name = of_clk_get_parent_name(dev->of_node, 0);
> > + init.parent_names = &parent_name;
>
> Can you use the new way of specifying clk parents with the parent_data
> member of clk_init?
Of course, but I don't understand why need recommend to use this member?
Is that the member parent_names will be discard in future?
Here are definition of the clk-provider.h
/* Only one of the following three should be assigned */
const char * const *parent_names;
const struct clk_parent_data *parent_data;
const struct clk_hw **parent_hws;
For PLLDIG, it only has one parent.
>
> > + init.num_parents = 1;
> > +
> > + data->hw.init = &init;
> > + data->dev = dev;
> > +
> > + ret = devm_clk_hw_register(dev, &data->hw);
> > + if (ret) {
> > + dev_err(dev, "failed to register %s clock\n", init.name);
> > + return ret;
> > + }
> > +
> > + return of_clk_add_hw_provider(dev->of_node,
> > + of_clk_hw_simple_get,
>
> Use devm? So that driver remove frees this.
Yes, here also should be using devm_of_clk_add_hw_provider().
>
> > + &data->hw);
> > +}
> > +
> > +static int plldig_clk_remove(struct platform_device *pdev) {
> > + of_clk_del_provider(pdev->dev.of_node);
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id plldig_clk_id[] = {
> > + { .compatible = "fsl,ls1028a-plldig", .data = NULL},
> > + { }
> > +};
>
> Add a MODULE_DEVICE_TABLE(of, plldig_clk_id) here.
>
OK,
> > +
> > +static struct platform_driver plldig_clk_driver = {
> > + .driver = {
> > + .name = "plldig-clock",
> > + .of_match_table = plldig_clk_id,
> > + },
> > + .probe = plldig_clk_probe,
> > + .remove = plldig_clk_remove,
> > +};
> > +module_platform_driver(plldig_clk_driver);
> > +
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_AUTHOR("Wen He <[email protected]>");
> > +MODULE_DESCRIPTION("LS1028A Display output interface pixel clock
> > +driver"); MODULE_ALIAS("platform:ls1028a-plldig");
>
> Drop MODULE_ALIAS, it's not useful.
OK,
Best Regards,
Wen
Quoting Wen He (2019-08-19 00:30:49)
> > Quoting Wen He (2019-08-15 03:16:12)
> > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> > > 801fa1cd0321..3c95d8ec31d4 100644
> > > --- a/drivers/clk/Kconfig
> > > +++ b/drivers/clk/Kconfig
> > > @@ -223,6 +223,16 @@ config CLK_QORIQ
> > > This adds the clock driver support for Freescale QorIQ platforms
> > > using common clock framework.
> > >
> > > +config CLK_LS1028A_PLLDIG
> > > + bool "Clock driver for LS1028A Display output"
> > > + depends on (ARCH_LAYERSCAPE || COMPILE_TEST) && OF
> >
> > Where is the OF dependency to build anything? Doesn't this still compile
> > without CONFIG_OF set?
>
> Yes, current included some APIs of the OF, like of_get_parent_name()
And there isn't a stub API for of_get_parent_name when OF isn't defined?
> > > +
> > > +static int plldig_clk_probe(struct platform_device *pdev) {
> > > + struct clk_plldig *data;
> > > + struct resource *mem;
> > > + const char *parent_name;
> > > + struct clk_init_data init = {};
> > > + struct device *dev = &pdev->dev;
> > > + int ret;
> > > +
> > > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > > + if (!data)
> > > + return -ENOMEM;
> > > +
> > > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > + data->regs = devm_ioremap_resource(dev, mem);
> > > + if (IS_ERR(data->regs))
> > > + return PTR_ERR(data->regs);
> > > +
> > > + init.name = dev->of_node->name;
> > > + init.ops = &plldig_clk_ops;
> > > + parent_name = of_clk_get_parent_name(dev->of_node, 0);
> > > + init.parent_names = &parent_name;
> >
> > Can you use the new way of specifying clk parents with the parent_data
> > member of clk_init?
>
> Of course, but I don't understand why need recommend to use this member?
> Is that the member parent_names will be discard in future?
>
> Here are definition of the clk-provider.h
> /* Only one of the following three should be assigned */
> const char * const *parent_names;
> const struct clk_parent_data *parent_data;
> const struct clk_hw **parent_hws;
>
> For PLLDIG, it only has one parent.
Yes. Can you use clk_parent_data array and specify a DT index of 0 and
some name that would go into "clock-names" in the .fw_name member?
> -----Original Message-----
> From: Stephen Boyd <[email protected]>
> Sent: 2019年8月20日 2:30
> To: [email protected]; [email protected];
> [email protected]; [email protected]; Mark Rutland
> <[email protected]>; Michael Turquette <[email protected]>;
> Rob Herring <[email protected]>; Shawn Guo <[email protected]>; Wen
> He <[email protected]>
> Cc: Leo Li <[email protected]>; [email protected]
> Subject: RE: [EXT] Re: [v2 2/3] clk: ls1028a: Add clock driver for Display output
> interface
>
> Caution: EXT Email
>
> Quoting Wen He (2019-08-19 00:30:49)
> > > Quoting Wen He (2019-08-15 03:16:12)
> > > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> > > > 801fa1cd0321..3c95d8ec31d4 100644
> > > > --- a/drivers/clk/Kconfig
> > > > +++ b/drivers/clk/Kconfig
> > > > @@ -223,6 +223,16 @@ config CLK_QORIQ
> > > > This adds the clock driver support for Freescale QorIQ
> platforms
> > > > using common clock framework.
> > > >
> > > > +config CLK_LS1028A_PLLDIG
> > > > + bool "Clock driver for LS1028A Display output"
> > > > + depends on (ARCH_LAYERSCAPE || COMPILE_TEST) && OF
> > >
> > > Where is the OF dependency to build anything? Doesn't this still
> > > compile without CONFIG_OF set?
> >
> > Yes, current included some APIs of the OF, like of_get_parent_name()
>
> And there isn't a stub API for of_get_parent_name when OF isn't defined?
You are right, should be remove OF dependency.
>
> > > > +
> > > > +static int plldig_clk_probe(struct platform_device *pdev) {
> > > > + struct clk_plldig *data;
> > > > + struct resource *mem;
> > > > + const char *parent_name;
> > > > + struct clk_init_data init = {};
> > > > + struct device *dev = &pdev->dev;
> > > > + int ret;
> > > > +
> > > > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > > > + if (!data)
> > > > + return -ENOMEM;
> > > > +
> > > > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > + data->regs = devm_ioremap_resource(dev, mem);
> > > > + if (IS_ERR(data->regs))
> > > > + return PTR_ERR(data->regs);
> > > > +
> > > > + init.name = dev->of_node->name;
> > > > + init.ops = &plldig_clk_ops;
> > > > + parent_name = of_clk_get_parent_name(dev->of_node, 0);
> > > > + init.parent_names = &parent_name;
> > >
> > > Can you use the new way of specifying clk parents with the
> > > parent_data member of clk_init?
> >
> > Of course, but I don't understand why need recommend to use this member?
> > Is that the member parent_names will be discard in future?
> >
> > Here are definition of the clk-provider.h
> > /* Only one of the following three should be assigned */
> > const char * const *parent_names;
> > const struct clk_parent_data *parent_data;
> > const struct clk_hw **parent_hws;
> >
> > For PLLDIG, it only has one parent.
>
> Yes. Can you use clk_parent_data array and specify a DT index of 0 and some
> name that would go into "clock-names" in the .fw_name member?
OK, but .fw_name used for to registering clk, current it registered with fixed clk in dts .
I think should be specify a DT index of 0 and specify the unique name for .name member.
I found have two ways to specify:
1. declare clk_parent_data variable parent_data, and initialization with clk_init_data, like this:
parent_data.name = of_clk_get_parent_name(dev->of_node, 0);
parent_data.index = 0;
init.name = dev->of_node->name;
init.ops = &plldig_clk_ops;
init.parent_data = &parent_data;
init.num_parents = 1;
2. Or use a static const array for here? And put the unique name and index like this.
static const struct clk_parent_data parent_data[] = {
{.name = "phy_27m", .index = 0},
};
After then initialization with macro CLK_HW_INIT_PARENTS_DATA?
Best Regards,
Wen
Quoting Wen He (2019-08-19 19:24:25)
>
> >
> > > > > +
> > > > > +static int plldig_clk_probe(struct platform_device *pdev) {
> > > > > + struct clk_plldig *data;
> > > > > + struct resource *mem;
> > > > > + const char *parent_name;
> > > > > + struct clk_init_data init = {};
> > > > > + struct device *dev = &pdev->dev;
> > > > > + int ret;
> > > > > +
> > > > > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > > > > + if (!data)
> > > > > + return -ENOMEM;
> > > > > +
> > > > > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > > + data->regs = devm_ioremap_resource(dev, mem);
> > > > > + if (IS_ERR(data->regs))
> > > > > + return PTR_ERR(data->regs);
> > > > > +
> > > > > + init.name = dev->of_node->name;
> > > > > + init.ops = &plldig_clk_ops;
> > > > > + parent_name = of_clk_get_parent_name(dev->of_node, 0);
> > > > > + init.parent_names = &parent_name;
> > > >
> > > > Can you use the new way of specifying clk parents with the
> > > > parent_data member of clk_init?
> > >
> > > Of course, but I don't understand why need recommend to use this member?
> > > Is that the member parent_names will be discard in future?
> > >
> > > Here are definition of the clk-provider.h
> > > /* Only one of the following three should be assigned */
> > > const char * const *parent_names;
> > > const struct clk_parent_data *parent_data;
> > > const struct clk_hw **parent_hws;
> > >
> > > For PLLDIG, it only has one parent.
> >
> > Yes. Can you use clk_parent_data array and specify a DT index of 0 and some
> > name that would go into "clock-names" in the .fw_name member?
>
> OK, but .fw_name used for to registering clk, current it registered with fixed clk in dts .
> I think should be specify a DT index of 0 and specify the unique name for .name member.
>
> I found have two ways to specify:
> 1. declare clk_parent_data variable parent_data, and initialization with clk_init_data, like this:
>
> parent_data.name = of_clk_get_parent_name(dev->of_node, 0);
This isn't preferred because of_clk_get_parent_name() is DT specific and
relies on the parent clk being registered before calling the function so
that we can figure out the globally unique name.
> parent_data.index = 0;
>
> init.name = dev->of_node->name;
> init.ops = &plldig_clk_ops;
> init.parent_data = &parent_data;
> init.num_parents = 1;
>
> 2. Or use a static const array for here? And put the unique name and index like this.
> static const struct clk_parent_data parent_data[] = {
> {.name = "phy_27m", .index = 0},
> };
>
> After then initialization with macro CLK_HW_INIT_PARENTS_DATA?
Yes use option #2. But, don't even specify a .name if this is new code
because .name is a fallback mechanism that is supposed to be used if
you're migrating code from an older DT to a newer DT. I don't think
that's happening here.