The patchset contains driver and devicetree changes to support I2C and
PWM for Tegra234
v2->v1:
* Reverted changes in i2c-tegra.c. using tegra194_i2c_hw for tegra234
as the values are compatible.
Akhil R (4):
dt-bindings: Add headers for Tegra234 I2C
arm64: tegra: Add Tegra234 I2C devicetree nodes
dt-bindings: Add headers for Tegra234 PWM
arm64: tegra: Add Tegra234 PWM devicetree nodes
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 133 +++++++++++++++++++++++++++++
include/dt-bindings/clock/tegra234-clock.h | 36 ++++++++
include/dt-bindings/reset/tegra234-reset.h | 16 ++++
3 files changed, 185 insertions(+)
--
2.7.4
Add dt-bindings header files for I2C controllers for Tegra234
Signed-off-by: Akhil R <[email protected]>
---
include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++
include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
2 files changed, 27 insertions(+)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 8d7e66e..5d05c19 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -30,5 +30,24 @@
#define TEGRA234_CLK_PLLC4 237U
/** @brief 32K input clock provided by PMIC */
#define TEGRA234_CLK_CLK_32K 289U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
+#define TEGRA234_CLK_I2C1 48U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
+#define TEGRA234_CLK_I2C2 49U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
+#define TEGRA234_CLK_I2C3 50U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
+#define TEGRA234_CLK_I2C4 51U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA234_CLK_I2C6 52U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
+#define TEGRA234_CLK_I2C7 53U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
+#define TEGRA234_CLK_I2C8 54U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
+#define TEGRA234_CLK_I2C9 55U
+
+/** @brief PLLP clk output */
+#define TEGRA234_CLK_PLLP_OUT0 102U
#endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 50e13bc..e07e898 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -12,6 +12,14 @@
*/
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_UARTA 100U
+#define TEGRA234_RESET_I2C1 24U
+#define TEGRA234_RESET_I2C2 29U
+#define TEGRA234_RESET_I2C3 30U
+#define TEGRA234_RESET_I2C4 31U
+#define TEGRA234_RESET_I2C6 32U
+#define TEGRA234_RESET_I2C7 33U
+#define TEGRA234_RESET_I2C8 34U
+#define TEGRA234_RESET_I2C9 35U
/** @} */
--
2.7.4
Add device tree nodes for Tegra234 I2C controllers
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 6b6f1580..c686827 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -144,6 +144,96 @@
status = "disabled";
};
+ gen1_i2c: i2c@3160000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x3160000 0x100>;
+ status = "disabled";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C1
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C1>;
+ reset-names = "i2c";
+ };
+
+ cam_i2c: i2c@3180000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x3180000 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <400000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C3
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C3>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch1_i2c: i2c@3190000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x3190000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C4
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C4>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch0_i2c: i2c@31b0000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x31b0000 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C6
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C6>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch2_i2c: i2c@31c0000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x31c0000 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C7
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C7>;
+ reset-names = "i2c";
+ };
+
+ dp_aux_ch3_i2c: i2c@31e0000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0x31e0000 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C9
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ resets = <&bpmp TEGRA234_RESET_I2C9>;
+ reset-names = "i2c";
+ };
+
mmc@3460000 {
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03460000 0x20000>;
@@ -212,6 +302,37 @@
#mbox-cells = <2>;
};
+ gen2_i2c: i2c@c240000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0xc240000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <100000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C2
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ resets = <&bpmp TEGRA234_RESET_I2C2>;
+ reset-names = "i2c";
+ };
+
+ gen8_i2c: i2c@c250000 {
+ compatible = "nvidia,tegra194-i2c";
+ reg = <0xc250000 0x100>;
+ nvidia,hw-instance-id = <0x7>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clock-frequency = <400000>;
+ clocks = <&bpmp TEGRA234_CLK_I2C8
+ &bpmp TEGRA234_CLK_PLLP_OUT0>;
+ clock-names = "div-clk", "parent";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ resets = <&bpmp TEGRA234_RESET_I2C8>;
+ reset-names = "i2c";
+ };
+
rtc@c2a0000 {
compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
reg = <0x0c2a0000 0x10000>;
--
2.7.4
Add dt-bindings header files for PWM of Tegra234
Signed-off-by: Akhil R <[email protected]>
---
include/dt-bindings/clock/tegra234-clock.h | 17 +++++++++++++++++
include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
2 files changed, 25 insertions(+)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 5d05c19..9d17309 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -50,4 +50,21 @@
/** @brief PLLP clk output */
#define TEGRA234_CLK_PLLP_OUT0 102U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA234_CLK_PWM1 105U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA234_CLK_PWM2 106U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA234_CLK_PWM3 107U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA234_CLK_PWM4 108U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA234_CLK_PWM5 109U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA234_CLK_PWM6 110U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA234_CLK_PWM7 111U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA234_CLK_PWM8 112U
+
#endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index e07e898..288524f 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -20,6 +20,14 @@
#define TEGRA234_RESET_I2C7 33U
#define TEGRA234_RESET_I2C8 34U
#define TEGRA234_RESET_I2C9 35U
+#define TEGRA234_RESET_PWM1 68U
+#define TEGRA234_RESET_PWM2 69U
+#define TEGRA234_RESET_PWM3 70U
+#define TEGRA234_RESET_PWM4 71U
+#define TEGRA234_RESET_PWM5 72U
+#define TEGRA234_RESET_PWM6 73U
+#define TEGRA234_RESET_PWM7 74U
+#define TEGRA234_RESET_PWM8 75U
/** @} */
--
2.7.4
Add device tree nodes for Tegra234 PWM
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index c686827..cbebf1e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -234,6 +234,18 @@
reset-names = "i2c";
};
+ pwm1: pwm@3280000 {
+ compatible = "nvidia,tegra194-pwm",
+ "nvidia,tegra186-pwm";
+ reg = <0x3280000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM1>;
+ clock-names = "pwm";
+ resets = <&bpmp TEGRA234_RESET_PWM1>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
mmc@3460000 {
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03460000 0x20000>;
--
2.7.4
22.01.2022 14:23, Akhil R пишет:
> Add dt-bindings header files for I2C controllers for Tegra234
>
> Signed-off-by: Akhil R <[email protected]>
> ---
> include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++
> include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
> 2 files changed, 27 insertions(+)
>
> diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
> index 8d7e66e..5d05c19 100644
> --- a/include/dt-bindings/clock/tegra234-clock.h
> +++ b/include/dt-bindings/clock/tegra234-clock.h
> @@ -30,5 +30,24 @@
> #define TEGRA234_CLK_PLLC4 237U
> /** @brief 32K input clock provided by PMIC */
> #define TEGRA234_CLK_CLK_32K 289U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
> +#define TEGRA234_CLK_I2C1 48U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
> +#define TEGRA234_CLK_I2C2 49U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
> +#define TEGRA234_CLK_I2C3 50U
> +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
> +#define TEGRA234_CLK_I2C4 51U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
> +#define TEGRA234_CLK_I2C6 52U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
> +#define TEGRA234_CLK_I2C7 53U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
> +#define TEGRA234_CLK_I2C8 54U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
> +#define TEGRA234_CLK_I2C9 55U
> +
> +/** @brief PLLP clk output */
> +#define TEGRA234_CLK_PLLP_OUT0 102U
>
> #endif
> diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
> index 50e13bc..e07e898 100644
> --- a/include/dt-bindings/reset/tegra234-reset.h
> +++ b/include/dt-bindings/reset/tegra234-reset.h
> @@ -12,6 +12,14 @@
> */
> #define TEGRA234_RESET_SDMMC4 85U
> #define TEGRA234_RESET_UARTA 100U
> +#define TEGRA234_RESET_I2C1 24U
> +#define TEGRA234_RESET_I2C2 29U
> +#define TEGRA234_RESET_I2C3 30U
> +#define TEGRA234_RESET_I2C4 31U
> +#define TEGRA234_RESET_I2C6 32U
> +#define TEGRA234_RESET_I2C7 33U
> +#define TEGRA234_RESET_I2C8 34U
> +#define TEGRA234_RESET_I2C9 35U
Why ID order isn't maintained?
> > Add dt-bindings header files for I2C controllers for Tegra234
> >
> > Signed-off-by: Akhil R <[email protected]>
> > ---
> > include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++
> > include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
> > 2 files changed, 27 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/tegra234-clock.h
> > b/include/dt-bindings/clock/tegra234-clock.h
> > index 8d7e66e..5d05c19 100644
> > --- a/include/dt-bindings/clock/tegra234-clock.h
> > +++ b/include/dt-bindings/clock/tegra234-clock.h
> > @@ -30,5 +30,24 @@
> > #define TEGRA234_CLK_PLLC4 237U
> > /** @brief 32K input clock provided by PMIC */
> > #define TEGRA234_CLK_CLK_32K 289U
> > +/** @brief output of mux controlled by
> CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
> > +#define TEGRA234_CLK_I2C1 48U
> > +/** @brief output of mux controlled by
> CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
> > +#define TEGRA234_CLK_I2C2 49U
> > +/** @brief output of mux controlled by
> CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
> > +#define TEGRA234_CLK_I2C3 50U
> > +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4
> */
> > +#define TEGRA234_CLK_I2C4 51U
> > +/** @brief output of mux controlled by
> CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
> > +#define TEGRA234_CLK_I2C6 52U
> > +/** @brief output of mux controlled by
> CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
> > +#define TEGRA234_CLK_I2C7 53U
> > +/** @brief output of mux controlled by
> CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
> > +#define TEGRA234_CLK_I2C8 54U
> > +/** @brief output of mux controlled by
> CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
> > +#define TEGRA234_CLK_I2C9 55U
> > +
> > +/** @brief PLLP clk output */
> > +#define TEGRA234_CLK_PLLP_OUT0 102U
> >
> > #endif
> > diff --git a/include/dt-bindings/reset/tegra234-reset.h
> > b/include/dt-bindings/reset/tegra234-reset.h
> > index 50e13bc..e07e898 100644
> > --- a/include/dt-bindings/reset/tegra234-reset.h
> > +++ b/include/dt-bindings/reset/tegra234-reset.h
> > @@ -12,6 +12,14 @@
> > */
> > #define TEGRA234_RESET_SDMMC4 85U
> > #define TEGRA234_RESET_UARTA 100U
> > +#define TEGRA234_RESET_I2C1 24U
> > +#define TEGRA234_RESET_I2C2 29U
> > +#define TEGRA234_RESET_I2C3 30U
> > +#define TEGRA234_RESET_I2C4 31U
> > +#define TEGRA234_RESET_I2C6 32U
> > +#define TEGRA234_RESET_I2C7 33U
> > +#define TEGRA234_RESET_I2C8 34U
> > +#define TEGRA234_RESET_I2C9 35U
>
> Why ID order isn't maintained?
Do you mean RESET_UART4, SDMMC4 etc should be
below RESET_I2C*?
Regards,
Akhil
--
nvpublic
23.01.2022 19:56, Akhil R пишет:
>>> Add dt-bindings header files for I2C controllers for Tegra234
>>>
>>> Signed-off-by: Akhil R <[email protected]>
>>> ---
>>> include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++
>>> include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++
>>> 2 files changed, 27 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/clock/tegra234-clock.h
>>> b/include/dt-bindings/clock/tegra234-clock.h
>>> index 8d7e66e..5d05c19 100644
>>> --- a/include/dt-bindings/clock/tegra234-clock.h
>>> +++ b/include/dt-bindings/clock/tegra234-clock.h
>>> @@ -30,5 +30,24 @@
>>> #define TEGRA234_CLK_PLLC4 237U
>>> /** @brief 32K input clock provided by PMIC */
>>> #define TEGRA234_CLK_CLK_32K 289U
>>> +/** @brief output of mux controlled by
>> CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
>>> +#define TEGRA234_CLK_I2C1 48U
>>> +/** @brief output of mux controlled by
>> CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
>>> +#define TEGRA234_CLK_I2C2 49U
>>> +/** @brief output of mux controlled by
>> CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
>>> +#define TEGRA234_CLK_I2C3 50U
>>> +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4
>> */
>>> +#define TEGRA234_CLK_I2C4 51U
>>> +/** @brief output of mux controlled by
>> CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
>>> +#define TEGRA234_CLK_I2C6 52U
>>> +/** @brief output of mux controlled by
>> CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
>>> +#define TEGRA234_CLK_I2C7 53U
>>> +/** @brief output of mux controlled by
>> CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
>>> +#define TEGRA234_CLK_I2C8 54U
>>> +/** @brief output of mux controlled by
>> CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
>>> +#define TEGRA234_CLK_I2C9 55U
>>> +
>>> +/** @brief PLLP clk output */
>>> +#define TEGRA234_CLK_PLLP_OUT0 102U
>>>
>>> #endif
>>> diff --git a/include/dt-bindings/reset/tegra234-reset.h
>>> b/include/dt-bindings/reset/tegra234-reset.h
>>> index 50e13bc..e07e898 100644
>>> --- a/include/dt-bindings/reset/tegra234-reset.h
>>> +++ b/include/dt-bindings/reset/tegra234-reset.h
>>> @@ -12,6 +12,14 @@
>>> */
>>> #define TEGRA234_RESET_SDMMC4 85U
>>> #define TEGRA234_RESET_UARTA 100U
>>> +#define TEGRA234_RESET_I2C1 24U
>>> +#define TEGRA234_RESET_I2C2 29U
>>> +#define TEGRA234_RESET_I2C3 30U
>>> +#define TEGRA234_RESET_I2C4 31U
>>> +#define TEGRA234_RESET_I2C6 32U
>>> +#define TEGRA234_RESET_I2C7 33U
>>> +#define TEGRA234_RESET_I2C8 34U
>>> +#define TEGRA234_RESET_I2C9 35U
>>
>> Why ID order isn't maintained?
> Do you mean RESET_UART4, SDMMC4 etc should be
> below RESET_I2C*?
Yes, please see T186/194 headers for the example and do the same for
T234. Always try to use existing examples in general to maintain
consistency.