-Added standard mode for AXI I2C controller.
-Added Smbus block read support to xiic driver.
-Added 'xlnx,axi-iic-2.1' new IP version support.
-Added dynamic SCL frequency configuration support.
-Removed 'local_irq_save/restore' calls as discussed
here: https://www.spinics.net/lists/linux-i2c/msg46483.html.
-Corrected the BNB interrupt enable sequence.
Raviteja Narayanam (11):
i2c: xiic: Add standard mode support for > 255 byte read transfers
i2c: xiic: Enter standard mode only for > 255 byte read transfers
i2c: xiic: Fix Rx and Tx paths in standard mode repeated start
i2c: xiic: Add wait for FIFO empty in send_tx
i2c: xiic: Use 'nmsgs' variable instead of repeated_start
i2c: xiic: Add smbus_block_read functionality
i2c: xiic: Switch to Xiic standard mode for i2c-read
i2c: xiic: Remove interrupt enable/disable in Rx path
dt-bindings: i2c: xiic: Add 'xlnx,axi-iic-2.1' to compatible
i2c: xiic: Update compatible with new IP version
i2c: xiic: Add SCL frequency configuration support
Srinivas Goud (1):
i2c: xiic: Correct the BNB interrupt enable sequence
.../bindings/i2c/xlnx,xps-iic-2.00.a.yaml | 4 +-
drivers/i2c/busses/i2c-xiic.c | 631 ++++++++++++++++--
2 files changed, 578 insertions(+), 57 deletions(-)
--
2.25.1
From: Raviteja Narayanam <[email protected]>
Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads.
Older IPs are handled with a workaround in which they are using
xiic standard mode for all these effected use cases.
Added the xilinx I2C new version 'xlnx,axi-iic-2.1' string to
compatible.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
.../devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
index 715dcfa5a922..e516c1ed358c 100644
--- a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+++ b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
@@ -14,7 +14,9 @@ allOf:
properties:
compatible:
- const: xlnx,xps-iic-2.00.a
+ enum:
+ - xlnx,xps-iic-2.00.a
+ - xlnx,axi-iic-2.1
reg:
maxItems: 1
--
2.25.1
From: Raviteja Narayanam <[email protected]>
When a combined message request comes from user space, the
controller has to initiate repeated start sequence. In standard
mode, this repeated start sequence is corrupted if there is still
data in the Tx FIFO.
So, always make sure that all the bytes are completely transmitted
out of the FIFO by waiting for TXEMPTY, if the previous message is
of Tx type.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 54 +++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index c8b68176427c..2d5214f1ba03 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -62,6 +62,7 @@ enum xiic_endian {
* @singlemaster: Indicates bus is single master
* @dynamic: Mode of controller
* @repeated_start: Repeated start operation
+ * @prev_msg_tx: Previous message is Tx
*/
struct xiic_i2c {
struct device *dev;
@@ -80,6 +81,7 @@ struct xiic_i2c {
bool singlemaster;
bool dynamic;
bool repeated_start;
+ bool prev_msg_tx;
};
#define XIIC_MSB_OFFSET 0
@@ -282,6 +284,24 @@ static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
return 0;
}
+static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
+{
+ u8 isr;
+ unsigned long timeout;
+
+ timeout = jiffies + XIIC_I2C_TIMEOUT;
+ for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
+ !(isr & XIIC_INTR_TX_EMPTY_MASK);
+ isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) {
+ if (time_after(jiffies, timeout)) {
+ dev_err(i2c->dev, "Timeout waiting at Tx empty\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
static int xiic_reinit(struct xiic_i2c *i2c)
{
int ret;
@@ -731,6 +751,20 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
local_irq_restore(flags);
} else {
+ /*
+ * If previous message is Tx, make sure that Tx FIFO is empty
+ * before starting a new transfer as the repeated start in
+ * standard mode can corrupt the transaction if there are
+ * still bytes to be transmitted in FIFO
+ */
+ if (i2c->prev_msg_tx) {
+ int status;
+
+ status = xiic_wait_tx_empty(i2c);
+ if (status)
+ return;
+ }
+
cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
/* Set Receive fifo depth */
@@ -784,6 +818,8 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
/* Enable interrupts */
xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
+
+ i2c->prev_msg_tx = false;
}
static void xiic_start_send(struct xiic_i2c *i2c)
@@ -820,6 +856,20 @@ static void xiic_start_send(struct xiic_i2c *i2c)
xiic_fill_tx_fifo(i2c);
} else {
+ /*
+ * If previous message is Tx, make sure that Tx FIFO is empty
+ * before starting a new transfer as the repeated start in
+ * standard mode can corrupt the transaction if there are
+ * still bytes to be transmitted in FIFO
+ */
+ if (i2c->prev_msg_tx) {
+ int status;
+
+ status = xiic_wait_tx_empty(i2c);
+ if (status)
+ return;
+ }
+
/* Check if RSTA should be set */
cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
if (cr & XIIC_CR_MSMS_MASK) {
@@ -853,6 +903,7 @@ static void xiic_start_send(struct xiic_i2c *i2c)
XIIC_INTR_TX_ERROR_MASK |
XIIC_INTR_BNB_MASK);
}
+ i2c->prev_msg_tx = true;
}
static void __xiic_start_xfer(struct xiic_i2c *i2c)
@@ -916,6 +967,9 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
/* Decide standard mode or Dynamic mode */
i2c->dynamic = true;
+ /* Initialize prev message type */
+ i2c->prev_msg_tx = false;
+
/* Enter standard mode only when read length is > 255 bytes */
for (count = 0; count < i2c->nmsgs; count++) {
if ((i2c->tx_msg[count].flags & I2C_M_RD) &&
--
2.25.1
From: Raviteja Narayanam <[email protected]>
From 'clock-frequency' device tree property, configure I2C SCL
frequency by calculating the timing register values according to
input clock.
After soft reset in reinit function, the timing registers are set
to default values (configured in vivado design). So, setting SCL
frequency is done inside reinit function after the soft reset.
This allows configuration of SCL frequency exclusively through
software via device tree property, overriding the vivado design.
If the clock-frequency parameter is not specified in DT, driver
doesn't configure frequency, making it backward compatible.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 149 ++++++++++++++++++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index f9492c39d3c7..f29acabba5e7 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -65,6 +65,8 @@ enum xiic_endian {
* @prev_msg_tx: Previous message is Tx
* @smbus_block_read: Flag to handle block read
* @quirks: To hold platform specific bug info
+ * @input_clk: Input clock to I2C controller
+ * @i2c_clk: I2C SCL frequency
*/
struct xiic_i2c {
struct device *dev;
@@ -85,12 +87,30 @@ struct xiic_i2c {
bool prev_msg_tx;
bool smbus_block_read;
u32 quirks;
+ unsigned long input_clk;
+ unsigned int i2c_clk;
};
struct xiic_version_data {
u32 quirks;
};
+/**
+ * struct timing_regs - AXI I2C timing registers that depend on I2C spec
+ * @tsusta: setup time for a repeated START condition
+ * @tsusto: setup time for a STOP condition
+ * @thdsta: hold time for a repeated START condition
+ * @tsudat: setup time for data
+ * @tbuf: bus free time between STOP and START
+ */
+struct timing_regs {
+ unsigned int tsusta;
+ unsigned int tsusto;
+ unsigned int thdsta;
+ unsigned int tsudat;
+ unsigned int tbuf;
+};
+
#define XIIC_MSB_OFFSET 0
#define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET)
@@ -109,6 +129,19 @@ struct xiic_version_data {
#define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
#define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */
+/*
+ * Timing register offsets from RegisterBase. These are used only for
+ * setting i2c clock frequency for the line.
+ */
+#define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */
+#define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */
+#define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */
+#define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */
+#define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */
+#define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */
+#define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */
+#define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */
+
/* Control Register masks */
#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
@@ -190,6 +223,7 @@ struct xiic_version_data {
static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
static void __xiic_start_xfer(struct xiic_i2c *i2c);
+static int xiic_setclk(struct xiic_i2c *i2c);
/*
* For the register read and write functions, a little-endian and big-endian
@@ -315,6 +349,10 @@ static int xiic_reinit(struct xiic_i2c *i2c)
xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
+ ret = xiic_setclk(i2c);
+ if (ret)
+ return ret;
+
/* Set receive Fifo depth to maximum (zero based). */
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
@@ -1118,6 +1156,105 @@ static const struct of_device_id xiic_of_match[] = {
MODULE_DEVICE_TABLE(of, xiic_of_match);
#endif
+enum i2c_scl_freq {
+ REG_VALUES_100KHZ = 0,
+ REG_VALUES_400KHZ = 1,
+ REG_VALUES_1MHZ = 2
+};
+
+/* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
+static const struct timing_regs timing_reg_values[] = {
+ { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */
+ { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */
+ { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */
+};
+
+/**
+ * xiic_setclk - Sets the configured clock rate
+ * @i2c: Pointer to the xiic device structure
+ *
+ * The timing register values are calculated according to the input clock
+ * frequency and configured scl frequency. For details, please refer the
+ * AXI I2C PG and NXP I2C Spec.
+ * Supported frequencies are 100KHz, 400KHz and 1MHz.
+ *
+ * Return: 0 on success (Supported frequency selected or not configurable in SW)
+ * -EINVAL on failure (scl frequency not supported or THIGH is 0)
+ */
+static int xiic_setclk(struct xiic_i2c *i2c)
+{
+ unsigned int clk_in_mhz;
+ unsigned int index = 0;
+ u32 reg_val;
+
+ dev_dbg(i2c->adap.dev.parent,
+ "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
+ __func__, i2c->input_clk, i2c->i2c_clk);
+
+ /* If not specified in DT, do not configure in SW. Rely only on Vivado design */
+ if (!i2c->i2c_clk)
+ return 0;
+
+ clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
+
+ switch (i2c->i2c_clk) {
+ case I2C_MAX_FAST_MODE_PLUS_FREQ:
+ index = REG_VALUES_1MHZ;
+ break;
+ case I2C_MAX_FAST_MODE_FREQ:
+ index = REG_VALUES_400KHZ;
+ break;
+ case I2C_MAX_STANDARD_MODE_FREQ:
+ index = REG_VALUES_100KHZ;
+ break;
+ default:
+ dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Value to be stored in a register is the number of clock cycles required
+ * for the time duration. So the time is divided by the input clock time
+ * period to get the number of clock cycles required. Refer Xilinx AXI I2C
+ * PG document and I2C specification for further details.
+ */
+
+ /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */
+ reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
+ if (reg_val == 0)
+ return -EINVAL;
+
+ xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
+
+ /* TLOW - Value same as THIGH */
+ xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
+
+ /* TSUSTA */
+ reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
+
+ /* TSUSTO */
+ reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
+
+ /* THDSTA */
+ reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
+
+ /* TSUDAT */
+ reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
+
+ /* TBUF */
+ reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
+
+ /* THDDAT */
+ xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
+
+ return 0;
+}
+
static int xiic_i2c_probe(struct platform_device *pdev)
{
struct xiic_i2c *i2c;
@@ -1176,6 +1313,15 @@ static int xiic_i2c_probe(struct platform_device *pdev)
pm_runtime_use_autosuspend(i2c->dev);
pm_runtime_set_active(i2c->dev);
pm_runtime_enable(i2c->dev);
+
+ /* SCL frequency configuration */
+ i2c->input_clk = clk_get_rate(i2c->clk);
+ ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
+ &i2c->i2c_clk);
+ /* If clock-frequency not specified in DT, do not configure in SW */
+ if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
+ i2c->i2c_clk = 0;
+
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
xiic_process, IRQF_ONESHOT,
pdev->name, i2c);
@@ -1219,6 +1365,9 @@ static int xiic_i2c_probe(struct platform_device *pdev)
i2c_new_client_device(&i2c->adap, pdata->devices + i);
}
+ dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n",
+ (unsigned long)res->start, irq, i2c->i2c_clk);
+
return 0;
err_clk_dis:
--
2.25.1
From: Raviteja Narayanam <[email protected]>
smbus_block_read is added to xiic driver to read from few sensors
which support this command. Since the number of bytes to read is not
known prior to transfer, we are using xiic standard mode for low level
control of IP.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 82 ++++++++++++++++++++++++++++++++---
1 file changed, 76 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 3debb44608cf..57ede62de67d 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -62,6 +62,7 @@ enum xiic_endian {
* @singlemaster: Indicates bus is single master
* @dynamic: Mode of controller
* @prev_msg_tx: Previous message is Tx
+ * @smbus_block_read: Flag to handle block read
*/
struct xiic_i2c {
struct device *dev;
@@ -80,6 +81,7 @@ struct xiic_i2c {
bool singlemaster;
bool dynamic;
bool prev_msg_tx;
+ bool smbus_block_read;
};
#define XIIC_MSB_OFFSET 0
@@ -339,6 +341,54 @@ static void xiic_deinit(struct xiic_i2c *i2c)
xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
}
+static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
+{
+ u8 rxmsg_len;
+ u8 rfd_set = 0;
+
+ /*
+ * Clear the I2C_M_RECV_LEN flag to avoid setting
+ * message length again
+ */
+ i2c->rx_msg->flags &= ~I2C_M_RECV_LEN;
+
+ /* Set smbus_block_read flag to identify in isr */
+ i2c->smbus_block_read = true;
+
+ /* Read byte from rx fifo and set message length */
+ rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
+
+ i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len;
+
+ /* Check if received length is valid */
+ if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) {
+ /* Set Receive fifo depth */
+ if (rxmsg_len > IIC_RX_FIFO_DEPTH) {
+ rfd_set = IIC_RX_FIFO_DEPTH - 1;
+ i2c->rx_msg->len = rxmsg_len + 1;
+ } else if ((rxmsg_len == 1) ||
+ (rxmsg_len == 0)) {
+ /*
+ * Minimum of 3 bytes required to exit cleanly. 1 byte
+ * already received, Second byte is being received. Have
+ * to set NACK in read_rx before receiving the last byte
+ */
+ i2c->rx_msg->len = 3;
+ } else {
+ rfd_set = rxmsg_len - 2;
+ i2c->rx_msg->len = rxmsg_len + 1;
+ }
+ xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
+
+ return;
+ }
+
+ /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */
+ i2c->tx_msg->len = 3;
+ i2c->smbus_block_read = false;
+ dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n");
+}
+
static void xiic_read_rx(struct xiic_i2c *i2c)
{
u8 bytes_in_fifo, cr = 0, bytes_to_read = 0;
@@ -361,6 +411,12 @@ static void xiic_read_rx(struct xiic_i2c *i2c)
if (!i2c->dynamic) {
bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo;
+ /* Set msg length if smbus_block_read */
+ if (i2c->rx_msg->flags & I2C_M_RECV_LEN) {
+ xiic_smbus_block_read_setup(i2c);
+ return;
+ }
+
if (bytes_rem > IIC_RX_FIFO_DEPTH) {
bytes_to_read = bytes_in_fifo;
} else if (bytes_rem > 1) {
@@ -638,6 +694,12 @@ static irqreturn_t xiic_process(int irq, void *dev_id)
/* The bus is not busy, disable BusNotBusy interrupt */
xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
+ if (i2c->tx_msg && i2c->smbus_block_read) {
+ i2c->smbus_block_read = false;
+ /* Set requested message len=1 to indicate STATE_DONE */
+ i2c->tx_msg->len = 1;
+ }
+
if (!i2c->tx_msg)
goto out;
@@ -777,8 +839,12 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
rfd_set = IIC_RX_FIFO_DEPTH - 1;
} else if ((rx_watermark == 1) || (rx_watermark == 0)) {
rfd_set = rx_watermark - 1;
- /* Handle single byte transfer separately */
- cr |= XIIC_CR_NO_ACK_MASK;
+
+ /* Set No_ACK, except for smbus_block_read */
+ if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) {
+ /* Handle single byte transfer separately */
+ cr |= XIIC_CR_NO_ACK_MASK;
+ }
} else {
rfd_set = rx_watermark - 2;
}
@@ -970,10 +1036,14 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
/* Initialize prev message type */
i2c->prev_msg_tx = false;
- /* Enter standard mode only when read length is > 255 bytes */
+ /*
+ * Enter standard mode only when read length is > 255 bytes or
+ * for smbus_block_read transaction
+ */
for (count = 0; count < i2c->nmsgs; count++) {
- if ((i2c->tx_msg[count].flags & I2C_M_RD) &&
- i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC) {
+ if (((i2c->tx_msg[count].flags & I2C_M_RD) &&
+ i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC) ||
+ (i2c->tx_msg[count].flags & I2C_M_RECV_LEN)) {
i2c->dynamic = false;
break;
}
@@ -1007,7 +1077,7 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
static u32 xiic_func(struct i2c_adapter *adap)
{
- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
}
static const struct i2c_algorithm xiic_algorithm = {
--
2.25.1
From: Raviteja Narayanam <[email protected]>
Xilinx I2C IP has two modes of operation, both of which implement
I2C transactions. The only difference from sw perspective is the
programming sequence for these modes.
Dynamic mode -> Simple to program, less number of steps in sequence.
Standard mode -> Gives flexibility, more number of steps in sequence.
In dynamic mode, during the i2c-read transactions, if there is a
delay(> 200us) between the register writes (address & byte count),
read transaction fails. On a system with load, this scenario is
occurring frequently.
To avoid this, switch to standard mode if there is a read request.
Added a quirk to identify the IP version effected by this and follow
the standard mode.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 87 +++++++++++++++++++++++------------
1 file changed, 58 insertions(+), 29 deletions(-)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 57ede62de67d..74cd50478694 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -32,6 +32,7 @@
#include <linux/pm_runtime.h>
#define DRIVER_NAME "xiic-i2c"
+#define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
enum xilinx_i2c_state {
STATE_DONE,
@@ -63,6 +64,7 @@ enum xiic_endian {
* @dynamic: Mode of controller
* @prev_msg_tx: Previous message is Tx
* @smbus_block_read: Flag to handle block read
+ * @quirks: To hold platform specific bug info
*/
struct xiic_i2c {
struct device *dev;
@@ -82,6 +84,11 @@ struct xiic_i2c {
bool dynamic;
bool prev_msg_tx;
bool smbus_block_read;
+ u32 quirks;
+};
+
+struct xiic_version_data {
+ u32 quirks;
};
#define XIIC_MSB_OFFSET 0
@@ -995,7 +1002,8 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c)
static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
{
- int ret;
+ bool broken_read, max_read_len, smbus_blk_read;
+ int ret, count;
mutex_lock(&i2c->lock);
@@ -1008,6 +1016,34 @@ static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
i2c->nmsgs = num;
init_completion(&i2c->completion);
+ /* Decide standard mode or Dynamic mode */
+ i2c->dynamic = true;
+
+ /* Initialize prev message type */
+ i2c->prev_msg_tx = false;
+
+ /*
+ * Scan through nmsgs, use dynamic mode when none of the below three
+ * conditions occur. We need standard mode even if one condition holds
+ * true in the entire array of messages in a single transfer.
+ * If read transaction as dynamic mode is broken for delayed reads
+ * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions.
+ * If read length is > 255 bytes.
+ * If smbus_block_read transaction.
+ */
+ for (count = 0; count < i2c->nmsgs; count++) {
+ broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) &&
+ (i2c->tx_msg[count].flags & I2C_M_RD);
+ max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) &&
+ (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC);
+ smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN);
+
+ if (broken_read || max_read_len || smbus_blk_read) {
+ i2c->dynamic = false;
+ break;
+ }
+ }
+
ret = xiic_reinit(i2c);
if (!ret)
__xiic_start_xfer(i2c);
@@ -1021,7 +1057,7 @@ static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct xiic_i2c *i2c = i2c_get_adapdata(adap);
- int err, count;
+ int err;
dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
@@ -1030,25 +1066,6 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
if (err < 0)
return err;
- /* Decide standard mode or Dynamic mode */
- i2c->dynamic = true;
-
- /* Initialize prev message type */
- i2c->prev_msg_tx = false;
-
- /*
- * Enter standard mode only when read length is > 255 bytes or
- * for smbus_block_read transaction
- */
- for (count = 0; count < i2c->nmsgs; count++) {
- if (((i2c->tx_msg[count].flags & I2C_M_RD) &&
- i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC) ||
- (i2c->tx_msg[count].flags & I2C_M_RECV_LEN)) {
- i2c->dynamic = false;
- break;
- }
- }
-
err = xiic_start_xfer(i2c, msgs, num);
if (err < 0) {
dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
@@ -1091,10 +1108,23 @@ static const struct i2c_adapter xiic_adapter = {
.algo = &xiic_algorithm,
};
+static const struct xiic_version_data xiic_2_00 = {
+ .quirks = DYNAMIC_MODE_READ_BROKEN_BIT,
+};
+
+#if defined(CONFIG_OF)
+static const struct of_device_id xiic_of_match[] = {
+ { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xiic_of_match);
+#endif
+
static int xiic_i2c_probe(struct platform_device *pdev)
{
struct xiic_i2c *i2c;
struct xiic_i2c_platform_data *pdata;
+ const struct of_device_id *match;
struct resource *res;
int ret, irq;
u8 i;
@@ -1104,6 +1134,13 @@ static int xiic_i2c_probe(struct platform_device *pdev)
if (!i2c)
return -ENOMEM;
+ match = of_match_node(xiic_of_match, pdev->dev.of_node);
+ if (match && match->data) {
+ const struct xiic_version_data *data = match->data;
+
+ i2c->quirks = data->quirks;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
i2c->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(i2c->base))
@@ -1215,14 +1252,6 @@ static int xiic_i2c_remove(struct platform_device *pdev)
return 0;
}
-#if defined(CONFIG_OF)
-static const struct of_device_id xiic_of_match[] = {
- { .compatible = "xlnx,xps-iic-2.00.a", },
- {},
-};
-MODULE_DEVICE_TABLE(of, xiic_of_match);
-#endif
-
static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
{
struct xiic_i2c *i2c = dev_get_drvdata(dev);
--
2.25.1
From: Raviteja Narayanam <[email protected]>
As the 'DYNAMIC_MODE_READ_BROKEN_BIT' quirk is added in the driver,
we no longer enter dynamic mode for the effected IP versions.
So, remove local_irq_save/local_irq_restore APIs from driver.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 74cd50478694..720aa671f74b 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -776,7 +776,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
u16 rx_watermark;
u8 cr = 0, rfd_set = 0;
struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
- unsigned long flags;
dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
__func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
@@ -808,7 +807,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
- local_irq_save(flags);
if (!(msg->flags & I2C_M_NOSTART))
/* write the address */
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
@@ -822,7 +820,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
val |= msg->len;
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
- local_irq_restore(flags);
} else {
/*
* If previous message is Tx, make sure that Tx FIFO is empty
--
2.25.1
From: Raviteja Narayanam <[email protected]>
If the tx_half_empty interrupt comes first instead of tx_empty,
STOP bit is generated even before all the bytes are transmitted
out on the bus.
STOP bit should be sent only after all the bytes in the FIFO are
transmitted out of the FIFO. So wait until FIFO is empty before sending
the STOP bit.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 2d5214f1ba03..9c3266ac209e 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -472,6 +472,12 @@ static void xiic_send_tx(struct xiic_i2c *i2c)
if (i2c->nmsgs == 1) {
u8 cr;
+ int status;
+
+ /* Wait till FIFO is empty so STOP is sent last */
+ status = xiic_wait_tx_empty(i2c);
+ if (status)
+ return;
/* Write to CR to stop */
cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
--
2.25.1
From: Srinivas Goud <[email protected]>
With updated AXI IIC IP core(v2.1)there is change in IP behavior
in dynamic mode, where controller initiate read transfer on IIC
bus only after getting the value for the number of bytes to receive.
In the existing xiic_start_recv function Bus Not Busy(BNB)
interrupt is enabled just after "slave address + start"
write to FIFO and before the "count + stop"write to FIFO.
Since IIC controller drives the start address of a transaction
on the bus only after it has received the byte count information
the above sequence can lead to spurious BNB interrupt in case
there is any delay after "slave address + start" write to FIFO.
This is fixed by ensuring that BNB interrupt is enabled only
after "count + stop" has been written to FIFO.
Signed-off-by: Srinivas Goud <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index f29acabba5e7..0a34daa9e372 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -851,13 +851,13 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
i2c_8bit_addr_from_msg(msg) |
XIIC_TX_DYN_START_MASK);
- xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
-
/* If last message, include dynamic stop bit with length */
val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
val |= msg->len;
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
+
+ xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
} else {
/*
* If previous message is Tx, make sure that Tx FIFO is empty
--
2.25.1
From: Raviteja Narayanam <[email protected]>
Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads.
Older IPs are handled with a workaround in which they are using
xiic standard mode for all these effected use cases.
Added the new IP version to compatible.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
---
drivers/i2c/busses/i2c-xiic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 720aa671f74b..f9492c39d3c7 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -1112,6 +1112,7 @@ static const struct xiic_version_data xiic_2_00 = {
#if defined(CONFIG_OF)
static const struct of_device_id xiic_of_match[] = {
{ .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
+ { .compatible = "xlnx,axi-iic-2.1", },
{},
};
MODULE_DEVICE_TABLE(of, xiic_of_match);
--
2.25.1
W dniu 24.06.2022 o 14:05, Manikanta Guntupalli pisze:
> From: Raviteja Narayanam <[email protected]>
>
> smbus_block_read is added to xiic driver to read from few sensors
> which support this command. Since the number of bytes to read is not
> known prior to transfer, we are using xiic standard mode for low level
> control of IP.
>
> Signed-off-by: Raviteja Narayanam <[email protected]>
> Signed-off-by: Manikanta Guntupalli <[email protected]>
I have successfully tested the patches from this series up until this
one so:
Tested-by: Krzysztof Adamski <[email protected]>
W dniu 24.06.2022 o 14:05, Manikanta Guntupalli pisze:
> From: Srinivas Goud <[email protected]>
>
> With updated AXI IIC IP core(v2.1)there is change in IP behavior
> in dynamic mode, where controller initiate read transfer on IIC
> bus only after getting the value for the number of bytes to receive.
>
> In the existing xiic_start_recv function Bus Not Busy(BNB)
> interrupt is enabled just after "slave address + start"
> write to FIFO and before the "count + stop"write to FIFO.
> Since IIC controller drives the start address of a transaction
> on the bus only after it has received the byte count information
> the above sequence can lead to spurious BNB interrupt in case
> there is any delay after "slave address + start" write to FIFO.
>
> This is fixed by ensuring that BNB interrupt is enabled only
> after "count + stop" has been written to FIFO.
>
> Signed-off-by: Srinivas Goud <[email protected]>
> Signed-off-by: Manikanta Guntupalli <[email protected]>
> ---
[...]
Does this spurious interrupt cause any trouble or it is just ignored and
the only problem is unneeded extra CPU load?
Krzysztof
Hi Krzysztof,
> -----Original Message-----
> From: Krzysztof Adamski <[email protected]>
> Sent: Wednesday, June 29, 2022 6:44 PM
> To: Manikanta Guntupalli <[email protected]>;
> [email protected]; Simek, Michal <[email protected]>; linux-
> [email protected]; [email protected]; linux-
> [email protected]; git (AMD-Xilinx) <[email protected]>
> Cc: Srinivas Goud <[email protected]>
> Subject: Re: [PATCH 12/12] i2c: xiic: Correct the BNB interrupt enable
> sequence
>
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
>
>
> W dniu 24.06.2022 o 14:05, Manikanta Guntupalli pisze:
> > From: Srinivas Goud <[email protected]>
> >
> > With updated AXI IIC IP core(v2.1)there is change in IP behavior in
> > dynamic mode, where controller initiate read transfer on IIC bus only
> > after getting the value for the number of bytes to receive.
> >
> > In the existing xiic_start_recv function Bus Not Busy(BNB) interrupt
> > is enabled just after "slave address + start"
> > write to FIFO and before the "count + stop"write to FIFO.
> > Since IIC controller drives the start address of a transaction on the
> > bus only after it has received the byte count information the above
> > sequence can lead to spurious BNB interrupt in case there is any delay
> > after "slave address + start" write to FIFO.
> >
> > This is fixed by ensuring that BNB interrupt is enabled only after
> > "count + stop" has been written to FIFO.
> >
> > Signed-off-by: Srinivas Goud <[email protected]>
> > Signed-off-by: Manikanta Guntupalli <[email protected]>
> > ---
>
> [...]
>
> Does this spurious interrupt cause any trouble or it is just ignored and the
> only problem is unneeded extra CPU load?
>
No functional issue we just corrected the sequence as per IP changes.
> Krzysztof
Thanks,
Manikanta.