From: Peng Fan <[email protected]>
This patchset is to add more blk ctrl support for i.MX8MP
- Add HDMI HDCP/HRV BLK CTRL support
- Add VPU BLK CTRL support
- Add PGC VPU node which supplies power domain for VPU BLK
This patchset is based on:
https://lore.kernel.org/all/[email protected]/
repo: https://github.com/MrVan/linux/tree/imx8mp-blk-ctrl
Peng Fan (6):
dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV
dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV
soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl
arm64: dts: imx8mp: add vpu pgc nodes
arm64: dts: imx8mp: add VPU blk ctrl node
.../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 17 +++++--
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 45 ++++++++++++++++++
drivers/soc/imx/imx8m-blk-ctrl.c | 47 +++++++++++++++++++
drivers/soc/imx/imx8mp-blk-ctrl.c | 30 ++++++++++++
include/dt-bindings/power/imx8mp-power.h | 6 +++
5 files changed, 142 insertions(+), 3 deletions(-)
--
2.25.1
From: Peng Fan <[email protected]>
i.MX8MP HDMI supports HDCP and HRV, so add them.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/soc/imx/imx8mp-blk-ctrl.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 6f983adcb47c..527d45d12a54 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -235,6 +235,13 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
break;
+ case IMX8MP_HDMIBLK_PD_HDCP:
+ regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
+ break;
+ case IMX8MP_HDMIBLK_PD_HRV:
+ regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
+ regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
+ break;
default:
break;
}
@@ -283,6 +290,13 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
break;
+ case IMX8MP_HDMIBLK_PD_HDCP:
+ regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
+ break;
+ case IMX8MP_HDMIBLK_PD_HRV:
+ regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
+ regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
+ break;
default:
break;
}
@@ -365,6 +379,22 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
.num_clks = 2,
.gpc_name = "hdmi-tx-phy",
},
+ [IMX8MP_HDMIBLK_PD_HRV] = {
+ .name = "hdmiblk-hrv",
+ .clk_names = (const char *[]){ "axi", "apb" },
+ .num_clks = 2,
+ .gpc_name = "hrv",
+ .path_names = (const char *[]){"hrv"},
+ .num_paths = 1,
+ },
+ [IMX8MP_HDMIBLK_PD_HDCP] = {
+ .name = "hdmiblk-hdcp",
+ .clk_names = (const char *[]){ "axi", "apb" },
+ .num_clks = 2,
+ .gpc_name = "hdcp",
+ .path_names = (const char *[]){"hdcp"},
+ .num_paths = 1,
+ },
};
static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {
--
2.25.1
From: Peng Fan <[email protected]>
i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
the i.MX8MM VPU blk ctrl yaml file.
Signed-off-by: Peng Fan <[email protected]>
---
.../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 17 ++++++++++++++---
include/dt-bindings/power/imx8mp-power.h | 4 ++++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
index 26487daa64d9..edbd267cdd67 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
@@ -4,20 +4,22 @@
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: NXP i.MX8MM VPU blk-ctrl
+title: NXP i.MX8MM/P VPU blk-ctrl
maintainers:
- Lucas Stach <[email protected]>
description:
- The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
+ The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing access to
the NoC and ensuring proper power sequencing of the VPU peripherals
located in the VPU domain of the SoC.
properties:
compatible:
items:
- - const: fsl,imx8mm-vpu-blk-ctrl
+ - enum:
+ - fsl,imx8mm-vpu-blk-ctrl
+ - fsl,imx8mp-vpu-blk-ctrl
- const: syscon
reg:
@@ -47,6 +49,15 @@ properties:
- const: g2
- const: h1
+ interconnects:
+ maxItems: 3
+
+ interconnect-names:
+ items:
+ - const: g1
+ - const: g2
+ - const: h1
+
required:
- compatible
- reg
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 14b9c5ac9c82..11d43fc7a18e 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -52,4 +52,8 @@
#define IMX8MP_HDMIBLK_PD_HDCP 7
#define IMX8MP_HDMIBLK_PD_HRV 8
+#define IMX8MP_VPUBLK_PD_G1 0
+#define IMX8MP_VPUBLK_PD_G2 1
+#define IMX8MP_VPUBLK_PD_H1 2
+
#endif
--
2.25.1
On Tue, Jul 12, 2022 at 3:20 AM Peng Fan (OSS) <[email protected]> wrote:
>
> From: Peng Fan <[email protected]>
>
> i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
> the i.MX8MM VPU blk ctrl yaml file.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 17 ++++++++++++++---
> include/dt-bindings/power/imx8mp-power.h | 4 ++++
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> index 26487daa64d9..edbd267cdd67 100644
> --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> @@ -4,20 +4,22 @@
> $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: NXP i.MX8MM VPU blk-ctrl
> +title: NXP i.MX8MM/P VPU blk-ctrl
>
> maintainers:
> - Lucas Stach <[email protected]>
>
> description:
> - The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
> + The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing access to
> the NoC and ensuring proper power sequencing of the VPU peripherals
> located in the VPU domain of the SoC.
>
> properties:
> compatible:
> items:
> - - const: fsl,imx8mm-vpu-blk-ctrl
> + - enum:
> + - fsl,imx8mm-vpu-blk-ctrl
> + - fsl,imx8mp-vpu-blk-ctrl
> - const: syscon
>
> reg:
> @@ -47,6 +49,15 @@ properties:
> - const: g2
> - const: h1
>
> + interconnects:
> + maxItems: 3
> +
> + interconnect-names:
> + items:
> + - const: g1
> + - const: g2
> + - const: h1
> +
> required:
> - compatible
> - reg
> diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
> index 14b9c5ac9c82..11d43fc7a18e 100644
> --- a/include/dt-bindings/power/imx8mp-power.h
> +++ b/include/dt-bindings/power/imx8mp-power.h
> @@ -52,4 +52,8 @@
> #define IMX8MP_HDMIBLK_PD_HDCP 7
> #define IMX8MP_HDMIBLK_PD_HRV 8
>
> +#define IMX8MP_VPUBLK_PD_G1 0
> +#define IMX8MP_VPUBLK_PD_G2 1
> +#define IMX8MP_VPUBLK_PD_H1 2
Is H1 even correct for 8MP? The TRM calls the encoder a VC800E. Since
the Encoder on the 8MM is a Hantro H1, this might add confusion if
people start thinking they are the same.
> +
> #endif
> --
> 2.25.1
>
> Subject: Re: [PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
>
> On Tue, Jul 12, 2022 at 3:20 AM Peng Fan (OSS) <[email protected]>
> wrote:
> >
> > From: Peng Fan <[email protected]>
> >
> > i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
> > the i.MX8MM VPU blk ctrl yaml file.
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> > .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 17 ++++++++++++++---
> > include/dt-bindings/power/imx8mp-power.h | 4 ++++
> > 2 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctrl.ya
> > ml
> > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctrl.ya
> > ml index 26487daa64d9..edbd267cdd67 100644
> > ---
> > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctrl.ya
> > ml
> > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctr
> > +++ l.yaml
> > @@ -4,20 +4,22 @@
> > $id:
> >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevic
> > etree.org%2Fschemas%2Fsoc%2Fimx%2Ffsl%2Cimx8mm-vpu-blk-
> ctrl.yaml%23&am
> >
> p;data=05%7C01%7Cpeng.fan%40nxp.com%7Cc99b7cd9f40b4e5ecf8a08da6
> 3ffb350
> > %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63793224713390
> 0894%7CUnk
> >
> nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6I
> k1haWw
> >
> iLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=uiVz0so%2BdmCPhOu
> I3Lf1cJBfs0
> > kmBYa5J4Ak8uWxk%2Fk%3D&reserved=0
> > $schema:
> >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevic
> > etree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=05%7C01%7Cpeng.fan%40
> >
> nxp.com%7Cc99b7cd9f40b4e5ecf8a08da63ffb350%7C686ea1d3bc2b4c6fa92
> cd99c5
> >
> c301635%7C0%7C0%7C637932247133900894%7CUnknown%7CTWFpbGZsb
> 3d8eyJWIjoiM
> >
> C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000
> %7C%7C
> > %7C&sdata=4y71i22hEKKd8D16qHOMsK%2F%2FDfsV1IL17iioMm9lw
> %2Fk%3D&
> > ;reserved=0
> >
> > -title: NXP i.MX8MM VPU blk-ctrl
> > +title: NXP i.MX8MM/P VPU blk-ctrl
> >
> > maintainers:
> > - Lucas Stach <[email protected]>
> >
> > description:
> > - The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access
> > to
> > + The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing
> > + access to
> > the NoC and ensuring proper power sequencing of the VPU peripherals
> > located in the VPU domain of the SoC.
> >
> > properties:
> > compatible:
> > items:
> > - - const: fsl,imx8mm-vpu-blk-ctrl
> > + - enum:
> > + - fsl,imx8mm-vpu-blk-ctrl
> > + - fsl,imx8mp-vpu-blk-ctrl
> > - const: syscon
> >
> > reg:
> > @@ -47,6 +49,15 @@ properties:
> > - const: g2
> > - const: h1
> >
> > + interconnects:
> > + maxItems: 3
> > +
> > + interconnect-names:
> > + items:
> > + - const: g1
> > + - const: g2
> > + - const: h1
> > +
> > required:
> > - compatible
> > - reg
> > diff --git a/include/dt-bindings/power/imx8mp-power.h
> > b/include/dt-bindings/power/imx8mp-power.h
> > index 14b9c5ac9c82..11d43fc7a18e 100644
> > --- a/include/dt-bindings/power/imx8mp-power.h
> > +++ b/include/dt-bindings/power/imx8mp-power.h
> > @@ -52,4 +52,8 @@
> > #define IMX8MP_HDMIBLK_PD_HDCP 7
> > #define IMX8MP_HDMIBLK_PD_HRV 8
> >
> > +#define IMX8MP_VPUBLK_PD_G1 0
> > +#define IMX8MP_VPUBLK_PD_G2 1
> > +#define IMX8MP_VPUBLK_PD_H1 2
>
> Is H1 even correct for 8MP? The TRM calls the encoder a VC800E. Since the
> Encoder on the 8MM is a Hantro H1, this might add confusion if people start
> thinking they are the same.
VC8000E should be used, I'll update.
Thanks,
Peng.
> > +
> > #endif
> > --
> > 2.25.1
> >