From: Conor Dooley <[email protected]>
The RISC-V ISA Manual allows for the first Additional Standard
Extension having no leading underscore. Only if there are multiple
Additional Standard Extensions is it needed to have an underscore.
The dt-binding does not validate that a multi-letter extension is
canonically ordered, as that'd need an even worse regex than is here,
but it should not fail validation for valid ISA strings.
Allow the first Z multi-letter extension to appear immediately prior
after the single-letter extensions.
Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 90a7cabf58fe..e80c967a4fa4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -80,7 +80,7 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing.
$ref: "/schemas/types.yaml#/definitions/string"
- pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.38.1
On 30 Nov 2022, at 18:04, Conor Dooley <[email protected]> wrote:
>
> From: Conor Dooley <[email protected]>
>
> The RISC-V ISA Manual allows for the first Additional Standard
> Extension having no leading underscore. Only if there are multiple
> Additional Standard Extensions is it needed to have an underscore.
>
> The dt-binding does not validate that a multi-letter extension is
> canonically ordered, as that'd need an even worse regex than is here,
> but it should not fail validation for valid ISA strings.
>
> Allow the first Z multi-letter extension to appear immediately prior
> after the single-letter extensions.
>
> Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> Acked-by: Guo Ren <[email protected]>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 90a7cabf58fe..e80c967a4fa4 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -80,7 +80,7 @@ properties:
> insensitive, letters in the riscv,isa string must be all
> lowercase to simplify parsing.
> $ref: "/schemas/types.yaml#/definitions/string"
> - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
> + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
It certainly used to be at least; we use rv64gcxcheri...
Jess
On Wed, Nov 30, 2022 at 06:29:18PM +0000, Jessica Clarke wrote:
> On 30 Nov 2022, at 18:04, Conor Dooley <[email protected]> wrote:
> >
> > From: Conor Dooley <[email protected]>
> >
> > The RISC-V ISA Manual allows for the first Additional Standard
> > Extension having no leading underscore. Only if there are multiple
> > Additional Standard Extensions is it needed to have an underscore.
> >
> > The dt-binding does not validate that a multi-letter extension is
> > canonically ordered, as that'd need an even worse regex than is here,
> > but it should not fail validation for valid ISA strings.
> >
> > Allow the first Z multi-letter extension to appear immediately prior
> > after the single-letter extensions.
> >
> > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> > Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> > Acked-by: Guo Ren <[email protected]>
> > Signed-off-by: Conor Dooley <[email protected]>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 90a7cabf58fe..e80c967a4fa4 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -80,7 +80,7 @@ properties:
> > insensitive, letters in the riscv,isa string must be all
> > lowercase to simplify parsing.
> > $ref: "/schemas/types.yaml#/definitions/string"
> > - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
> > + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
>
> Isn’t it any multi-letter extension, i.e, this should be [hsxz] again?
>
> It certainly used to be at least; we use rv64gcxcheri...
<quote>
Non-standard extensions must be listed after all standard extensions.
They must be separated from other multi-letter extensions
by an underscore
<\quote>
Nope, you're right. I realised that the other day with the non-binding
series that was a response to v1. I had that itching feeling that I had
forgotten to do something when I was writing my changelog but could not
remember what...
Thanks Jess!