The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
minimal device tree files for this board to make it boot to a basic
shell.
Signed-off-by: Thomas Bonnefille <[email protected]>
---
Thomas Bonnefille (5):
dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
dt-bindings: timer: Add SOPHGO SG2002 clint
dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
riscv: dts: sophgo: Add initial SG2002 SoC device tree
riscv: dts: sophgo: Add LicheeRV Nano board device tree
.../interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/sophgo.yaml | 4 +++
.../devicetree/bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/sophgo/Makefile | 1 +
.../boot/dts/sophgo/sg2002-lichee-rv-nano.dts | 25 ++++++++++++++++++
arch/riscv/boot/dts/sophgo/sg2002.dtsi | 30 ++++++++++++++++++++++
6 files changed, 62 insertions(+)
---
base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
change-id: 20240515-sg2002-93dce1d263be
Best regards,
--
Thomas Bonnefille <[email protected]>
Add compatible string for SOPHGO SG2002 Core-Local Interrupt Controller.
Signed-off-by: Thomas Bonnefille <[email protected]>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index fced6f2d8ecb..b42d43d2de48 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -40,6 +40,7 @@ properties:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
- sophgo,cv1812h-clint
+ - sophgo,sg2002-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:
--
2.45.1
Document the compatible strings for the Sipeed LicheeRV Nano board which
uses the SOPHGO SG2002 SoC.
Signed-off-by: Thomas Bonnefille <[email protected]>
---
Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
index 9bc813dad098..b770ead6c723 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -26,6 +26,10 @@ properties:
- enum:
- sophgo,huashan-pi
- const: sophgo,cv1812h
+ - items:
+ - enum:
+ - sipeed,licheerv-nano
+ - const: sophgo,sg2002
- items:
- enum:
- milkv,pioneer
--
2.45.1
Add initial device tree for the SG2002 RISC-V SoC by SOPHGO.
Signed-off-by: Thomas Bonnefille <[email protected]>
---
arch/riscv/boot/dts/sophgo/sg2002.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
new file mode 100644
index 000000000000..b266357cb5c0
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <[email protected]>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+ compatible = "sophgo,sg2002";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&plic {
+ compatible = "sophgo,sg2002-plic", "thead,c900-plic";
+};
+
+&clint {
+ compatible = "sophgo,sg2002-clint", "thead,c900-clint";
+};
+
+&clk {
+ compatible = "sophgo,sg2000-clk";
+};
--
2.45.1
LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
SG2002 chip.
Add only support for UART.
Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
[1]
Signed-off-by: Thomas Bonnefille <[email protected]>
---
arch/riscv/boot/dts/sophgo/Makefile | 1 +
.../boot/dts/sophgo/sg2002-lichee-rv-nano.dts | 25 ++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 57ad82a61ea6..5759b21805dc 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
diff --git a/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
new file mode 100644
index 000000000000..aaad2733801b
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "sg2002.dtsi"
+
+/ {
+ model = "LicheeRV Nano";
+ compatible = "sipeed,licheerv-nano", "sophgo,sg2002";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.45.1
On Mon, May 27, 2024 at 12:28:18PM +0200, Thomas Bonnefille wrote:
> Add compatible string for SOPHGO SG2002 Core-Local Interrupt Controller.
>
> Signed-off-by: Thomas Bonnefille <[email protected]>
Acked-by: Conor Dooley <[email protected]>
On Mon, May 27, 2024 at 12:28:19PM +0200, Thomas Bonnefille wrote:
> Document the compatible strings for the Sipeed LicheeRV Nano board which
> uses the SOPHGO SG2002 SoC.
>
> Signed-off-by: Thomas Bonnefille <[email protected]>
Acked-by: Conor Dooley <[email protected]>
On Mon, May 27, 2024 at 12:28:21PM +0200, Thomas Bonnefille wrote:
> LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
> SG2002 chip.
>
> Add only support for UART.
>
> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
> [1]
Just format this as:
Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html [1]
On 5/27/24 12:28 PM, Thomas Bonnefille wrote:
> LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
> SG2002 chip.
>
> Add only support for UART.
>
> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
> [1]
>
> Signed-off-by: Thomas Bonnefille <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> .../boot/dts/sophgo/sg2002-lichee-rv-nano.dts | 25 ++++++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 57ad82a61ea6..5759b21805dc 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
>...
> +++ b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
I'm really sorry, it seems that I made a mistake here with git, the
device tree should not have an hyphen in its name, I'll send a new
version soon to correct this.
On Mon, May 27, 2024 at 12:28:21PM GMT, Thomas Bonnefille wrote:
> LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
> SG2002 chip.
>
> Add only support for UART.
>
Although this is OK, I think you can also add sdhci node, it is already
supported.
> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
> [1]
>
> Signed-off-by: Thomas Bonnefille <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> .../boot/dts/sophgo/sg2002-lichee-rv-nano.dts | 25 ++++++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 57ad82a61ea6..5759b21805dc 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
> new file mode 100644
> index 000000000000..aaad2733801b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2024 Thomas Bonnefille <[email protected]>
> + */
> +
> +/dts-v1/;
> +
> +#include "sg2002.dtsi"
> +
> +/ {
> + model = "LicheeRV Nano";
> + compatible = "sipeed,licheerv-nano", "sophgo,sg2002";
Use the right version, rv nano have several versions with different
peripherals. The compatible is good for the common file, but not the
specific board.
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
It is also better to add all already support nodes, such as gpio,
other uart port.
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
>
> --
> 2.45.1
>
On Mon, 27 May 2024 12:28:16 +0200, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
>
> Signed-off-by: Thomas Bonnefille <[email protected]>
> ---
> Thomas Bonnefille (5):
> dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
> dt-bindings: timer: Add SOPHGO SG2002 clint
> dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
> riscv: dts: sophgo: Add initial SG2002 SoC device tree
> riscv: dts: sophgo: Add LicheeRV Nano board device tree
>
> .../interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
> .../devicetree/bindings/riscv/sophgo.yaml | 4 +++
> .../devicetree/bindings/timer/sifive,clint.yaml | 1 +
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> .../boot/dts/sophgo/sg2002-lichee-rv-nano.dts | 25 ++++++++++++++++++
> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 30 ++++++++++++++++++++++
> 6 files changed, 62 insertions(+)
> ---
> base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
> change-id: 20240515-sg2002-93dce1d263be
>
> Best regards,
> --
> Thomas Bonnefille <[email protected]>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y sophgo/sg2002-lichee-rv-nano.dtb' for [email protected]:
arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dtb: oscillator: 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
Hi Thomas,
kernel test robot noticed the following build errors:
[auto build test ERROR on 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0]
url: https://github.com/intel-lab-lkp/linux/commits/Thomas-Bonnefille/dt-bindings-interrupt-controller-Add-SOPHGO-SG2002-plic/20240527-183235
base: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
patch link: https://lore.kernel.org/r/20240527-sg2002-v1-5-1b6cb38ce8f4%40bootlin.com
patch subject: [PATCH 5/5] riscv: dts: sophgo: Add LicheeRV Nano board device tree
config: riscv-allmodconfig (https://download.01.org/0day-ci/archive/20240529/[email protected]/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project bafda89a0944d947fc4b3b5663185e07a397ac30)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240529/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
>> make[6]: *** No rule to make target 'arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano.dtb', needed by 'arch/riscv/boot/dts/sophgo/'.
make[6]: Target 'arch/riscv/boot/dts/sophgo/' not remade because of errors.
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Thank you for your answer :)
On 5/28/24 12:25 AM, Inochi Amaoto wrote:
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>
> It is also better to add all already support nodes, such as gpio,
> other uart port.
I'm importing, cv18xx.dtsi through sg2002.dtsi, so GPIOs are already
configured and activated by default.
For the other peripherals, all of them are, with the default pinctrl,
set to function that haven't any driver yet (ADC, MIPI, PWM...).
Based on what I just said, I'm not sure to understand what you mean, can
you be more specific about the changes you want?
On Mon, Jun 10, 2024 at 09:30:55AM GMT, Thomas Bonnefille wrote:
> Thank you for your answer :)
>
> On 5/28/24 12:25 AM, Inochi Amaoto wrote:
>
> > > +
> > > + aliases {
> > > + serial0 = &uart0;
> > > + };
> > > +
> > > + chosen {
> > > + stdout-path = "serial0:115200n8";
> > > + };
> >
> > It is also better to add all already support nodes, such as gpio,
> > other uart port.
>
> I'm importing, cv18xx.dtsi through sg2002.dtsi, so GPIOs are already
> configured and activated by default.
> For the other peripherals, all of them are, with the default pinctrl, set to
> function that haven't any driver yet (ADC, MIPI, PWM...).
>
You forgot sdhci, which is already support the SD.
> Based on what I just said, I'm not sure to understand what you mean, can you
> be more specific about the changes you want?
I suggest adding aliases for all gpio and uart node. You can check
cv1800b-milkv-duo.dts as an example.