2020-03-09 11:56:12

by shiva.linuxworks

[permalink] [raw]
Subject: [PATCH v6 0/6] Add new series Micron SPI NAND devices

From: Shivamurthy Shastri <[email protected]>

This patchset is for the new series of Micron SPI NAND devices, and the
following links are their datasheets.

M78A:
[1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
[2] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf

M79A:
[3] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
[4] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf

M70A:
[5] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
[6] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
[7] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
[8] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf

Changes since v5:
-----------------

1. Rebased series to v5.6-rc1.

Changes since v4:
-----------------

1. Patch 2 is separated into two as per the comment by Boris.
2. Renamed MICRON_CFG_CONTI_READ into MICRON_CFG_CR.
3. Reworked die selection function as per the comment by Boris.

Changes since v3:
-----------------

1. Patch 3 and 4 reworked as follows
- Patch 3 introducing the Continuous read feature
- Patch 4 adding devices with the feature

Changes since v2:
-----------------

1. Patch commit messages have been modified.
2. Handled devices with Continuous Read feature with vendor specific flag.
3. Reworked die selection function as per the comment.

Changes since v1:
-----------------

1. The patch split into multiple patches.
2. Added comments for selecting the die.

Shivamurthy Shastri (6):
mtd: spinand: micron: Generalize the OOB layout structure and function
names
mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
mtd: spinand: micron: Add new Micron SPI NAND devices
mtd: spinand: micron: identify SPI NAND device with Continuous Read
mode
mtd: spinand: micron: Add M70A series Micron SPI NAND devices
mtd: spinand: micron: Add new Micron SPI NAND devices with multiple
dies

drivers/mtd/nand/spi/micron.c | 150 ++++++++++++++++++++++++++++++----
include/linux/mtd/spinand.h | 1 +
2 files changed, 137 insertions(+), 14 deletions(-)

--
2.17.1


2020-03-09 11:56:15

by shiva.linuxworks

[permalink] [raw]
Subject: [PATCH v6 2/6] mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD

From: Shivamurthy Shastri <[email protected]>

Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage
details as a comment.

Signed-off-by: Shivamurthy Shastri <[email protected]>
---
drivers/mtd/nand/spi/micron.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index c028d0d7e236..e4aeafc56f4e 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -91,6 +91,7 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand,
}

static const struct spinand_info micron_spinand_table[] = {
+ /* M79A 2Gb 3.3V */
SPINAND_INFO("MT29F2G01ABAGD", 0x24,
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(8, 512),
--
2.17.1

2020-03-09 11:56:19

by shiva.linuxworks

[permalink] [raw]
Subject: [PATCH v6 4/6] mtd: spinand: micron: identify SPI NAND device with Continuous Read mode

From: Shivamurthy Shastri <[email protected]>

Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.

Signed-off-by: Shivamurthy Shastri <[email protected]>
---
drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++
include/linux/mtd/spinand.h | 1 +
2 files changed, 17 insertions(+)

diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 5fd1f921ef12..ff0a3c01441d 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -18,6 +18,8 @@
#define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
#define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)

+#define MICRON_CFG_CR BIT(0)
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -153,8 +155,22 @@ static int micron_spinand_detect(struct spinand_device *spinand)
return 1;
}

+static int micron_spinand_init(struct spinand_device *spinand)
+{
+ /*
+ * M70A device series enable Continuous Read feature at Power-up,
+ * which is not supported. Disable this bit to avoid any possible
+ * failure.
+ */
+ if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
+ return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
+
+ return 0;
+}
+
static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
.detect = micron_spinand_detect,
+ .init = micron_spinand_init,
};

const struct spinand_manufacturer micron_spinand_manufacturer = {
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 4ea558bd3c46..333149b2855f 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -270,6 +270,7 @@ struct spinand_ecc_info {
};

#define SPINAND_HAS_QE_BIT BIT(0)
+#define SPINAND_HAS_CR_FEAT_BIT BIT(1)

/**
* struct spinand_info - Structure used to describe SPI NAND chips
--
2.17.1

2020-03-09 11:56:22

by shiva.linuxworks

[permalink] [raw]
Subject: [PATCH v6 5/6] mtd: spinand: micron: Add M70A series Micron SPI NAND devices

From: Shivamurthy Shastri <[email protected]>

Add device table for M70A series Micron SPI NAND devices.

Signed-off-by: Shivamurthy Shastri <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
---
drivers/mtd/nand/spi/micron.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index ff0a3c01441d..9db1ab71fcae 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -133,6 +133,26 @@ static const struct spinand_info micron_spinand_table[] = {
0,
SPINAND_ECCINFO(&micron_8_ooblayout,
micron_8_ecc_get_status)),
+ /* M70A 4Gb 3.3V */
+ SPINAND_INFO("MT29F4G01ABAFD", 0x34,
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_CR_FEAT_BIT,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status)),
+ /* M70A 4Gb 1.8V */
+ SPINAND_INFO("MT29F4G01ABBFD", 0x35,
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_CR_FEAT_BIT,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status)),
};

static int micron_spinand_detect(struct spinand_device *spinand)
--
2.17.1

2020-03-09 11:56:29

by shiva.linuxworks

[permalink] [raw]
Subject: [PATCH v6 6/6] mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies

From: Shivamurthy Shastri <[email protected]>

Add device table for new Micron SPI NAND devices, which have multiple
dies.

Also, enable support to select the dies.

Signed-off-by: Shivamurthy Shastri <[email protected]>
---
drivers/mtd/nand/spi/micron.c | 55 +++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)

diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 9db1ab71fcae..f7d148aaa476 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -20,6 +20,14 @@

#define MICRON_CFG_CR BIT(0)

+/*
+ * As per datasheet, die selection is done by the 6th bit of Die
+ * Select Register (Address 0xD0).
+ */
+#define MICRON_DIE_SELECT_REG 0xD0
+
+#define MICRON_SELECT_DIE(x) ((x) << 6)
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = {
.free = micron_8_ooblayout_free,
};

+static int micron_select_target(struct spinand_device *spinand,
+ unsigned int target)
+{
+ struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
+ spinand->scratchbuf);
+
+ if (target > 1)
+ return -EINVAL;
+
+ *spinand->scratchbuf = MICRON_SELECT_DIE(target);
+
+ return spi_mem_exec_op(spinand->spimem, &op);
+}
+
static int micron_8_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
@@ -133,6 +155,17 @@ static const struct spinand_info micron_spinand_table[] = {
0,
SPINAND_ECCINFO(&micron_8_ooblayout,
micron_8_ecc_get_status)),
+ /* M79A 4Gb 3.3V */
+ SPINAND_INFO("MT29F4G01ADAGD", 0x36,
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status),
+ SPINAND_SELECT_TARGET(micron_select_target)),
/* M70A 4Gb 3.3V */
SPINAND_INFO("MT29F4G01ABAFD", 0x34,
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
@@ -153,6 +186,28 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(&micron_8_ooblayout,
micron_8_ecc_get_status)),
+ /* M70A 8Gb 3.3V */
+ SPINAND_INFO("MT29F8G01ADAFD", 0x46,
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_CR_FEAT_BIT,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status),
+ SPINAND_SELECT_TARGET(micron_select_target)),
+ /* M70A 8Gb 1.8V */
+ SPINAND_INFO("MT29F8G01ADBFD", 0x47,
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_CR_FEAT_BIT,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status),
+ SPINAND_SELECT_TARGET(micron_select_target)),
};

static int micron_spinand_detect(struct spinand_device *spinand)
--
2.17.1

2020-03-09 11:57:02

by shiva.linuxworks

[permalink] [raw]
Subject: [PATCH v6 3/6] mtd: spinand: micron: Add new Micron SPI NAND devices

From: Shivamurthy Shastri <[email protected]>

Add device table for M79A and M78A series Micron SPI NAND devices.

Signed-off-by: Shivamurthy Shastri <[email protected]>
---
drivers/mtd/nand/spi/micron.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)

diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index e4aeafc56f4e..5fd1f921ef12 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -101,6 +101,36 @@ static const struct spinand_info micron_spinand_table[] = {
0,
SPINAND_ECCINFO(&micron_8_ooblayout,
micron_8_ecc_get_status)),
+ /* M79A 2Gb 1.8V */
+ SPINAND_INFO("MT29F2G01ABBGD", 0x25,
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status)),
+ /* M78A 1Gb 3.3V */
+ SPINAND_INFO("MT29F1G01ABAFD", 0x14,
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status)),
+ /* M78A 1Gb 1.8V */
+ SPINAND_INFO("MT29F1G01ABAFD", 0x15,
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&micron_8_ooblayout,
+ micron_8_ecc_get_status)),
};

static int micron_spinand_detect(struct spinand_device *spinand)
--
2.17.1

Subject: RE: [EXT] [PATCH v6 0/6] Add new series Micron SPI NAND devices

Hi Miquel,

I have rebased these patches to v5.6-rc1 as you suggested.
Please let me know, if there is still a problem.

Thanks,
Shiva

>
> From: Shivamurthy Shastri <[email protected]>
>
> This patchset is for the new series of Micron SPI NAND devices, and the
> following links are their datasheets.
>
> M78A:
> [1] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
> [2] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
>
> M79A:
> [3] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
> [4] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
>
> M70A:
> [5] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
> [6] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
> [7] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
> [8] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
>
> Changes since v5:
> -----------------
>
> 1. Rebased series to v5.6-rc1.
>
> Changes since v4:
> -----------------
>
> 1. Patch 2 is separated into two as per the comment by Boris.
> 2. Renamed MICRON_CFG_CONTI_READ into MICRON_CFG_CR.
> 3. Reworked die selection function as per the comment by Boris.
>
> Changes since v3:
> -----------------
>
> 1. Patch 3 and 4 reworked as follows
> - Patch 3 introducing the Continuous read feature
> - Patch 4 adding devices with the feature
>
> Changes since v2:
> -----------------
>
> 1. Patch commit messages have been modified.
> 2. Handled devices with Continuous Read feature with vendor specific flag.
> 3. Reworked die selection function as per the comment.
>
> Changes since v1:
> -----------------
>
> 1. The patch split into multiple patches.
> 2. Added comments for selecting the die.
>
> Shivamurthy Shastri (6):
> mtd: spinand: micron: Generalize the OOB layout structure and function
> names
> mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
> mtd: spinand: micron: Add new Micron SPI NAND devices
> mtd: spinand: micron: identify SPI NAND device with Continuous Read
> mode
> mtd: spinand: micron: Add M70A series Micron SPI NAND devices
> mtd: spinand: micron: Add new Micron SPI NAND devices with multiple
> dies
>
> drivers/mtd/nand/spi/micron.c | 150
> ++++++++++++++++++++++++++++++----
> include/linux/mtd/spinand.h | 1 +
> 2 files changed, 137 insertions(+), 14 deletions(-)
>
> --
> 2.17.1

2020-03-11 10:52:51

by Boris Brezillon

[permalink] [raw]
Subject: Re: [PATCH v6 2/6] mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD

On Mon, 9 Mar 2020 12:52:26 +0100
[email protected] wrote:

> From: Shivamurthy Shastri <[email protected]>
>
> Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage
> details as a comment.
>
> Signed-off-by: Shivamurthy Shastri <[email protected]>

Reviewed-by: Boris Brezillon <[email protected]>

> ---
> drivers/mtd/nand/spi/micron.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index c028d0d7e236..e4aeafc56f4e 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -91,6 +91,7 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand,
> }
>
> static const struct spinand_info micron_spinand_table[] = {
> + /* M79A 2Gb 3.3V */
> SPINAND_INFO("MT29F2G01ABAGD", 0x24,
> NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> NAND_ECCREQ(8, 512),

2020-03-11 10:53:44

by Boris Brezillon

[permalink] [raw]
Subject: Re: [PATCH v6 4/6] mtd: spinand: micron: identify SPI NAND device with Continuous Read mode

On Mon, 9 Mar 2020 12:52:28 +0100
[email protected] wrote:

> From: Shivamurthy Shastri <[email protected]>
>
> Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
> the Continuous Read mode.
>
> Some of the Micron SPI NAND devices have the "Continuous Read" feature
> enabled by default, which does not fit the subsystem needs.
>
> In this mode, the READ CACHE command doesn't require the starting column
> address. The device always output the data starting from the first
> column of the cache register, and once the end of the cache register
> reached, the data output continues through the next page. With the
> continuous read mode, it is possible to read out the entire block using
> a single READ command, and once the end of the block reached, the output
> pins become High-Z state. However, during this mode the read command
> doesn't output the OOB area.
>
> Hence, we disable the feature at probe time.
>
> Signed-off-by: Shivamurthy Shastri <[email protected]>

Reviewed-by: Boris Brezillon <[email protected]>

> ---
> drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++
> include/linux/mtd/spinand.h | 1 +
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index 5fd1f921ef12..ff0a3c01441d 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -18,6 +18,8 @@
> #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
> #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
>
> +#define MICRON_CFG_CR BIT(0)
> +
> static SPINAND_OP_VARIANTS(read_cache_variants,
> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
> SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> @@ -153,8 +155,22 @@ static int micron_spinand_detect(struct spinand_device *spinand)
> return 1;
> }
>
> +static int micron_spinand_init(struct spinand_device *spinand)
> +{
> + /*
> + * M70A device series enable Continuous Read feature at Power-up,
> + * which is not supported. Disable this bit to avoid any possible
> + * failure.
> + */
> + if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
> + return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
> +
> + return 0;
> +}
> +
> static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
> .detect = micron_spinand_detect,
> + .init = micron_spinand_init,
> };
>
> const struct spinand_manufacturer micron_spinand_manufacturer = {
> diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
> index 4ea558bd3c46..333149b2855f 100644
> --- a/include/linux/mtd/spinand.h
> +++ b/include/linux/mtd/spinand.h
> @@ -270,6 +270,7 @@ struct spinand_ecc_info {
> };
>
> #define SPINAND_HAS_QE_BIT BIT(0)
> +#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
>
> /**
> * struct spinand_info - Structure used to describe SPI NAND chips

2020-03-11 10:55:15

by Boris Brezillon

[permalink] [raw]
Subject: Re: [PATCH v6 3/6] mtd: spinand: micron: Add new Micron SPI NAND devices

On Mon, 9 Mar 2020 12:52:27 +0100
[email protected] wrote:

> From: Shivamurthy Shastri <[email protected]>
>
> Add device table for M79A and M78A series Micron SPI NAND devices.
>
> Signed-off-by: Shivamurthy Shastri <[email protected]>

Reviewed-by: Boris Brezillon <[email protected]>

> ---
> drivers/mtd/nand/spi/micron.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index e4aeafc56f4e..5fd1f921ef12 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -101,6 +101,36 @@ static const struct spinand_info micron_spinand_table[] = {
> 0,
> SPINAND_ECCINFO(&micron_8_ooblayout,
> micron_8_ecc_get_status)),
> + /* M79A 2Gb 1.8V */
> + SPINAND_INFO("MT29F2G01ABBGD", 0x25,
> + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + 0,
> + SPINAND_ECCINFO(&micron_8_ooblayout,
> + micron_8_ecc_get_status)),
> + /* M78A 1Gb 3.3V */
> + SPINAND_INFO("MT29F1G01ABAFD", 0x14,
> + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + 0,
> + SPINAND_ECCINFO(&micron_8_ooblayout,
> + micron_8_ecc_get_status)),
> + /* M78A 1Gb 1.8V */
> + SPINAND_INFO("MT29F1G01ABAFD", 0x15,
> + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + 0,
> + SPINAND_ECCINFO(&micron_8_ooblayout,
> + micron_8_ecc_get_status)),
> };
>
> static int micron_spinand_detect(struct spinand_device *spinand)

2020-03-11 10:55:32

by Boris Brezillon

[permalink] [raw]
Subject: Re: [PATCH v6 6/6] mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies

On Mon, 9 Mar 2020 12:52:30 +0100
[email protected] wrote:

> From: Shivamurthy Shastri <[email protected]>
>
> Add device table for new Micron SPI NAND devices, which have multiple
> dies.
>
> Also, enable support to select the dies.
>
> Signed-off-by: Shivamurthy Shastri <[email protected]>

Reviewed-by: Boris Brezillon <[email protected]>

> ---
> drivers/mtd/nand/spi/micron.c | 55 +++++++++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index 9db1ab71fcae..f7d148aaa476 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -20,6 +20,14 @@
>
> #define MICRON_CFG_CR BIT(0)
>
> +/*
> + * As per datasheet, die selection is done by the 6th bit of Die
> + * Select Register (Address 0xD0).
> + */
> +#define MICRON_DIE_SELECT_REG 0xD0
> +
> +#define MICRON_SELECT_DIE(x) ((x) << 6)
> +
> static SPINAND_OP_VARIANTS(read_cache_variants,
> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
> SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> @@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = {
> .free = micron_8_ooblayout_free,
> };
>
> +static int micron_select_target(struct spinand_device *spinand,
> + unsigned int target)
> +{
> + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
> + spinand->scratchbuf);
> +
> + if (target > 1)
> + return -EINVAL;
> +
> + *spinand->scratchbuf = MICRON_SELECT_DIE(target);
> +
> + return spi_mem_exec_op(spinand->spimem, &op);
> +}
> +
> static int micron_8_ecc_get_status(struct spinand_device *spinand,
> u8 status)
> {
> @@ -133,6 +155,17 @@ static const struct spinand_info micron_spinand_table[] = {
> 0,
> SPINAND_ECCINFO(&micron_8_ooblayout,
> micron_8_ecc_get_status)),
> + /* M79A 4Gb 3.3V */
> + SPINAND_INFO("MT29F4G01ADAGD", 0x36,
> + NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + 0,
> + SPINAND_ECCINFO(&micron_8_ooblayout,
> + micron_8_ecc_get_status),
> + SPINAND_SELECT_TARGET(micron_select_target)),
> /* M70A 4Gb 3.3V */
> SPINAND_INFO("MT29F4G01ABAFD", 0x34,
> NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> @@ -153,6 +186,28 @@ static const struct spinand_info micron_spinand_table[] = {
> SPINAND_HAS_CR_FEAT_BIT,
> SPINAND_ECCINFO(&micron_8_ooblayout,
> micron_8_ecc_get_status)),
> + /* M70A 8Gb 3.3V */
> + SPINAND_INFO("MT29F8G01ADAFD", 0x46,
> + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + SPINAND_HAS_CR_FEAT_BIT,
> + SPINAND_ECCINFO(&micron_8_ooblayout,
> + micron_8_ecc_get_status),
> + SPINAND_SELECT_TARGET(micron_select_target)),
> + /* M70A 8Gb 1.8V */
> + SPINAND_INFO("MT29F8G01ADBFD", 0x47,
> + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
> + NAND_ECCREQ(8, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + SPINAND_HAS_CR_FEAT_BIT,
> + SPINAND_ECCINFO(&micron_8_ooblayout,
> + micron_8_ecc_get_status),
> + SPINAND_SELECT_TARGET(micron_select_target)),
> };
>
> static int micron_spinand_detect(struct spinand_device *spinand)

2020-03-11 15:51:43

by Miquel Raynal

[permalink] [raw]
Subject: Re: [PATCH v6 0/6] Add new series Micron SPI NAND devices

Hi Shiva,

[email protected] wrote on Mon, 9 Mar 2020 12:52:24 +0100:

> From: Shivamurthy Shastri <[email protected]>
>
> This patchset is for the new series of Micron SPI NAND devices, and the
> following links are their datasheets.
>
> M78A:
> [1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
> [2] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
>
> M79A:
> [3] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
> [4] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
>
> M70A:
> [5] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
> [6] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
> [7] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
> [8] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
>
> Changes since v5:
> -----------------
>
> 1. Rebased series to v5.6-rc1.

I am very sorry but actually I had issues applying all your patches not
because they were not based on v5.6-rc1, but because since then I
applied a patch changing the detection that changed the content of a
lot of structures (including in Micron's patches).

Can you please rebase again on top of the current nand/next? I am very
sorry for this extra work, this is my mistake.

Head should be:

a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers")

And the culprit commit is:

f1541773af49 ("mtd: spinand: rework detect procedure for different READ_ID operation")

Thanks,
Miquèl

Subject: RE: [EXT] Re: [PATCH v6 0/6] Add new series Micron SPI NAND devices

Hi Miquel,

>
> Hi Shiva,
>
> [email protected] wrote on Mon, 9 Mar 2020 12:52:24 +0100:
>
> > From: Shivamurthy Shastri <[email protected]>
> >
> > This patchset is for the new series of Micron SPI NAND devices, and the
> > following links are their datasheets.
> >
> > M78A:
> > [1] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
> > [2] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
> >
> > M79A:
> > [3] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
> > [4] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
> >
> > M70A:
> > [5] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
> > [6] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
> > [7] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
> > [8] https://www.micron.com/~/media/documents/products/data-
> sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
> >
> > Changes since v5:
> > -----------------
> >
> > 1. Rebased series to v5.6-rc1.
>
> I am very sorry but actually I had issues applying all your patches not
> because they were not based on v5.6-rc1, but because since then I
> applied a patch changing the detection that changed the content of a
> lot of structures (including in Micron's patches).
>
> Can you please rebase again on top of the current nand/next? I am very
> sorry for this extra work, this is my mistake.
>
> Head should be:
>
> a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu
> for dma transfers")
>
> And the culprit commit is:
>
> f1541773af49 ("mtd: spinand: rework detect procedure for different
> READ_ID operation")


I will rebase and send the patches.
Meanwhile, there will be small code change because of the READ_ID patch.

Do I need to drop Reviewed-by from Boris?

Thanks,
Shiva

2020-03-11 17:37:21

by Boris Brezillon

[permalink] [raw]
Subject: Re: [EXT] Re: [PATCH v6 0/6] Add new series Micron SPI NAND devices

On Wed, 11 Mar 2020 17:33:41 +0000
"Shivamurthy Shastri (sshivamurthy)" <[email protected]> wrote:

> Hi Miquel,
>
> >
> > Hi Shiva,
> >
> > [email protected] wrote on Mon, 9 Mar 2020 12:52:24 +0100:
> >
> > > From: Shivamurthy Shastri <[email protected]>
> > >
> > > This patchset is for the new series of Micron SPI NAND devices, and the
> > > following links are their datasheets.
> > >
> > > M78A:
> > > [1] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
> > > [2] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
> > >
> > > M79A:
> > > [3] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
> > > [4] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
> > >
> > > M70A:
> > > [5] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
> > > [6] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
> > > [7] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
> > > [8] https://www.micron.com/~/media/documents/products/data-
> > sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
> > >
> > > Changes since v5:
> > > -----------------
> > >
> > > 1. Rebased series to v5.6-rc1.
> >
> > I am very sorry but actually I had issues applying all your patches not
> > because they were not based on v5.6-rc1, but because since then I
> > applied a patch changing the detection that changed the content of a
> > lot of structures (including in Micron's patches).
> >
> > Can you please rebase again on top of the current nand/next? I am very
> > sorry for this extra work, this is my mistake.
> >
> > Head should be:
> >
> > a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu
> > for dma transfers")
> >
> > And the culprit commit is:
> >
> > f1541773af49 ("mtd: spinand: rework detect procedure for different
> > READ_ID operation")
>
>
> I will rebase and send the patches.
> Meanwhile, there will be small code change because of the READ_ID patch.
>
> Do I need to drop Reviewed-by from Boris?

Nope, you can keep it.