This patchset fixes 64-bit simple CDMA transfer.
It also does some trivial code refactoring.
Changes for v2:
- Introduce helper macro for creating dma_addr_t from hardware buffer
descriptor LSB and MSB fields. Use it to fix 64-bit simple CDMA transfer.
- Modified commit description in 2/4 patch.
Radhey Shyam Pandey (4):
dmaengine: xilinx_dma: Refactor axidma channel allocation
dmaengine: xilinx_dma: Refactor axidma channel validation
dmaengine: xilinx_dma: Introduce helper macro for preparing dma
address
dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer
drivers/dma/xilinx/xilinx_dma.c | 48 +++++++++++++++++++++-----------------
1 files changed, 26 insertions(+), 22 deletions(-)
This patch introduces the xilinx_prep_dma_addr_t macro which prepares
dma_addr_t from hardware buffer descriptor LSB and MSB fields. It will
be used in simple dma 64-bit programming sequence.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
---
Changes for v2:
New patch- Preparatory change for 4/4 fix.
---
drivers/dma/xilinx/xilinx_dma.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index a37871e..c27ab64 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -190,6 +190,8 @@
/* AXI CDMA Specific Masks */
#define XILINX_CDMA_CR_SGMODE BIT(3)
+#define xilinx_prep_dma_addr_t(addr) \
+ ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
/**
* struct xilinx_vdma_desc_hw - Hardware Descriptor
* @next_desc: Next Descriptor Pointer @0x00
--
1.7.1
In axidma start_transfer, prefer checking channel states before
other params i.e pending_list. No functional change.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
---
Changes for v2:
Modified the commit message to mark it as non-functional change.
---
drivers/dma/xilinx/xilinx_dma.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 06d1632..a37871e 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1271,10 +1271,10 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
if (chan->err)
return;
- if (list_empty(&chan->pending_list))
+ if (!chan->idle)
return;
- if (!chan->idle)
+ if (list_empty(&chan->pending_list))
return;
head_desc = list_first_entry(&chan->pending_list,
--
1.7.1
In axidma alloc_chan_resources merge BD and cyclic BD allocation.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
---
Changes for v2:
None
---
drivers/dma/xilinx/xilinx_dma.c | 36 ++++++++++++++++++------------------
1 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index c124423..06d1632 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -887,6 +887,24 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
chan->id);
return -ENOMEM;
}
+ /*
+ * For cyclic DMA mode we need to program the tail Descriptor
+ * register with a value which is not a part of the BD chain
+ * so allocating a desc segment during channel allocation for
+ * programming tail descriptor.
+ */
+ chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
+ sizeof(*chan->cyclic_seg_v),
+ &chan->cyclic_seg_p, GFP_KERNEL);
+ if (!chan->cyclic_seg_v) {
+ dev_err(chan->dev,
+ "unable to allocate desc segment for cyclic DMA\n");
+ dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
+ XILINX_DMA_NUM_DESCS, chan->seg_v,
+ chan->seg_p);
+ return -ENOMEM;
+ }
+ chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
chan->seg_v[i].hw.next_desc =
@@ -922,24 +940,6 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
return -ENOMEM;
}
- if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
- /*
- * For cyclic DMA mode we need to program the tail Descriptor
- * register with a value which is not a part of the BD chain
- * so allocating a desc segment during channel allocation for
- * programming tail descriptor.
- */
- chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
- sizeof(*chan->cyclic_seg_v),
- &chan->cyclic_seg_p, GFP_KERNEL);
- if (!chan->cyclic_seg_v) {
- dev_err(chan->dev,
- "unable to allocate desc segment for cyclic DMA\n");
- return -ENOMEM;
- }
- chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
- }
-
dma_cookie_init(dchan);
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
--
1.7.1
In AXI CDMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. This fixes simple CDMA operation
mode using 64-bit addressing.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
---
Changes for v2:
Use helper macro for preparing dma_addr_t.
---
drivers/dma/xilinx/xilinx_dma.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index c27ab64..d04ef85 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1247,8 +1247,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
hw = &segment->hw;
- xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
- xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
+ xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
+ xilinx_prep_dma_addr_t(hw->src_addr));
+ xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
+ xilinx_prep_dma_addr_t(hw->dest_addr));
/* Start the transfer */
dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
--
1.7.1
Hi,
Thanks for the patch...
>
> This patch introduces the xilinx_prep_dma_addr_t macro which prepares
> dma_addr_t from hardware buffer descriptor LSB and MSB fields. It will be
> used in simple dma 64-bit programming sequence.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
Reviewed-by: Appana Durga Kedareswara Rao <[email protected]>
Regards,
Kedar.
> ---
> Changes for v2:
> New patch- Preparatory change for 4/4 fix.
> ---
> drivers/dma/xilinx/xilinx_dma.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index a37871e..c27ab64 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -190,6 +190,8 @@
> /* AXI CDMA Specific Masks */
> #define XILINX_CDMA_CR_SGMODE BIT(3)
>
> +#define xilinx_prep_dma_addr_t(addr) \
> + ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
> /**
> * struct xilinx_vdma_desc_hw - Hardware Descriptor
> * @next_desc: Next Descriptor Pointer @0x00
> --
> 1.7.1
> -----Original Message-----
> From: Radhey Shyam Pandey <[email protected]>
> Sent: Saturday, September 29, 2018 10:48 PM
> To: [email protected]; [email protected]; Michal Simek
> <[email protected]>; Appana Durga Kedareswara Rao
> <[email protected]>; Radhey Shyam Pandey <[email protected]>
> Cc: [email protected]; [email protected]; linux-
> [email protected]
> Subject: [PATCH v2 4/4] dmaengine: xilinx_dma: Fix 64-bit simple CDMA
> transfer
>
> In AXI CDMA simple mode also pass MSB bits of source and destination
> address to xilinx_write function. This fixes simple CDMA operation mode using
> 64-bit addressing.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Appana Durga Kedareswara Rao <[email protected]>
Regards,
Kedar.
> ---
> Changes for v2:
> Use helper macro for preparing dma_addr_t.
> ---
> drivers/dma/xilinx/xilinx_dma.c | 6 ++++--
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index c27ab64..d04ef85 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1247,8 +1247,10 @@ static void xilinx_cdma_start_transfer(struct
> xilinx_dma_chan *chan)
>
> hw = &segment->hw;
>
> - xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw-
> >src_addr);
> - xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw-
> >dest_addr);
> + xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
> + xilinx_prep_dma_addr_t(hw->src_addr));
> + xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
> + xilinx_prep_dma_addr_t(hw->dest_addr));
>
> /* Start the transfer */
> dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
> --
> 1.7.1
On 29-09-18, 11:17, Radhey Shyam Pandey wrote:
> In axidma start_transfer, prefer checking channel states before
> other params i.e pending_list. No functional change.
There needs to be proper reason rather than a preference, can you
explain why
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
> Changes for v2:
> Modified the commit message to mark it as non-functional change.
> ---
> drivers/dma/xilinx/xilinx_dma.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 06d1632..a37871e 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1271,10 +1271,10 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
> if (chan->err)
> return;
>
> - if (list_empty(&chan->pending_list))
> + if (!chan->idle)
> return;
>
> - if (!chan->idle)
> + if (list_empty(&chan->pending_list))
> return;
>
> head_desc = list_first_entry(&chan->pending_list,
> --
> 1.7.1
--
~Vinod
On 29-09-18, 11:17, Radhey Shyam Pandey wrote:
> This patchset fixes 64-bit simple CDMA transfer.
> It also does some trivial code refactoring.
Applied except 2nd patch, thanks
--
~Vinod
> -----Original Message-----
> From: Vinod Koul <[email protected]>
> Sent: Sunday, November 11, 2018 2:30 AM
> To: Radhey Shyam Pandey <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Appana
> Durga Kedareswara Rao <[email protected]>; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH v2 2/4] dmaengine: xilinx_dma: Refactor axidma channel
> validation
>
> On 29-09-18, 11:17, Radhey Shyam Pandey wrote:
> > In axidma start_transfer, prefer checking channel states before
> > other params i.e pending_list. No functional change.
>
> There needs to be proper reason rather than a preference, can you
> explain why
Initially, I thought to group channel states check before checking
pending_list. It came up in doing diff with xilinx tree and mainline
tree. But agree it's not of significant importance and can be dropped.
>
> >
> > Signed-off-by: Radhey Shyam Pandey <[email protected]>
> > ---
> > Changes for v2:
> > Modified the commit message to mark it as non-functional change.
> > ---
> > drivers/dma/xilinx/xilinx_dma.c | 4 ++--
> > 1 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> > index 06d1632..a37871e 100644
> > --- a/drivers/dma/xilinx/xilinx_dma.c
> > +++ b/drivers/dma/xilinx/xilinx_dma.c
> > @@ -1271,10 +1271,10 @@ static void xilinx_dma_start_transfer(struct
> xilinx_dma_chan *chan)
> > if (chan->err)
> > return;
> >
> > - if (list_empty(&chan->pending_list))
> > + if (!chan->idle)
> > return;
> >
> > - if (!chan->idle)
> > + if (list_empty(&chan->pending_list))
> > return;
> >
> > head_desc = list_first_entry(&chan->pending_list,
> > --
> > 1.7.1
>
> --
> ~Vinod