From: Nick Hawkins <[email protected]>
Creating binding for gxp timer in device tree hpe,gxp-timer
Although there are multiple times on the SoC we are only
enabling one at this time.
Signed-off-by: Nick Hawkins <[email protected]>
----
v2:
*Removed maintainer change from patch
*Verified there was no compilation errors
*Added reference code in separate patch of patchset
---
.../bindings/timer/hpe,gxp-timer.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
new file mode 100644
index 000000000000..1f4e345c5fb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/hpe,gxp-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HPE GXP TIMER
+
+maintainers:
+ - Nick Hawkins <[email protected]>
+ - Jean-Marie Verdun <[email protected]>
+
+properties:
+ compatible:
+ const: hpe,gxp-timer
+
+ reg:
+ items:
+ - description: T0CNT register
+ - description: T0CS register
+ - description: TIMELO register
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency:
+ description: The frequency of the clock that drives the counter, in Hz.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-frequency
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@10003000 {
+ compatible = "hpe,gxp-timer";
+ reg = <0xc0000080 0x1>, <0xc0000094 0x01>, <0xc0000088 0x08>;
+ interrupts = <0>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <400000000>;
+ };
--
2.17.1
On Thu, Mar 10, 2022 at 01:52:24PM -0600, [email protected] wrote:
>> From: Nick Hawkins <[email protected]>>
>>
>> Creating binding for gxp timer in device tree hpe,gxp-timer Although
>> there are multiple times on the SoC we are only enabling one at this
>> time.
>>
>> Signed-off-by: Nick Hawkins <[email protected]>>
>>
>> ----
>>
>> v2:
>> *Removed maintainer change from patch *Verified there was no
>> compilation errors *Added reference code in separate patch of
>> patchset
>> ---
>> .../bindings/timer/hpe,gxp-timer.yaml | 45 +++++++++++++++++++
>> 1 file changed, 45 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>> b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>> new file mode 100644
>> index 000000000000..1f4e345c5fb8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id:
>> +INVALID URI REMOVED
>> +xp-timer.yaml*__;Iw!!NpxR!yaItMPvjqEf3fKyp1xDQAzawRQDd8uDGTNKMlVPpn5Y
>> +56IUABMYbali7jonBl20K$
>> +$schema:
>> +INVALID URI REMOVED
>> +aml*__;Iw!!NpxR!yaItMPvjqEf3fKyp1xDQAzawRQDd8uDGTNKMlVPpn5Y56IUABMYba
>> +li7jmX565-G$
>> +
>> +title: HPE GXP TIMER
>> +
>> +maintainers:
>> + - Nick Hawkins <[email protected]>>
>> + - Jean-Marie Verdun <[email protected]>>
>> +
>> +properties:
>> + compatible:
>> + const: hpe,gxp-timer
>> +
>> + reg:
>> + items:
>> + - description: T0CNT register
>> + - description: T0CS register
>> + - description: TIMELO register
> Is the spec public to know what T0CNT, T0CS, and TIMELO are?
No it is not, should I not mention the register descriptions at all?
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + clock-frequency:
>> + description: The frequency of the clock that drives the counter, in Hz.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interrupts
>> + - clock-frequency
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + timer@10003000 {
>> + compatible = "hpe,gxp-timer";
>> + reg = <0xc0000080 0x1>>, <0xc0000094 0x01>>, <0xc0000088 0x08>>;
> Based on the driver these are 4 bytes, 1 byte, 4 bytes in size.
> Are there other registers in 0x80-0x95 range or do these offsets change in other chips? If not, just 1 entry covering the whole thing would be better.
There are other registers in this range that cover different timers/clocks, for the most part between chip generations the offsets remain the same unless there is an architectural issue.
Can you provide a quick example of what one entry would be?
>> + interrupts = <0>>;
>> + interrupt-parent = <&vic0>>;
>> + clock-frequency = <400000000>>;
>> + };
>> --
>> 2.17.1
>>
>>
Regards,
Nick Hawkins
On 10/03/2022 20:52, [email protected] wrote:
> From: Nick Hawkins <[email protected]>
>
> Creating binding for gxp timer in device tree hpe,gxp-timer
> Although there are multiple times on the SoC we are only
> enabling one at this time.
>
> Signed-off-by: Nick Hawkins <[email protected]>
>
> ----
>
> v2:
> *Removed maintainer change from patch
> *Verified there was no compilation errors
> *Added reference code in separate patch of patchset
> ---
> .../bindings/timer/hpe,gxp-timer.yaml | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
> new file mode 100644
> index 000000000000..1f4e345c5fb8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/hpe,gxp-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HPE GXP TIMER
> +
> +maintainers:
> + - Nick Hawkins <[email protected]>
> + - Jean-Marie Verdun <[email protected]>
> +
> +properties:
> + compatible:
> + const: hpe,gxp-timer
> +
> + reg:
> + items:
> + - description: T0CNT register
> + - description: T0CS register
> + - description: TIMELO register
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-frequency:
> + description: The frequency of the clock that drives the counter, in Hz.
Which clock is it? Generated inside the timer? If outside, why driver
does not take the reference to it and uses clk_get_rate()?
Best regards,
Krzysztof
On 11/03/2022 17:22, Hawkins, Nick wrote:
> On Thu, Mar 10, 2022 at 01:52:24PM -0600, [email protected] wrote:
>>> From: Nick Hawkins <[email protected]>>
>>>
>>> Creating binding for gxp timer in device tree hpe,gxp-timer Although
>>> there are multiple times on the SoC we are only enabling one at this
>>> time.
>>>
>>> Signed-off-by: Nick Hawkins <[email protected]>>
>>>
>>> ----
>>>
>>> v2:
>>> *Removed maintainer change from patch *Verified there was no
>>> compilation errors *Added reference code in separate patch of
>>> patchset
>>> ---
>>> .../bindings/timer/hpe,gxp-timer.yaml | 45 +++++++++++++++++++
>>> 1 file changed, 45 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>>> b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>>> new file mode 100644
>>> index 000000000000..1f4e345c5fb8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>>> @@ -0,0 +1,45 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>>> +---
>>> +$id:
>>> +INVALID URI REMOVED
>>> +xp-timer.yaml*__;Iw!!NpxR!yaItMPvjqEf3fKyp1xDQAzawRQDd8uDGTNKMlVPpn5Y
>>> +56IUABMYbali7jonBl20K$
>>> +$schema:
>>> +INVALID URI REMOVED
>>> +aml*__;Iw!!NpxR!yaItMPvjqEf3fKyp1xDQAzawRQDd8uDGTNKMlVPpn5Y56IUABMYba
>>> +li7jmX565-G$
>>> +
>>> +title: HPE GXP TIMER
>>> +
>>> +maintainers:
>>> + - Nick Hawkins <[email protected]>>
>>> + - Jean-Marie Verdun <[email protected]>>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: hpe,gxp-timer
>>> +
>>> + reg:
>>> + items:
>>> + - description: T0CNT register
>>> + - description: T0CS register
>>> + - description: TIMELO register
>
>> Is the spec public to know what T0CNT, T0CS, and TIMELO are?
> No it is not, should I not mention the register descriptions at all?
>
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> +
>>> + clock-frequency:
>>> + description: The frequency of the clock that drives the counter, in Hz.
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - interrupts
>>> + - clock-frequency
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + timer@10003000 {
>>> + compatible = "hpe,gxp-timer";
>>> + reg = <0xc0000080 0x1>>, <0xc0000094 0x01>>, <0xc0000088 0x08>>;
>
>> Based on the driver these are 4 bytes, 1 byte, 4 bytes in size.
>
>> Are there other registers in 0x80-0x95 range or do these offsets change in other chips? If not, just 1 entry covering the whole thing would be better.
> There are other registers in this range that cover different timers/clocks, for the most part between chip generations the offsets remain the same unless there is an architectural issue.
> Can you provide a quick example of what one entry would be?
arch/arm/boot/dts/versatile-ab.dts
and actually 90% of DTS... it's rather a challange to find such
fine-grained iomap.
Best regards,
Krzysztof
On Thu, Mar 10, 2022 at 01:52:24PM -0600, [email protected] wrote:
> From: Nick Hawkins <[email protected]>
>
> Creating binding for gxp timer in device tree hpe,gxp-timer
> Although there are multiple times on the SoC we are only
> enabling one at this time.
>
> Signed-off-by: Nick Hawkins <[email protected]>
>
> ----
>
> v2:
> *Removed maintainer change from patch
> *Verified there was no compilation errors
> *Added reference code in separate patch of patchset
> ---
> .../bindings/timer/hpe,gxp-timer.yaml | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
> new file mode 100644
> index 000000000000..1f4e345c5fb8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/hpe,gxp-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HPE GXP TIMER
> +
> +maintainers:
> + - Nick Hawkins <[email protected]>
> + - Jean-Marie Verdun <[email protected]>
> +
> +properties:
> + compatible:
> + const: hpe,gxp-timer
> +
> + reg:
> + items:
> + - description: T0CNT register
> + - description: T0CS register
> + - description: TIMELO register
Is the spec public to know what T0CNT, T0CS, and TIMELO are?
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-frequency:
> + description: The frequency of the clock that drives the counter, in Hz.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clock-frequency
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + timer@10003000 {
> + compatible = "hpe,gxp-timer";
> + reg = <0xc0000080 0x1>, <0xc0000094 0x01>, <0xc0000088 0x08>;
Based on the driver these are 4 bytes, 1 byte, 4 bytes in size.
Are there other registers in 0x80-0x95 range or do these offsets change
in other chips? If not, just 1 entry covering the whole thing would be
better.
> + interrupts = <0>;
> + interrupt-parent = <&vic0>;
> + clock-frequency = <400000000>;
> + };
> --
> 2.17.1
>
>