This patchset supports some dfl device drivers written in userspace.
There are some Q&A about why UIO driver is needed in v11:
From Greg:
Why are you saying that an ethernet driver should be using the UIO
interface?
And why can't you use the existing UIO drivers that bind to memory
regions specified by firmware? Without an interrupt being used, why is
UIO needed at all?
From Moritz:
Essentially I see two options:
- Have a DFL bus driver instantiate a platform driver (uio_pdrv_genirq)
which I *think* you described above?
- What this patch implements -- a UIO driver on the DFL bus
These FPGA devices can on the fly change their contents and -- even if
just for test -- being able to expose a bunch of registers via UIO can
be extremely useful.
Whether a device should expose registers or not should be up to the
implemeneter of the FPGA design I think (policy). This patch (or the
previous version) provides a mechanism to do so via DFL.
This is similar in nature to uio_pdrv_genirq on a DT based platform, to
expose the registers you instantiate the DT node.
Re-implementing a new driver for each of these instances doesn't seem
desirable and tying DFL as enumeration mechanism to UIO seems like a
good compromise for enabling this kind of functionality.
Note this is *not* an attempt to bypass the network stack or other
existing subsystems.
See the original message in:
https://lore.kernel.org/linux-fpga/[email protected]/T/#m66ba2c96848e3dea38d1a4f16dfea3cb291f7975
From Yilun:
The ETH GROUP IP is not designed as the full functional ethernet
controller. It is specially developed for the Intel N3000 NIC. Since it
is an FPGA based card, it is designed for the users to runtime reload
part of the MAC layer logic developed by themselves, while the ETH GROUP
is another part of the MAC which is not expected to be reloaded by
customers, but it provides some configurations for software to work with
the user logic.
So I category the feature as the devices that "designed for specific
purposes and does not fit into one of the standard kernel subsystems".
Some related description could be found in Patch #2, to illustrate why
using UIO for some DFL devices.
There are now UIO drivers for PCI or platform devices, but in this case
we are going to export a DFL(Device Feature List) bus device to
userspace, a DFL driver for UIO is needed to bind to it.
See the original message in:
https://lore.kernel.org/linux-fpga/[email protected]/T/#m91b303fd61485644353fad1e1e9c11d528844684
Xu Yilun (2):
uio: uio_dfl: add userspace i/o driver for DFL bus
Documentation: fpga: dfl: Add description for DFL UIO support
Documentation/fpga/dfl.rst | 26 ++++++++++++++++++
MAINTAINERS | 1 +
drivers/uio/Kconfig | 17 ++++++++++++
drivers/uio/Makefile | 1 +
drivers/uio/uio_dfl.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 111 insertions(+)
create mode 100644 drivers/uio/uio_dfl.c
--
2.7.4
This patch adds description for UIO support for dfl devices on DFL
bus.
Signed-off-by: Xu Yilun <[email protected]>
Reviewed-by: Tom Rix <[email protected]>
Reviewed-by: Wu Hao <[email protected]>
---
v2: no doc in v1, add it for v2.
v3: some documentation fixes.
v4: documentation change since the driver matching is changed.
v5: no change.
v6: improve the title of the userspace driver support section.
some word improvement.
v7: rebased to next-20210119
v8: some doc fixes.
v9: some doc change since we switch to the driver in drivers/uio.
v10: no change.
v11: add description that interrupt support is not implemented yet.
v12: rebase to 5.12-rc2, no change
---
Documentation/fpga/dfl.rst | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index c41ac76..f3a1223 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -7,6 +7,7 @@ Authors:
- Enno Luebbers <[email protected]>
- Xiao Guangrong <[email protected]>
- Wu Hao <[email protected]>
+- Xu Yilun <[email protected]>
The Device Feature List (DFL) FPGA framework (and drivers according to
this framework) hides the very details of low layer hardwares and provides
@@ -530,6 +531,31 @@ Being able to specify more than one DFL per BAR has been considered, but it
was determined the use case did not provide value. Specifying a single DFL
per BAR simplifies the implementation and allows for extra error checking.
+
+Userspace driver support for DFL devices
+========================================
+The purpose of an FPGA is to be reprogrammed with newly developed hardware
+components. New hardware can instantiate a new private feature in the DFL, and
+then present a DFL device in the system. In some cases users may need a
+userspace driver for the DFL device:
+
+* Users may need to run some diagnostic test for their hardware.
+* Users may prototype the kernel driver in user space.
+* Some hardware is designed for specific purposes and does not fit into one of
+ the standard kernel subsystems.
+
+This requires direct access to MMIO space and interrupt handling from
+userspace. The uio_dfl module exposes the UIO device interfaces for this
+purpose.
+
+Currently the uio_dfl driver only supports the Ether Group sub feature, which
+has no irq in hardware. So the interrupt handling is not added in this driver.
+
+UIO_DFL should be selected to enable the uio_dfl module driver. To support a
+new DFL feature via UIO direct access, its feature id should be added to the
+driver's id_table.
+
+
Open discussion
===============
FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
--
2.7.4
Hi Greg:
I listed below some answers from Moritz and Yilun from previous mails for
your question.
Do you have more comments?
Thanks in advance,
Yilun
On Mon, Mar 08, 2021 at 09:59:34AM +0800, Xu Yilun wrote:
> This patchset supports some dfl device drivers written in userspace.
>
> There are some Q&A about why UIO driver is needed in v11:
>
> >From Greg:
> Why are you saying that an ethernet driver should be using the UIO
> interface?
>
> And why can't you use the existing UIO drivers that bind to memory
> regions specified by firmware? Without an interrupt being used, why is
> UIO needed at all?
>
> >From Moritz:
> Essentially I see two options:
> - Have a DFL bus driver instantiate a platform driver (uio_pdrv_genirq)
> which I *think* you described above?
> - What this patch implements -- a UIO driver on the DFL bus
>
> These FPGA devices can on the fly change their contents and -- even if
> just for test -- being able to expose a bunch of registers via UIO can
> be extremely useful.
>
> Whether a device should expose registers or not should be up to the
> implemeneter of the FPGA design I think (policy). This patch (or the
> previous version) provides a mechanism to do so via DFL.
>
> This is similar in nature to uio_pdrv_genirq on a DT based platform, to
> expose the registers you instantiate the DT node.
>
> Re-implementing a new driver for each of these instances doesn't seem
> desirable and tying DFL as enumeration mechanism to UIO seems like a
> good compromise for enabling this kind of functionality.
>
> Note this is *not* an attempt to bypass the network stack or other
> existing subsystems.
>
> See the original message in:
> https://lore.kernel.org/linux-fpga/[email protected]/T/#m66ba2c96848e3dea38d1a4f16dfea3cb291f7975
>
>
> >From Yilun:
> The ETH GROUP IP is not designed as the full functional ethernet
> controller. It is specially developed for the Intel N3000 NIC. Since it
> is an FPGA based card, it is designed for the users to runtime reload
> part of the MAC layer logic developed by themselves, while the ETH GROUP
> is another part of the MAC which is not expected to be reloaded by
> customers, but it provides some configurations for software to work with
> the user logic.
>
> So I category the feature as the devices that "designed for specific
> purposes and does not fit into one of the standard kernel subsystems".
> Some related description could be found in Patch #2, to illustrate why
> using UIO for some DFL devices.
>
> There are now UIO drivers for PCI or platform devices, but in this case
> we are going to export a DFL(Device Feature List) bus device to
> userspace, a DFL driver for UIO is needed to bind to it.
>
> See the original message in:
> https://lore.kernel.org/linux-fpga/[email protected]/T/#m91b303fd61485644353fad1e1e9c11d528844684
>
>
> Xu Yilun (2):
> uio: uio_dfl: add userspace i/o driver for DFL bus
> Documentation: fpga: dfl: Add description for DFL UIO support
>
> Documentation/fpga/dfl.rst | 26 ++++++++++++++++++
> MAINTAINERS | 1 +
> drivers/uio/Kconfig | 17 ++++++++++++
> drivers/uio/Makefile | 1 +
> drivers/uio/uio_dfl.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 111 insertions(+)
> create mode 100644 drivers/uio/uio_dfl.c
>
> --
> 2.7.4
Hi Moritz:
Sorry I need to get back to you again, seems no more comments from Greg.
The patchset is stuck here for more than 1 month. Do you have some
more suggestion that could make it move forward? Do you have some more
comments? Or give an acked-by? Or could you apply it to your fpga branch
and go with next pull request?
Thanks,
Yilun
On Mon, Mar 08, 2021 at 09:59:34AM +0800, Xu Yilun wrote:
> This patchset supports some dfl device drivers written in userspace.
>
> There are some Q&A about why UIO driver is needed in v11:
>
> >From Greg:
> Why are you saying that an ethernet driver should be using the UIO
> interface?
>
> And why can't you use the existing UIO drivers that bind to memory
> regions specified by firmware? Without an interrupt being used, why is
> UIO needed at all?
>
> >From Moritz:
> Essentially I see two options:
> - Have a DFL bus driver instantiate a platform driver (uio_pdrv_genirq)
> which I *think* you described above?
> - What this patch implements -- a UIO driver on the DFL bus
>
> These FPGA devices can on the fly change their contents and -- even if
> just for test -- being able to expose a bunch of registers via UIO can
> be extremely useful.
>
> Whether a device should expose registers or not should be up to the
> implemeneter of the FPGA design I think (policy). This patch (or the
> previous version) provides a mechanism to do so via DFL.
>
> This is similar in nature to uio_pdrv_genirq on a DT based platform, to
> expose the registers you instantiate the DT node.
>
> Re-implementing a new driver for each of these instances doesn't seem
> desirable and tying DFL as enumeration mechanism to UIO seems like a
> good compromise for enabling this kind of functionality.
>
> Note this is *not* an attempt to bypass the network stack or other
> existing subsystems.
>
> See the original message in:
> https://lore.kernel.org/linux-fpga/[email protected]/T/#m66ba2c96848e3dea38d1a4f16dfea3cb291f7975
>
>
> >From Yilun:
> The ETH GROUP IP is not designed as the full functional ethernet
> controller. It is specially developed for the Intel N3000 NIC. Since it
> is an FPGA based card, it is designed for the users to runtime reload
> part of the MAC layer logic developed by themselves, while the ETH GROUP
> is another part of the MAC which is not expected to be reloaded by
> customers, but it provides some configurations for software to work with
> the user logic.
>
> So I category the feature as the devices that "designed for specific
> purposes and does not fit into one of the standard kernel subsystems".
> Some related description could be found in Patch #2, to illustrate why
> using UIO for some DFL devices.
>
> There are now UIO drivers for PCI or platform devices, but in this case
> we are going to export a DFL(Device Feature List) bus device to
> userspace, a DFL driver for UIO is needed to bind to it.
>
> See the original message in:
> https://lore.kernel.org/linux-fpga/[email protected]/T/#m91b303fd61485644353fad1e1e9c11d528844684
>
>
> Xu Yilun (2):
> uio: uio_dfl: add userspace i/o driver for DFL bus
> Documentation: fpga: dfl: Add description for DFL UIO support
>
> Documentation/fpga/dfl.rst | 26 ++++++++++++++++++
> MAINTAINERS | 1 +
> drivers/uio/Kconfig | 17 ++++++++++++
> drivers/uio/Makefile | 1 +
> drivers/uio/uio_dfl.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 111 insertions(+)
> create mode 100644 drivers/uio/uio_dfl.c
>
> --
> 2.7.4
Hi Xu,
On Wed, Mar 24, 2021 at 04:22:17PM +0800, Xu Yilun wrote:
> Hi Moritz:
>
> Sorry I need to get back to you again, seems no more comments from Greg.
>
> The patchset is stuck here for more than 1 month. Do you have some
> more suggestion that could make it move forward? Do you have some more
> comments? Or give an acked-by? Or could you apply it to your fpga branch
> and go with next pull request?
In its current form it's a UIO driver and needs at least Greg's Acked-by
before I could apply it.
Greg, can you take another look?
>
> Thanks,
> Yilun
>
> On Mon, Mar 08, 2021 at 09:59:34AM +0800, Xu Yilun wrote:
> > This patchset supports some dfl device drivers written in userspace.
> >
> > There are some Q&A about why UIO driver is needed in v11:
> >
> > >From Greg:
> > Why are you saying that an ethernet driver should be using the UIO
> > interface?
> >
> > And why can't you use the existing UIO drivers that bind to memory
> > regions specified by firmware? Without an interrupt being used, why is
> > UIO needed at all?
> >
> > >From Moritz:
> > Essentially I see two options:
> > - Have a DFL bus driver instantiate a platform driver (uio_pdrv_genirq)
> > which I *think* you described above?
> > - What this patch implements -- a UIO driver on the DFL bus
> >
> > These FPGA devices can on the fly change their contents and -- even if
> > just for test -- being able to expose a bunch of registers via UIO can
> > be extremely useful.
> >
> > Whether a device should expose registers or not should be up to the
> > implemeneter of the FPGA design I think (policy). This patch (or the
> > previous version) provides a mechanism to do so via DFL.
> >
> > This is similar in nature to uio_pdrv_genirq on a DT based platform, to
> > expose the registers you instantiate the DT node.
> >
> > Re-implementing a new driver for each of these instances doesn't seem
> > desirable and tying DFL as enumeration mechanism to UIO seems like a
> > good compromise for enabling this kind of functionality.
> >
> > Note this is *not* an attempt to bypass the network stack or other
> > existing subsystems.
> >
> > See the original message in:
> > https://lore.kernel.org/linux-fpga/[email protected]/T/#m66ba2c96848e3dea38d1a4f16dfea3cb291f7975
> >
> >
> > >From Yilun:
> > The ETH GROUP IP is not designed as the full functional ethernet
> > controller. It is specially developed for the Intel N3000 NIC. Since it
> > is an FPGA based card, it is designed for the users to runtime reload
> > part of the MAC layer logic developed by themselves, while the ETH GROUP
> > is another part of the MAC which is not expected to be reloaded by
> > customers, but it provides some configurations for software to work with
> > the user logic.
> >
> > So I category the feature as the devices that "designed for specific
> > purposes and does not fit into one of the standard kernel subsystems".
> > Some related description could be found in Patch #2, to illustrate why
> > using UIO for some DFL devices.
> >
> > There are now UIO drivers for PCI or platform devices, but in this case
> > we are going to export a DFL(Device Feature List) bus device to
> > userspace, a DFL driver for UIO is needed to bind to it.
> >
> > See the original message in:
> > https://lore.kernel.org/linux-fpga/[email protected]/T/#m91b303fd61485644353fad1e1e9c11d528844684
> >
> >
> > Xu Yilun (2):
> > uio: uio_dfl: add userspace i/o driver for DFL bus
> > Documentation: fpga: dfl: Add description for DFL UIO support
> >
> > Documentation/fpga/dfl.rst | 26 ++++++++++++++++++
> > MAINTAINERS | 1 +
> > drivers/uio/Kconfig | 17 ++++++++++++
> > drivers/uio/Makefile | 1 +
> > drivers/uio/uio_dfl.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++
> > 5 files changed, 111 insertions(+)
> > create mode 100644 drivers/uio/uio_dfl.c
> >
> > --
> > 2.7.4
Thanks,
Moritz
On Tue, Mar 16, 2021 at 01:10:05PM +0800, Xu Yilun wrote:
> Hi Greg:
>
> I listed below some answers from Moritz and Yilun from previous mails for
> your question.
>
> Do you have more comments?
Nah, it's fine, now queued up, thanks.
greg k-h