2021-08-12 07:46:46

by Rajesh Patil

Subject: [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node

From: Roja Rani Yarubandi <[email protected]>

Update the compatible string as "qcom,geni-uart".
Add interconnects and power-domains. Split the pinctrl
functions and correct the gpio pins.

Signed-off-by: Roja Rani Yarubandi <[email protected]>
Signed-off-by: Rajesh Patil <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e461395..2dc7e8c 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -861,13 +861,18 @@
};

uart5: serial@994000 {
- compatible = "qcom,geni-debug-uart";
+ compatible = "qcom,geni-uart";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};

@@ -2255,9 +2260,24 @@
function = "qup04";
};

- qup_uart5_default: qup-uart5-default {
- pins = "gpio46", "gpio47";
- function = "qup13";
+ qup_uart5_cts: qup-uart5-cts {
+ pins = "gpio20";
+ function = "qup05";
+ };
+
+ qup_uart5_rts: qup-uart5-rts {
+ pins = "gpio21";
+ function = "qup05";
+ };
+
+ qup_uart5_tx: qup-uart5-tx {
+ pins = "gpio22";
+ function = "qup05";
+ };
+
+ qup_uart5_rx: qup-uart5-rx {
+ pins = "gpio23";
+ function = "qup05";
};

qup_uart6_cts: qup-uart6-cts {
--
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2021-08-12 17:46:11

by Matthias Kaehlcke

Subject: Re: [PATCH V5 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node

On Thu, Aug 12, 2021 at 01:11:15PM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <[email protected]>
>
> Update the compatible string as "qcom,geni-uart".
> Add interconnects and power-domains. Split the pinctrl
> functions and correct the gpio pins.
>
> Signed-off-by: Roja Rani Yarubandi <[email protected]>
> Signed-off-by: Rajesh Patil <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++-----
> 1 file changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e461395..2dc7e8c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -861,13 +861,18 @@
> };
>
> uart5: serial@994000 {
> - compatible = "qcom,geni-debug-uart";
> + compatible = "qcom,geni-uart";
> reg = <0 0x00994000 0 0x4000>;
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> pinctrl-names = "default";
> - pinctrl-0 = <&qup_uart5_default>;
> + pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
> + interconnect-names = "qup-core", "qup-config";
> status = "disabled";
> };
>
> @@ -2255,9 +2260,24 @@
> function = "qup04";
> };
>
> - qup_uart5_default: qup-uart5-default {
> - pins = "gpio46", "gpio47";
> - function = "qup13";

sc7280-idp.dtsi references this node, so if this patch is applied the SC7280
IDP DT would be broken, unless "[5/7] arm64: dts: sc7280: Configure debug
uart for sc7280-idp" is also applied. I think you need to squash the two
patches.