2021-08-23 10:05:53

by Claudiu Beznea

Subject: [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5

Hi,

The following patches enable UDDRC, DDR3 PHY, SECURAM and SHDWC IPs
on SAMA7G5.

Thank you,
Claudiu Beznea

Claudiu Beznea (3):
ARM: dts: at91: add ram bindings
ARM: dts: at91: add bindins for securam
ARM: dts: at91: add bindings for shdwc

arch/arm/boot/dts/at91-sama7g5ek.dts | 9 ++++++++
arch/arm/boot/dts/sama7g5.dtsi | 34 ++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)

--
2.25.1

2021-08-23 10:06:13

by Claudiu Beznea

Subject: [PATCH 2/3] ARM: dts: at91: add bindins for securam

Add bindings for securam.

Signed-off-by: Claudiu Beznea <[email protected]>
---
arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index ecabab4343b6..3a4315ac0eb0 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -75,6 +75,17 @@ soc {
#size-cells = <1>;
ranges;

+ securam: securam@e0000000 {
+ compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
+ reg = <0xe0000000 0x4000>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe0000000 0x4000>;
+ no-memory-wc;
+ status = "okay";
+ };
+
secumod: secumod@e0004000 {
compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
reg = <0xe0004000 0x4000>;
--
2.25.1

2021-08-23 12:20:33

by Alexandre Belloni

Subject: Re: [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5

On 23/08/2021 13:03:53+0300, Claudiu Beznea wrote:
> Hi,
>
> The following patches enable UDDRC, DDR3 PHY, SECURAM and SHDWC IPs
> on SAMA7G5.
>
> Thank you,
> Claudiu Beznea
>
> Claudiu Beznea (3):
> ARM: dts: at91: add ram bindings
> ARM: dts: at91: add bindins for securam
> ARM: dts: at91: add bindings for shdwc

I think you meant node instead of bindings.


--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com