Hi,
Thanks for spotting this. Some comments below.
On Sun, Feb 13, 2022 at 01:37:01AM +0100, Tobias Waldekranz wrote:
> +static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
> + struct phylink_config *config)
> +{
> + u8 cmode = chip->ports[port].cmode;
> +
> + config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
> +
> + if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
> + if (cmode == MV88E6185_PORT_STS_CMODE_PHY)
> + __set_bit(PHY_INTERFACE_MODE_MII,
> + config->supported_interfaces);
Hmm. First, note that with mv88e6xxx_get_caps(), you'll end up with both
MII and GMII here. GMII is necessary as that's the phylib default if no
one specifies anything different in the firmware description. I assume
you've noticed a problem because you specify MII for the internal ports
in firmware?
I'm wondering what the point of checking the cmode here is - if the port
is internal, won't this switch always have cmode == PHY?
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On Sun, Feb 13, 2022 at 12:58, "Russell King (Oracle)" <[email protected]> wrote:
> Hi,
>
> Thanks for spotting this. Some comments below.
>
> On Sun, Feb 13, 2022 at 01:37:01AM +0100, Tobias Waldekranz wrote:
>> +static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
>> + struct phylink_config *config)
>> +{
>> + u8 cmode = chip->ports[port].cmode;
>> +
>> + config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
>> +
>> + if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
>> + if (cmode == MV88E6185_PORT_STS_CMODE_PHY)
>> + __set_bit(PHY_INTERFACE_MODE_MII,
>> + config->supported_interfaces);
>
> Hmm. First, note that with mv88e6xxx_get_caps(), you'll end up with both
> MII and GMII here. GMII is necessary as that's the phylib default if no
I did notice that.
> one specifies anything different in the firmware description. I assume
> you've noticed a problem because you specify MII for the internal ports
> in firmware?
Precisely.
> I'm wondering what the point of checking the cmode here is - if the port
> is internal, won't this switch always have cmode == PHY?
For all intents and purposes: I think so. It is just that the functional
spec. also lists cmode == 4 == disabled (PHYDetect == 0) for the
internal ports. So I figured that there might be some way of strapping
ports as disabled that I had never come across.
Do you think we should drop it?
On Sun, Feb 13, 2022 at 04:32:51PM +0100, Tobias Waldekranz wrote:
> On Sun, Feb 13, 2022 at 12:58, "Russell King (Oracle)" <[email protected]> wrote:
> > I'm wondering what the point of checking the cmode here is - if the port
> > is internal, won't this switch always have cmode == PHY?
>
> For all intents and purposes: I think so. It is just that the functional
> spec. also lists cmode == 4 == disabled (PHYDetect == 0) for the
> internal ports. So I figured that there might be some way of strapping
> ports as disabled that I had never come across.
I don't think there is a way to pinstrap the internal ports. As far as
I can see, the only way would be for software to program PHY Detect to
zero.
If we wanted a port to be disabled, then describing it in firmware as
being enabled would be a bug. If it isn't described in firmware, the
DSA code won't even consider looking at the port.
> Do you think we should drop it?
I think so.
Thanks.
--
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FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!