2022-02-25 12:42:28

by Peng Fan (OSS)

Subject: [PATCH 2/2] clk: imx8mq: add 27m phy pll ref clock

From: Peng Fan <[email protected]>

According to pll documentation, the 3rd pll ref clock should be
hdmi phy 27m clock, not dummy clock.

Signed-off-by: Peng Fan <[email protected]>
---
drivers/clk/imx/clk-imx8mq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 83cc2b1c3294..a9e69b6355ed 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -25,7 +25,7 @@ static u32 share_count_sai6;
static u32 share_count_dcss;
static u32 share_count_nand;

-static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
--
2.25.1

2022-02-25 22:18:27

by Abel Vesa

Subject: Re: [PATCH 2/2] clk: imx8mq: add 27m phy pll ref clock

On 22-02-25 17:00:02, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> According to pll documentation, the 3rd pll ref clock should be
> hdmi phy 27m clock, not dummy clock.
>
> Signed-off-by: Peng Fan <[email protected]>

Reviewed-by: Abel Vesa <[email protected]>

> ---
> drivers/clk/imx/clk-imx8mq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 83cc2b1c3294..a9e69b6355ed 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -25,7 +25,7 @@ static u32 share_count_sai6;
> static u32 share_count_dcss;
> static u32 share_count_nand;
>
> -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
> +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", };
> static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
> static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
> --
> 2.25.1
>

2022-04-07 21:03:25

by Abel Vesa

Subject: Re: [PATCH 2/2] clk: imx8mq: add 27m phy pll ref clock

On 22-02-25 17:00:02, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> According to pll documentation, the 3rd pll ref clock should be
> hdmi phy 27m clock, not dummy clock.
>
> Signed-off-by: Peng Fan <[email protected]>

Applied, thanks!

> ---
> drivers/clk/imx/clk-imx8mq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 83cc2b1c3294..a9e69b6355ed 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -25,7 +25,7 @@ static u32 share_count_sai6;
> static u32 share_count_dcss;
> static u32 share_count_nand;
>
> -static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
> +static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", };
> static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
> static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
> --
> 2.25.1
>