2023-06-30 19:56:14

by Mario Limonciello

Subject: [PATCH 3/4] pinctrl: amd: Unify debounce handling into amd_pinconf_set()

Debounce handling is done in two different entry points in the driver.
Unify this to make sure that it's always handled the same.

Signed-off-by: Mario Limonciello <[email protected]>
---
drivers/pinctrl/pinctrl-amd.c | 38 +++++++++++++++--------------------
1 file changed, 16 insertions(+), 22 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index cd46a5200f9b4..a22e02e2f5d35 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -115,16 +115,12 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}

-static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
- unsigned debounce)
+static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned offset,
+ unsigned debounce)
{
u32 time;
u32 pin_reg;
int ret = 0;
- unsigned long flags;
- struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
-
- raw_spin_lock_irqsave(&gpio_dev->lock, flags);

/* Use special handling for Pin0 debounce */
if (offset == 0) {
@@ -183,23 +179,10 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
}
writel(pin_reg, gpio_dev->base + offset * 4);
- raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);

return ret;
}

-static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
- unsigned long config)
-{
- u32 debounce;
-
- if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
- return -ENOTSUPP;
-
- debounce = pinconf_to_config_argument(config);
- return amd_gpio_set_debounce(gc, offset, debounce);
-}
-
#ifdef CONFIG_DEBUG_FS
static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
@@ -794,9 +777,8 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,

switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
- pin_reg &= ~DB_TMR_OUT_MASK;
- pin_reg |= arg & DB_TMR_OUT_MASK;
- break;
+ ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
+ goto out;

case PIN_CONFIG_BIAS_PULL_DOWN:
pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
@@ -823,6 +805,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,

writel(pin_reg, gpio_dev->base + pin*4);
}
+out:
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);

return ret;
@@ -864,6 +847,17 @@ static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
return 0;
}

+static int amd_gpio_set_config(struct gpio_chip *gc, unsigned pin,
+ unsigned long config)
+{
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+ if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
+ return -ENOTSUPP;
+
+ return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
+}
+
static const struct pinconf_ops amd_pinconf_ops = {
.pin_config_get = amd_pinconf_get,
.pin_config_set = amd_pinconf_set,
--
2.34.1

2023-07-03 21:48:13

by Andy Shevchenko

Subject: Re: [PATCH 3/4] pinctrl: amd: Unify debounce handling into amd_pinconf_set()

Fri, Jun 30, 2023 at 02:47:15PM -0500, Mario Limonciello kirjoitti:
> Debounce handling is done in two different entry points in the driver.
> Unify this to make sure that it's always handled the same.

...

> -static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
> - unsigned debounce)
> +static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned offset,
> + unsigned debounce)

Side note: Are you going to fix unsigned --> unsigned int?
The former is discouraged.

...

> +out:

out_unlock: ?

> raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
>
> return ret;

--
With Best Regards,
Andy Shevchenko

2023-07-04 02:22:09

by Mario Limonciello

Subject: Re: [PATCH 3/4] pinctrl: amd: Unify debounce handling into amd_pinconf_set()

On 7/3/23 16:33, [email protected] wrote:
> Fri, Jun 30, 2023 at 02:47:15PM -0500, Mario Limonciello kirjoitti:
>> Debounce handling is done in two different entry points in the driver.
>> Unify this to make sure that it's always handled the same.
>
> ...
>
>> -static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
>> - unsigned debounce)
>> +static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned offset,
>> + unsigned debounce)
>
> Side note: Are you going to fix unsigned --> unsigned int?
> The former is discouraged.
>
> ...
>
>> +out:
>
> out_unlock: ?
>
>> raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
>>
>> return ret;
>

Ack, thanks will adjust both.