Hi,
This patchset adds initial rudimentary support for the StarFive
Pulse Width Modulation controller driver. And this driver will
be used in StarFive's VisionFive 2 board.The first patch add
Documentations for the device and Patch 2 adds device probe for
the module.
Changes v4->v5:
- Rebased to v6.6rc2.
- Updated macro definition indent.
- Replaced the clock initializes the interface.
- Fixed patch description.
Changes v3->v4:
- Rebased to v6.5rc7.
- Sorted the header files in alphabetic order.
- Changed iowrite32() to writel().
- Added a way to turn off.
- Moified polarity inversion implementation.
- Added 7100 support.
- Added dts patches.
- Used the various helpers in linux/math.h.
- Corrected formatting problems.
- Renamed dtbinding to 'starfive,jh7100-pwm.yaml'.
- Dropped the redundant code.
Changes v2->v3:
- Fixed some formatting issues.
Changes v1->v2:
- Renamed the dt-binding 'pwm-starfive.yaml' to 'starfive,jh7110-pwm.yaml'.
- Dropped the compatible's Items.
- Dropped the unuse defines.
- Modified the code to follow the Linux coding style.
- Changed return value to dev_err_probe.
- Dropped the unnecessary local variable.
The patch series is based on v6.6rc2.
William Qiu (4):
dt-bindings: pwm: Add StarFive PWM module
pwm: starfive: Add PWM driver support
riscv: dts: starfive: jh7110: Add PWM node and pins configuration
riscv: dts: starfive: jh7100: Add PWM node and pins configuration
.../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++
MAINTAINERS | 7 +
.../boot/dts/starfive/jh7100-common.dtsi | 24 +++
arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +
.../jh7110-starfive-visionfive-2.dtsi | 22 ++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +
drivers/pwm/Kconfig | 9 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-starfive.c | 190 ++++++++++++++++++
9 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
create mode 100644 drivers/pwm/pwm-starfive.c
--
2.34.1
Add StarFive JH7110 PWM controller node and add PWM pins configuration
on VisionFive 2 board.
Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index d79f94432b27..4bfb8f0f810f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -268,6 +268,12 @@ reserved-data@600000 {
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
@@ -402,6 +408,22 @@ GPOEN_SYS_SDIO1_DATA3,
};
};
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+ GPOEN_SYS_PWM0_CHANNEL0,
+ GPI_NONE)>,
+ <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+ GPOEN_SYS_PWM0_CHANNEL1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
spi0_pins: spi0-0 {
mosi-pins {
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index e85464c328d0..c1f97c5a8ab5 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -736,6 +736,15 @@ spi6: spi@120a0000 {
status = "disabled";
};
+ pwm: pwm@120d0000 {
+ compatible = "starfive,jh7110-pwm";
+ reg = <0x0 0x120d0000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
+ resets = <&syscrg JH7110_SYSRST_PWM_APB>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
sfctemp: temperature-sensor@120e0000 {
compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;
--
2.34.1
Add StarFive JH7100 PWM controller node and add PWM pins configuration
on VisionFive 1 board.
Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
.../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++
2 files changed, 33 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index b93ce351a90f..11876906cc05 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN,
};
};
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(7,
+ GPO_PWM_PAD_OUT_BIT0,
+ GPO_PWM_PAD_OE_N_BIT0,
+ GPI_NONE)>,
+ <GPIOMUX(5,
+ GPO_PWM_PAD_OUT_BIT1,
+ GPO_PWM_PAD_OE_N_BIT1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <35>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -154,6 +172,12 @@ &osc_aud {
clock-frequency = <27000000>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 35ab54fb235f..9c8c557031e6 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -274,6 +274,15 @@ watchdog@12480000 {
<&rstgen JH7100_RSTN_WDT>;
};
+ pwm: pwm@12490000 {
+ compatible = "starfive,jh7100-pwm";
+ reg = <0x0 0x12490000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_PWM_APB>;
+ resets = <&rstgen JH7100_RSTN_PWM_APB>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
sfctemp: temperature-sensor@124a0000 {
compatible = "starfive,jh7100-temp";
reg = <0x0 0x124a0000 0x0 0x10000>;
--
2.34.1
Add Pulse Width Modulation driver support for StarFive
JH7100 and JH7110 SoC.
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Signed-off-by: William Qiu <[email protected]>
---
MAINTAINERS | 7 ++
drivers/pwm/Kconfig | 9 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++
4 files changed, 207 insertions(+)
create mode 100644 drivers/pwm/pwm-starfive.c
diff --git a/MAINTAINERS b/MAINTAINERS
index bf0f54c24f81..bc2155bd2712 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
+STARFIVE JH71X0 PWM DRIVERS
+M: William Qiu <[email protected]>
+M: Hal Feng <[email protected]>
+S: Supported
+F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
+F: drivers/pwm/pwm-starfive-ptc.c
+
STARFIVE JH71X0 RESET CONTROLLER DRIVERS
M: Emil Renner Berthing <[email protected]>
M: Hal Feng <[email protected]>
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 8ebcddf91f7b..e2ee0169f6e4 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -569,6 +569,15 @@ config PWM_SPRD
To compile this driver as a module, choose M here: the module
will be called pwm-sprd.
+config PWM_STARFIVE
+ tristate "StarFive PWM support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ help
+ Generic PWM framework driver for StarFive SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-starfive.
+
config PWM_STI
tristate "STiH4xx PWM support"
depends on ARCH_STI || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c822389c2a24..93b954376873 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
+obj-$(CONFIG_PWM_STARFIVE) += pwm-starfive.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c
new file mode 100644
index 000000000000..d390349fc95d
--- /dev/null
+++ b/drivers/pwm/pwm-starfive.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PWM driver for the StarFive JH71x0 SoC
+ *
+ * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+/* Access PTC register (CNTR, HRC, LRC and CTRL) */
+#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + (((N) > 3) ? \
+ (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
+#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
+#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
+#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
+#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
+
+/* PTC_RPTC_CTRL register bits*/
+#define PTC_EN BIT(0)
+#define PTC_ECLK BIT(1)
+#define PTC_NEC BIT(2)
+#define PTC_OE BIT(3)
+#define PTC_SIGNLE BIT(4)
+#define PTC_INTE BIT(5)
+#define PTC_INT BIT(6)
+#define PTC_CNTRRST BIT(7)
+#define PTC_CAPTE BIT(8)
+
+struct starfive_pwm_ptc_device {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct reset_control *rst;
+ void __iomem *regs;
+ u32 clk_rate; /* PWM APB clock frequency */
+};
+
+static inline struct starfive_pwm_ptc_device *
+chip_to_starfive_ptc(struct pwm_chip *chip)
+
+{
+ return container_of(chip, struct starfive_pwm_ptc_device, chip);
+}
+
+static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
+ struct pwm_device *dev,
+ struct pwm_state *state)
+{
+ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
+ u32 period_data, duty_data, ctrl_data;
+
+ period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
+ duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
+ ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+
+ state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
+ state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
+ state->polarity = PWM_POLARITY_INVERSED;
+ state->enabled = (ctrl_data & PTC_EN) ? true : false;
+
+ return 0;
+}
+
+static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
+ struct pwm_device *dev,
+ const struct pwm_state *state)
+{
+ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
+ u32 period_data, duty_data, ctrl_data = 0;
+
+ if (state->polarity != PWM_POLARITY_INVERSED)
+ return -EINVAL;
+
+ period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
+ NSEC_PER_SEC);
+ duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
+ NSEC_PER_SEC);
+
+ writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
+ writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
+ writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
+
+ ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+ if (state->enabled)
+ writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+ else
+ writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
+
+ return 0;
+}
+
+static const struct pwm_ops starfive_pwm_ptc_ops = {
+ .get_state = starfive_pwm_ptc_get_state,
+ .apply = starfive_pwm_ptc_apply,
+ .owner = THIS_MODULE,
+};
+
+static int starfive_pwm_ptc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct starfive_pwm_ptc_device *pwm;
+ struct pwm_chip *chip;
+ int ret;
+
+ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ return -ENOMEM;
+
+ chip = &pwm->chip;
+ chip->dev = dev;
+ chip->ops = &starfive_pwm_ptc_ops;
+ chip->npwm = 8;
+ chip->of_pwm_n_cells = 3;
+
+ pwm->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pwm->regs))
+ return dev_err_probe(dev, PTR_ERR(pwm->regs),
+ "Unable to map IO resources\n");
+
+ pwm->clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(pwm->clk))
+ return dev_err_probe(dev, PTR_ERR(pwm->clk),
+ "Unable to get pwm's clock\n");
+
+ pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(pwm->rst))
+ return dev_err_probe(dev, PTR_ERR(pwm->rst),
+ "Unable to get pwm's reset\n");
+
+ ret = reset_control_deassert(pwm->rst);
+ if (ret) {
+ dev_err(dev, "Failed to enable clock for pwm: %d\n", ret);
+ return ret;
+ }
+
+ pwm->clk_rate = clk_get_rate(pwm->clk);
+ if (pwm->clk_rate <= 0) {
+ dev_warn(dev, "Failed to get APB clock rate\n");
+ return -EINVAL;
+ }
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret < 0) {
+ dev_err(dev, "Cannot register PTC: %d\n", ret);
+ clk_disable_unprepare(pwm->clk);
+ reset_control_assert(pwm->rst);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pwm);
+
+ return 0;
+}
+
+static int starfive_pwm_ptc_remove(struct platform_device *dev)
+{
+ struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
+
+ reset_control_assert(pwm->rst);
+ clk_disable_unprepare(pwm->clk);
+
+ return 0;
+}
+
+static const struct of_device_id starfive_pwm_ptc_of_match[] = {
+ { .compatible = "starfive,jh7100-pwm" },
+ { .compatible = "starfive,jh7110-pwm" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
+
+static struct platform_driver starfive_pwm_ptc_driver = {
+ .probe = starfive_pwm_ptc_probe,
+ .remove = starfive_pwm_ptc_remove,
+ .driver = {
+ .name = "pwm-starfive-ptc",
+ .of_match_table = starfive_pwm_ptc_of_match,
+ },
+};
+module_platform_driver(starfive_pwm_ptc_driver);
+
+MODULE_AUTHOR("Jieqin Chen");
+MODULE_AUTHOR("Hal Feng <[email protected]>");
+MODULE_DESCRIPTION("StarFive PWM PTC driver");
+MODULE_LICENSE("GPL");
--
2.34.1
William Qiu wrote:
> Add Pulse Width Modulation driver support for StarFive
> JH7100 and JH7110 SoC.
>
> Co-developed-by: Hal Feng <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
> ---
> MAINTAINERS | 7 ++
> drivers/pwm/Kconfig | 9 ++
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++
> 4 files changed, 207 insertions(+)
> create mode 100644 drivers/pwm/pwm-starfive.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bf0f54c24f81..bc2155bd2712 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
> F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
> F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
>
> +STARFIVE JH71X0 PWM DRIVERS
> +M: William Qiu <[email protected]>
> +M: Hal Feng <[email protected]>
> +S: Supported
> +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
> +F: drivers/pwm/pwm-starfive-ptc.c
> +
> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
> M: Emil Renner Berthing <[email protected]>
> M: Hal Feng <[email protected]>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 8ebcddf91f7b..e2ee0169f6e4 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -569,6 +569,15 @@ config PWM_SPRD
> To compile this driver as a module, choose M here: the module
> will be called pwm-sprd.
>
> +config PWM_STARFIVE
> + tristate "StarFive PWM support"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + help
> + Generic PWM framework driver for StarFive SoCs.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-starfive.
> +
> config PWM_STI
> tristate "STiH4xx PWM support"
> depends on ARCH_STI || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index c822389c2a24..93b954376873 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
> obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
> +obj-$(CONFIG_PWM_STARFIVE) += pwm-starfive.o
> obj-$(CONFIG_PWM_STI) += pwm-sti.o
> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
> diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c
Hi William,
You never answered my questions about what PTC is short for and if there are
other PWMs on the JH7110. You just removed -ptc from the name of this file..
> new file mode 100644
> index 000000000000..d390349fc95d
> --- /dev/null
> +++ b/drivers/pwm/pwm-starfive.c
> @@ -0,0 +1,190 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PWM driver for the StarFive JH71x0 SoC
> + *
> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +/* Access PTC register (CNTR, HRC, LRC and CTRL) */
> +#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + (((N) > 3) ? \
> + (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
> +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
> +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
> +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
> +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
..but these defines
> +
> +/* PTC_RPTC_CTRL register bits*/
> +#define PTC_EN BIT(0)
> +#define PTC_ECLK BIT(1)
> +#define PTC_NEC BIT(2)
> +#define PTC_OE BIT(3)
> +#define PTC_SIGNLE BIT(4)
> +#define PTC_INTE BIT(5)
> +#define PTC_INT BIT(6)
> +#define PTC_CNTRRST BIT(7)
> +#define PTC_CAPTE BIT(8)
..and these defines are still prefixed with *PTC where I'd expect something like
STARFIVE_PWM_, and below structs and function names are also still
using starfive_pwm_ptc_
where I'd expect starfive_pwm_. Please be consistant in your naming.
> +struct starfive_pwm_ptc_device {
> + struct pwm_chip chip;
> + struct clk *clk;
> + struct reset_control *rst;
> + void __iomem *regs;
> + u32 clk_rate; /* PWM APB clock frequency */
> +};
> +
> +static inline struct starfive_pwm_ptc_device *
> +chip_to_starfive_ptc(struct pwm_chip *chip)
> +
> +{
> + return container_of(chip, struct starfive_pwm_ptc_device, chip);
> +}
> +
> +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
> + struct pwm_device *dev,
> + struct pwm_state *state)
> +{
> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
> + u32 period_data, duty_data, ctrl_data;
> +
> + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
> + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> +
> + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
> + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
> + state->polarity = PWM_POLARITY_INVERSED;
> + state->enabled = (ctrl_data & PTC_EN) ? true : false;
> +
> + return 0;
> +}
> +
> +static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
> + struct pwm_device *dev,
> + const struct pwm_state *state)
> +{
> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
> + u32 period_data, duty_data, ctrl_data = 0;
> +
> + if (state->polarity != PWM_POLARITY_INVERSED)
> + return -EINVAL;
> +
> + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
> + NSEC_PER_SEC);
> + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
> + NSEC_PER_SEC);
> +
> + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
> + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
> + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
> +
> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> + if (state->enabled)
> + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> + else
> + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> +
> + return 0;
> +}
> +
> +static const struct pwm_ops starfive_pwm_ptc_ops = {
> + .get_state = starfive_pwm_ptc_get_state,
> + .apply = starfive_pwm_ptc_apply,
> + .owner = THIS_MODULE,
> +};
> +
> +static int starfive_pwm_ptc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct starfive_pwm_ptc_device *pwm;
> + struct pwm_chip *chip;
> + int ret;
> +
> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
> + if (!pwm)
> + return -ENOMEM;
> +
> + chip = &pwm->chip;
> + chip->dev = dev;
> + chip->ops = &starfive_pwm_ptc_ops;
> + chip->npwm = 8;
> + chip->of_pwm_n_cells = 3;
> +
> + pwm->regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(pwm->regs))
> + return dev_err_probe(dev, PTR_ERR(pwm->regs),
> + "Unable to map IO resources\n");
> +
> + pwm->clk = devm_clk_get_enabled(dev, NULL);
> + if (IS_ERR(pwm->clk))
> + return dev_err_probe(dev, PTR_ERR(pwm->clk),
> + "Unable to get pwm's clock\n");
> +
> + pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
> + if (IS_ERR(pwm->rst))
> + return dev_err_probe(dev, PTR_ERR(pwm->rst),
> + "Unable to get pwm's reset\n");
> +
> + ret = reset_control_deassert(pwm->rst);
> + if (ret) {
> + dev_err(dev, "Failed to enable clock for pwm: %d\n", ret);
> + return ret;
> + }
> +
> + pwm->clk_rate = clk_get_rate(pwm->clk);
> + if (pwm->clk_rate <= 0) {
> + dev_warn(dev, "Failed to get APB clock rate\n");
> + return -EINVAL;
> + }
> +
> + ret = devm_pwmchip_add(dev, chip);
> + if (ret < 0) {
> + dev_err(dev, "Cannot register PTC: %d\n", ret);
> + clk_disable_unprepare(pwm->clk);
> + reset_control_assert(pwm->rst);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, pwm);
> +
> + return 0;
> +}
> +
> +static int starfive_pwm_ptc_remove(struct platform_device *dev)
> +{
> + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
> +
> + reset_control_assert(pwm->rst);
> + clk_disable_unprepare(pwm->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id starfive_pwm_ptc_of_match[] = {
> + { .compatible = "starfive,jh7100-pwm" },
> + { .compatible = "starfive,jh7110-pwm" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
> +
> +static struct platform_driver starfive_pwm_ptc_driver = {
> + .probe = starfive_pwm_ptc_probe,
> + .remove = starfive_pwm_ptc_remove,
> + .driver = {
> + .name = "pwm-starfive-ptc",
Here
> + .of_match_table = starfive_pwm_ptc_of_match,
> + },
> +};
> +module_platform_driver(starfive_pwm_ptc_driver);
> +
> +MODULE_AUTHOR("Jieqin Chen");
> +MODULE_AUTHOR("Hal Feng <[email protected]>");
> +MODULE_DESCRIPTION("StarFive PWM PTC driver");
..and here you're also still calling the driver PTC without explaining why.
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
>
On 2023/9/23 20:08, Emil Renner Berthing wrote:
> William Qiu wrote:
>> Add Pulse Width Modulation driver support for StarFive
>> JH7100 and JH7110 SoC.
>>
>> Co-developed-by: Hal Feng <[email protected]>
>> Signed-off-by: Hal Feng <[email protected]>
>> Signed-off-by: William Qiu <[email protected]>
>> ---
>> MAINTAINERS | 7 ++
>> drivers/pwm/Kconfig | 9 ++
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++
>> 4 files changed, 207 insertions(+)
>> create mode 100644 drivers/pwm/pwm-starfive.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index bf0f54c24f81..bc2155bd2712 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
>> F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
>> F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
>>
>> +STARFIVE JH71X0 PWM DRIVERS
>> +M: William Qiu <[email protected]>
>> +M: Hal Feng <[email protected]>
>> +S: Supported
>> +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
>> +F: drivers/pwm/pwm-starfive-ptc.c
>> +
>> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
>> M: Emil Renner Berthing <[email protected]>
>> M: Hal Feng <[email protected]>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index 8ebcddf91f7b..e2ee0169f6e4 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -569,6 +569,15 @@ config PWM_SPRD
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-sprd.
>>
>> +config PWM_STARFIVE
>> + tristate "StarFive PWM support"
>> + depends on ARCH_STARFIVE || COMPILE_TEST
>> + help
>> + Generic PWM framework driver for StarFive SoCs.
>> +
>> + To compile this driver as a module, choose M here: the module
>> + will be called pwm-starfive.
>> +
>> config PWM_STI
>> tristate "STiH4xx PWM support"
>> depends on ARCH_STI || COMPILE_TEST
>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> index c822389c2a24..93b954376873 100644
>> --- a/drivers/pwm/Makefile
>> +++ b/drivers/pwm/Makefile
>> @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
>> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
>> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
>> obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
>> +obj-$(CONFIG_PWM_STARFIVE) += pwm-starfive.o
>> obj-$(CONFIG_PWM_STI) += pwm-sti.o
>> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
>> obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
>> diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c
>
> Hi William,
>
> You never answered my questions about what PTC is short for and if there are
> other PWMs on the JH7110. You just removed -ptc from the name of this file..
>
Hi Emil,
The PTC, short for PWM/TIMER/CONUTER, comes from OpenCore's ip, but only PWM
mode is used in the JH7110. So the register still has the word "PTC".
s the best way to change all the prefix to STARFIVE?
Best regards,
William
>> new file mode 100644
>> index 000000000000..d390349fc95d
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-starfive.c
>> @@ -0,0 +1,190 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * PWM driver for the StarFive JH71x0 SoC
>> + *
>> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pwm.h>
>> +#include <linux/reset.h>
>> +#include <linux/slab.h>
>> +
>> +/* Access PTC register (CNTR, HRC, LRC and CTRL) */
>> +#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + (((N) > 3) ? \
>> + (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
>> +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
>> +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
>> +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
>> +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
>
> ..but these defines
>
>> +
>> +/* PTC_RPTC_CTRL register bits*/
>> +#define PTC_EN BIT(0)
>> +#define PTC_ECLK BIT(1)
>> +#define PTC_NEC BIT(2)
>> +#define PTC_OE BIT(3)
>> +#define PTC_SIGNLE BIT(4)
>> +#define PTC_INTE BIT(5)
>> +#define PTC_INT BIT(6)
>> +#define PTC_CNTRRST BIT(7)
>> +#define PTC_CAPTE BIT(8)
>
> ..and these defines are still prefixed with *PTC where I'd expect something like
> STARFIVE_PWM_, and below structs and function names are also still
> using starfive_pwm_ptc_
> where I'd expect starfive_pwm_. Please be consistant in your naming.
>
>> +struct starfive_pwm_ptc_device {
>> + struct pwm_chip chip;
>> + struct clk *clk;
>> + struct reset_control *rst;
>> + void __iomem *regs;
>> + u32 clk_rate; /* PWM APB clock frequency */
>> +};
>> +
>> +static inline struct starfive_pwm_ptc_device *
>> +chip_to_starfive_ptc(struct pwm_chip *chip)
>> +
>> +{
>> + return container_of(chip, struct starfive_pwm_ptc_device, chip);
>> +}
>> +
>> +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
>> + struct pwm_device *dev,
>> + struct pwm_state *state)
>> +{
>> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
>> + u32 period_data, duty_data, ctrl_data;
>> +
>> + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
>> + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
>> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> +
>> + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
>> + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
>> + state->polarity = PWM_POLARITY_INVERSED;
>> + state->enabled = (ctrl_data & PTC_EN) ? true : false;
>> +
>> + return 0;
>> +}
>> +
>> +static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
>> + struct pwm_device *dev,
>> + const struct pwm_state *state)
>> +{
>> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
>> + u32 period_data, duty_data, ctrl_data = 0;
>> +
>> + if (state->polarity != PWM_POLARITY_INVERSED)
>> + return -EINVAL;
>> +
>> + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
>> + NSEC_PER_SEC);
>> + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
>> + NSEC_PER_SEC);
>> +
>> + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
>> + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
>> + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
>> +
>> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> + if (state->enabled)
>> + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> + else
>> + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> +
>> + return 0;
>> +}
>> +
>> +static const struct pwm_ops starfive_pwm_ptc_ops = {
>> + .get_state = starfive_pwm_ptc_get_state,
>> + .apply = starfive_pwm_ptc_apply,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int starfive_pwm_ptc_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct starfive_pwm_ptc_device *pwm;
>> + struct pwm_chip *chip;
>> + int ret;
>> +
>> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
>> + if (!pwm)
>> + return -ENOMEM;
>> +
>> + chip = &pwm->chip;
>> + chip->dev = dev;
>> + chip->ops = &starfive_pwm_ptc_ops;
>> + chip->npwm = 8;
>> + chip->of_pwm_n_cells = 3;
>> +
>> + pwm->regs = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(pwm->regs))
>> + return dev_err_probe(dev, PTR_ERR(pwm->regs),
>> + "Unable to map IO resources\n");
>> +
>> + pwm->clk = devm_clk_get_enabled(dev, NULL);
>> + if (IS_ERR(pwm->clk))
>> + return dev_err_probe(dev, PTR_ERR(pwm->clk),
>> + "Unable to get pwm's clock\n");
>> +
>> + pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
>> + if (IS_ERR(pwm->rst))
>> + return dev_err_probe(dev, PTR_ERR(pwm->rst),
>> + "Unable to get pwm's reset\n");
>> +
>> + ret = reset_control_deassert(pwm->rst);
>> + if (ret) {
>> + dev_err(dev, "Failed to enable clock for pwm: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + pwm->clk_rate = clk_get_rate(pwm->clk);
>> + if (pwm->clk_rate <= 0) {
>> + dev_warn(dev, "Failed to get APB clock rate\n");
>> + return -EINVAL;
>> + }
>> +
>> + ret = devm_pwmchip_add(dev, chip);
>> + if (ret < 0) {
>> + dev_err(dev, "Cannot register PTC: %d\n", ret);
>> + clk_disable_unprepare(pwm->clk);
>> + reset_control_assert(pwm->rst);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, pwm);
>> +
>> + return 0;
>> +}
>> +
>> +static int starfive_pwm_ptc_remove(struct platform_device *dev)
>> +{
>> + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
>> +
>> + reset_control_assert(pwm->rst);
>> + clk_disable_unprepare(pwm->clk);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id starfive_pwm_ptc_of_match[] = {
>> + { .compatible = "starfive,jh7100-pwm" },
>> + { .compatible = "starfive,jh7110-pwm" },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
>> +
>> +static struct platform_driver starfive_pwm_ptc_driver = {
>> + .probe = starfive_pwm_ptc_probe,
>> + .remove = starfive_pwm_ptc_remove,
>> + .driver = {
>> + .name = "pwm-starfive-ptc",
>
> Here
>
>> + .of_match_table = starfive_pwm_ptc_of_match,
>> + },
>> +};
>> +module_platform_driver(starfive_pwm_ptc_driver);
>> +
>> +MODULE_AUTHOR("Jieqin Chen");
>> +MODULE_AUTHOR("Hal Feng <[email protected]>");
>> +MODULE_DESCRIPTION("StarFive PWM PTC driver");
>
> ..and here you're also still calling the driver PTC without explaining why.
>
>> +MODULE_LICENSE("GPL");
>> --
>> 2.34.1
>>
On 2023/9/25 18:31, Emil Renner Berthing wrote:
> William Qiu wrote:
>>
>>
>> On 2023/9/23 20:08, Emil Renner Berthing wrote:
>> > William Qiu wrote:
>> >> Add Pulse Width Modulation driver support for StarFive
>> >> JH7100 and JH7110 SoC.
>> >>
>> >> Co-developed-by: Hal Feng <[email protected]>
>> >> Signed-off-by: Hal Feng <[email protected]>
>> >> Signed-off-by: William Qiu <[email protected]>
>> >> ---
>> >> MAINTAINERS | 7 ++
>> >> drivers/pwm/Kconfig | 9 ++
>> >> drivers/pwm/Makefile | 1 +
>> >> drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++
>> >> 4 files changed, 207 insertions(+)
>> >> create mode 100644 drivers/pwm/pwm-starfive.c
>> >>
>> >> diff --git a/MAINTAINERS b/MAINTAINERS
>> >> index bf0f54c24f81..bc2155bd2712 100644
>> >> --- a/MAINTAINERS
>> >> +++ b/MAINTAINERS
>> >> @@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
>> >> F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
>> >> F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
>> >>
>> >> +STARFIVE JH71X0 PWM DRIVERS
>> >> +M: William Qiu <[email protected]>
>> >> +M: Hal Feng <[email protected]>
>> >> +S: Supported
>> >> +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
>> >> +F: drivers/pwm/pwm-starfive-ptc.c
>> >> +
>> >> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
>> >> M: Emil Renner Berthing <[email protected]>
>> >> M: Hal Feng <[email protected]>
>> >> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> >> index 8ebcddf91f7b..e2ee0169f6e4 100644
>> >> --- a/drivers/pwm/Kconfig
>> >> +++ b/drivers/pwm/Kconfig
>> >> @@ -569,6 +569,15 @@ config PWM_SPRD
>> >> To compile this driver as a module, choose M here: the module
>> >> will be called pwm-sprd.
>> >>
>> >> +config PWM_STARFIVE
>> >> + tristate "StarFive PWM support"
>> >> + depends on ARCH_STARFIVE || COMPILE_TEST
>> >> + help
>> >> + Generic PWM framework driver for StarFive SoCs.
>> >> +
>> >> + To compile this driver as a module, choose M here: the module
>> >> + will be called pwm-starfive.
>> >> +
>> >> config PWM_STI
>> >> tristate "STiH4xx PWM support"
>> >> depends on ARCH_STI || COMPILE_TEST
>> >> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> >> index c822389c2a24..93b954376873 100644
>> >> --- a/drivers/pwm/Makefile
>> >> +++ b/drivers/pwm/Makefile
>> >> @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
>> >> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
>> >> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
>> >> obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
>> >> +obj-$(CONFIG_PWM_STARFIVE) += pwm-starfive.o
>> >> obj-$(CONFIG_PWM_STI) += pwm-sti.o
>> >> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
>> >> obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
>> >> diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c
>> >
>> > Hi William,
>> >
>> > You never answered my questions about what PTC is short for and if there are
>> > other PWMs on the JH7110. You just removed -ptc from the name of this file..
>> >
>> Hi Emil,
>>
>> The PTC, short for PWM/TIMER/CONUTER, comes from OpenCore's ip, but only PWM
>> mode is used in the JH7110. So the register still has the word "PTC".
>> s the best way to change all the prefix to STARFIVE?
>
> I see. Yeah, since you're only using the P from PTC the PTC name doesn't make a
> lot of sense anymore. I'd just call this whole driver
> STARFIVE_PWM_/starfive_pwm_ consistently.
>
I see, I'll update it in next version.
>>
>> Best regards,
>> William
>> >> new file mode 100644
>> >> index 000000000000..d390349fc95d
>> >> --- /dev/null
>> >> +++ b/drivers/pwm/pwm-starfive.c
>> >> @@ -0,0 +1,190 @@
>> >> +// SPDX-License-Identifier: GPL-2.0
>> >> +/*
>> >> + * PWM driver for the StarFive JH71x0 SoC
>> >> + *
>> >> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
>> >> + */
>> >> +
>> >> +#include <linux/clk.h>
>> >> +#include <linux/io.h>
>> >> +#include <linux/module.h>
>> >> +#include <linux/platform_device.h>
>> >> +#include <linux/pwm.h>
>> >> +#include <linux/reset.h>
>> >> +#include <linux/slab.h>
>> >> +
>> >> +/* Access PTC register (CNTR, HRC, LRC and CTRL) */
>> >> +#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + (((N) > 3) ? \
>> >> + (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
>> >> +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
>> >> +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
>> >> +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
>> >> +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
>> >
>> > ..but these defines
>> >
>> >> +
>> >> +/* PTC_RPTC_CTRL register bits*/
>> >> +#define PTC_EN BIT(0)
>> >> +#define PTC_ECLK BIT(1)
>> >> +#define PTC_NEC BIT(2)
>> >> +#define PTC_OE BIT(3)
>> >> +#define PTC_SIGNLE BIT(4)
>> >> +#define PTC_INTE BIT(5)
>> >> +#define PTC_INT BIT(6)
>> >> +#define PTC_CNTRRST BIT(7)
>> >> +#define PTC_CAPTE BIT(8)
>> >
>> > ..and these defines are still prefixed with *PTC where I'd expect something like
>> > STARFIVE_PWM_, and below structs and function names are also still
>> > using starfive_pwm_ptc_
>> > where I'd expect starfive_pwm_. Please be consistant in your naming.
>> >
>> >> +struct starfive_pwm_ptc_device {
>> >> + struct pwm_chip chip;
>> >> + struct clk *clk;
>> >> + struct reset_control *rst;
>> >> + void __iomem *regs;
>> >> + u32 clk_rate; /* PWM APB clock frequency */
>> >> +};
>> >> +
>> >> +static inline struct starfive_pwm_ptc_device *
>> >> +chip_to_starfive_ptc(struct pwm_chip *chip)
>> >> +
>> >> +{
>> >> + return container_of(chip, struct starfive_pwm_ptc_device, chip);
>> >> +}
>> >> +
>> >> +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
>> >> + struct pwm_device *dev,
>> >> + struct pwm_state *state)
>> >> +{
>> >> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
>> >> + u32 period_data, duty_data, ctrl_data;
>> >> +
>> >> + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
>> >> + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
>> >> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> >> +
>> >> + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
>> >> + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
>> >> + state->polarity = PWM_POLARITY_INVERSED;
>> >> + state->enabled = (ctrl_data & PTC_EN) ? true : false;
>> >> +
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
>> >> + struct pwm_device *dev,
>> >> + const struct pwm_state *state)
>> >> +{
>> >> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
>> >> + u32 period_data, duty_data, ctrl_data = 0;
>> >> +
>> >> + if (state->polarity != PWM_POLARITY_INVERSED)
>> >> + return -EINVAL;
>> >> +
>> >> + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
>> >> + NSEC_PER_SEC);
>> >> + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
>> >> + NSEC_PER_SEC);
>> >> +
>> >> + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
>> >> + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
>> >> + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
>> >> +
>> >> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> >> + if (state->enabled)
>> >> + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> >> + else
>> >> + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
>> >> +
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static const struct pwm_ops starfive_pwm_ptc_ops = {
>> >> + .get_state = starfive_pwm_ptc_get_state,
>> >> + .apply = starfive_pwm_ptc_apply,
>> >> + .owner = THIS_MODULE,
>> >> +};
>> >> +
>> >> +static int starfive_pwm_ptc_probe(struct platform_device *pdev)
>> >> +{
>> >> + struct device *dev = &pdev->dev;
>> >> + struct starfive_pwm_ptc_device *pwm;
>> >> + struct pwm_chip *chip;
>> >> + int ret;
>> >> +
>> >> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
>> >> + if (!pwm)
>> >> + return -ENOMEM;
>> >> +
>> >> + chip = &pwm->chip;
>> >> + chip->dev = dev;
>> >> + chip->ops = &starfive_pwm_ptc_ops;
>> >> + chip->npwm = 8;
>> >> + chip->of_pwm_n_cells = 3;
>> >> +
>> >> + pwm->regs = devm_platform_ioremap_resource(pdev, 0);
>> >> + if (IS_ERR(pwm->regs))
>> >> + return dev_err_probe(dev, PTR_ERR(pwm->regs),
>> >> + "Unable to map IO resources\n");
>> >> +
>> >> + pwm->clk = devm_clk_get_enabled(dev, NULL);
>> >> + if (IS_ERR(pwm->clk))
>> >> + return dev_err_probe(dev, PTR_ERR(pwm->clk),
>> >> + "Unable to get pwm's clock\n");
>> >> +
>> >> + pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
>> >> + if (IS_ERR(pwm->rst))
>> >> + return dev_err_probe(dev, PTR_ERR(pwm->rst),
>> >> + "Unable to get pwm's reset\n");
>> >> +
>> >> + ret = reset_control_deassert(pwm->rst);
>> >> + if (ret) {
>> >> + dev_err(dev, "Failed to enable clock for pwm: %d\n", ret);
>> >> + return ret;
>> >> + }
>> >> +
>> >> + pwm->clk_rate = clk_get_rate(pwm->clk);
>> >> + if (pwm->clk_rate <= 0) {
>> >> + dev_warn(dev, "Failed to get APB clock rate\n");
>> >> + return -EINVAL;
>> >> + }
>> >> +
>> >> + ret = devm_pwmchip_add(dev, chip);
>> >> + if (ret < 0) {
>> >> + dev_err(dev, "Cannot register PTC: %d\n", ret);
>> >> + clk_disable_unprepare(pwm->clk);
>> >> + reset_control_assert(pwm->rst);
>> >> + return ret;
>> >> + }
>> >> +
>> >> + platform_set_drvdata(pdev, pwm);
>> >> +
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static int starfive_pwm_ptc_remove(struct platform_device *dev)
>> >> +{
>> >> + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
>> >> +
>> >> + reset_control_assert(pwm->rst);
>> >> + clk_disable_unprepare(pwm->clk);
>> >> +
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static const struct of_device_id starfive_pwm_ptc_of_match[] = {
>> >> + { .compatible = "starfive,jh7100-pwm" },
>> >> + { .compatible = "starfive,jh7110-pwm" },
>> >> + { /* sentinel */ }
>> >> +};
>> >> +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
>> >> +
>> >> +static struct platform_driver starfive_pwm_ptc_driver = {
>> >> + .probe = starfive_pwm_ptc_probe,
>> >> + .remove = starfive_pwm_ptc_remove,
>> >> + .driver = {
>> >> + .name = "pwm-starfive-ptc",
>> >
>> > Here
>> >
>> >> + .of_match_table = starfive_pwm_ptc_of_match,
>> >> + },
>> >> +};
>> >> +module_platform_driver(starfive_pwm_ptc_driver);
>> >> +
>> >> +MODULE_AUTHOR("Jieqin Chen");
>> >> +MODULE_AUTHOR("Hal Feng <[email protected]>");
>> >> +MODULE_DESCRIPTION("StarFive PWM PTC driver");
>> >
>> > ..and here you're also still calling the driver PTC without explaining why.
>> >
>> >> +MODULE_LICENSE("GPL");
>> >> --
>> >> 2.34.1
>> >>
Hello,
On Mon, Sep 25, 2023 at 10:31:49AM +0000, Emil Renner Berthing wrote:
> William Qiu wrote:
> > The PTC, short for PWM/TIMER/CONUTER, comes from OpenCore's ip, but only PWM
> > mode is used in the JH7110. So the register still has the word "PTC".
> > s the best way to change all the prefix to STARFIVE?
>
> I see. Yeah, since you're only using the P from PTC the PTC name doesn't make a
> lot of sense anymore. I'd just call this whole driver
> STARFIVE_PWM_/starfive_pwm_ consistently.
I don't care much how the driver is named iff there is only a single
type of hardware unit on this platform that can be used as a PWM.
However if the hardware manual calls this unit PTC I'd at least mention
that in a comment at the top of the driver.
Thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
William Qiu wrote:
>
>
> On 2023/9/23 20:08, Emil Renner Berthing wrote:
> > William Qiu wrote:
> >> Add Pulse Width Modulation driver support for StarFive
> >> JH7100 and JH7110 SoC.
> >>
> >> Co-developed-by: Hal Feng <[email protected]>
> >> Signed-off-by: Hal Feng <[email protected]>
> >> Signed-off-by: William Qiu <[email protected]>
> >> ---
> >> MAINTAINERS | 7 ++
> >> drivers/pwm/Kconfig | 9 ++
> >> drivers/pwm/Makefile | 1 +
> >> drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++
> >> 4 files changed, 207 insertions(+)
> >> create mode 100644 drivers/pwm/pwm-starfive.c
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index bf0f54c24f81..bc2155bd2712 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
> >> F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
> >> F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
> >>
> >> +STARFIVE JH71X0 PWM DRIVERS
> >> +M: William Qiu <[email protected]>
> >> +M: Hal Feng <[email protected]>
> >> +S: Supported
> >> +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
> >> +F: drivers/pwm/pwm-starfive-ptc.c
> >> +
> >> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
> >> M: Emil Renner Berthing <[email protected]>
> >> M: Hal Feng <[email protected]>
> >> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> >> index 8ebcddf91f7b..e2ee0169f6e4 100644
> >> --- a/drivers/pwm/Kconfig
> >> +++ b/drivers/pwm/Kconfig
> >> @@ -569,6 +569,15 @@ config PWM_SPRD
> >> To compile this driver as a module, choose M here: the module
> >> will be called pwm-sprd.
> >>
> >> +config PWM_STARFIVE
> >> + tristate "StarFive PWM support"
> >> + depends on ARCH_STARFIVE || COMPILE_TEST
> >> + help
> >> + Generic PWM framework driver for StarFive SoCs.
> >> +
> >> + To compile this driver as a module, choose M here: the module
> >> + will be called pwm-starfive.
> >> +
> >> config PWM_STI
> >> tristate "STiH4xx PWM support"
> >> depends on ARCH_STI || COMPILE_TEST
> >> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> >> index c822389c2a24..93b954376873 100644
> >> --- a/drivers/pwm/Makefile
> >> +++ b/drivers/pwm/Makefile
> >> @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
> >> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
> >> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
> >> obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
> >> +obj-$(CONFIG_PWM_STARFIVE) += pwm-starfive.o
> >> obj-$(CONFIG_PWM_STI) += pwm-sti.o
> >> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> >> obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
> >> diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c
> >
> > Hi William,
> >
> > You never answered my questions about what PTC is short for and if there are
> > other PWMs on the JH7110. You just removed -ptc from the name of this file..
> >
> Hi Emil,
>
> The PTC, short for PWM/TIMER/CONUTER, comes from OpenCore's ip, but only PWM
> mode is used in the JH7110. So the register still has the word "PTC".
> s the best way to change all the prefix to STARFIVE?
I see. Yeah, since you're only using the P from PTC the PTC name doesn't make a
lot of sense anymore. I'd just call this whole driver
STARFIVE_PWM_/starfive_pwm_ consistently.
>
> Best regards,
> William
> >> new file mode 100644
> >> index 000000000000..d390349fc95d
> >> --- /dev/null
> >> +++ b/drivers/pwm/pwm-starfive.c
> >> @@ -0,0 +1,190 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * PWM driver for the StarFive JH71x0 SoC
> >> + *
> >> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
> >> + */
> >> +
> >> +#include <linux/clk.h>
> >> +#include <linux/io.h>
> >> +#include <linux/module.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/pwm.h>
> >> +#include <linux/reset.h>
> >> +#include <linux/slab.h>
> >> +
> >> +/* Access PTC register (CNTR, HRC, LRC and CTRL) */
> >> +#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + (((N) > 3) ? \
> >> + (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
> >> +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N))
> >> +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
> >> +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
> >> +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
> >
> > ..but these defines
> >
> >> +
> >> +/* PTC_RPTC_CTRL register bits*/
> >> +#define PTC_EN BIT(0)
> >> +#define PTC_ECLK BIT(1)
> >> +#define PTC_NEC BIT(2)
> >> +#define PTC_OE BIT(3)
> >> +#define PTC_SIGNLE BIT(4)
> >> +#define PTC_INTE BIT(5)
> >> +#define PTC_INT BIT(6)
> >> +#define PTC_CNTRRST BIT(7)
> >> +#define PTC_CAPTE BIT(8)
> >
> > ..and these defines are still prefixed with *PTC where I'd expect something like
> > STARFIVE_PWM_, and below structs and function names are also still
> > using starfive_pwm_ptc_
> > where I'd expect starfive_pwm_. Please be consistant in your naming.
> >
> >> +struct starfive_pwm_ptc_device {
> >> + struct pwm_chip chip;
> >> + struct clk *clk;
> >> + struct reset_control *rst;
> >> + void __iomem *regs;
> >> + u32 clk_rate; /* PWM APB clock frequency */
> >> +};
> >> +
> >> +static inline struct starfive_pwm_ptc_device *
> >> +chip_to_starfive_ptc(struct pwm_chip *chip)
> >> +
> >> +{
> >> + return container_of(chip, struct starfive_pwm_ptc_device, chip);
> >> +}
> >> +
> >> +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip,
> >> + struct pwm_device *dev,
> >> + struct pwm_state *state)
> >> +{
> >> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
> >> + u32 period_data, duty_data, ctrl_data;
> >> +
> >> + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
> >> + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
> >> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> >> +
> >> + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate);
> >> + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate);
> >> + state->polarity = PWM_POLARITY_INVERSED;
> >> + state->enabled = (ctrl_data & PTC_EN) ? true : false;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int starfive_pwm_ptc_apply(struct pwm_chip *chip,
> >> + struct pwm_device *dev,
> >> + const struct pwm_state *state)
> >> +{
> >> + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip);
> >> + u32 period_data, duty_data, ctrl_data = 0;
> >> +
> >> + if (state->polarity != PWM_POLARITY_INVERSED)
> >> + return -EINVAL;
> >> +
> >> + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate,
> >> + NSEC_PER_SEC);
> >> + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate,
> >> + NSEC_PER_SEC);
> >> +
> >> + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
> >> + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
> >> + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm));
> >> +
> >> + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> >> + if (state->enabled)
> >> + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> >> + else
> >> + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm));
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static const struct pwm_ops starfive_pwm_ptc_ops = {
> >> + .get_state = starfive_pwm_ptc_get_state,
> >> + .apply = starfive_pwm_ptc_apply,
> >> + .owner = THIS_MODULE,
> >> +};
> >> +
> >> +static int starfive_pwm_ptc_probe(struct platform_device *pdev)
> >> +{
> >> + struct device *dev = &pdev->dev;
> >> + struct starfive_pwm_ptc_device *pwm;
> >> + struct pwm_chip *chip;
> >> + int ret;
> >> +
> >> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
> >> + if (!pwm)
> >> + return -ENOMEM;
> >> +
> >> + chip = &pwm->chip;
> >> + chip->dev = dev;
> >> + chip->ops = &starfive_pwm_ptc_ops;
> >> + chip->npwm = 8;
> >> + chip->of_pwm_n_cells = 3;
> >> +
> >> + pwm->regs = devm_platform_ioremap_resource(pdev, 0);
> >> + if (IS_ERR(pwm->regs))
> >> + return dev_err_probe(dev, PTR_ERR(pwm->regs),
> >> + "Unable to map IO resources\n");
> >> +
> >> + pwm->clk = devm_clk_get_enabled(dev, NULL);
> >> + if (IS_ERR(pwm->clk))
> >> + return dev_err_probe(dev, PTR_ERR(pwm->clk),
> >> + "Unable to get pwm's clock\n");
> >> +
> >> + pwm->rst = devm_reset_control_get_exclusive(dev, NULL);
> >> + if (IS_ERR(pwm->rst))
> >> + return dev_err_probe(dev, PTR_ERR(pwm->rst),
> >> + "Unable to get pwm's reset\n");
> >> +
> >> + ret = reset_control_deassert(pwm->rst);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to enable clock for pwm: %d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + pwm->clk_rate = clk_get_rate(pwm->clk);
> >> + if (pwm->clk_rate <= 0) {
> >> + dev_warn(dev, "Failed to get APB clock rate\n");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + ret = devm_pwmchip_add(dev, chip);
> >> + if (ret < 0) {
> >> + dev_err(dev, "Cannot register PTC: %d\n", ret);
> >> + clk_disable_unprepare(pwm->clk);
> >> + reset_control_assert(pwm->rst);
> >> + return ret;
> >> + }
> >> +
> >> + platform_set_drvdata(pdev, pwm);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int starfive_pwm_ptc_remove(struct platform_device *dev)
> >> +{
> >> + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
> >> +
> >> + reset_control_assert(pwm->rst);
> >> + clk_disable_unprepare(pwm->clk);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static const struct of_device_id starfive_pwm_ptc_of_match[] = {
> >> + { .compatible = "starfive,jh7100-pwm" },
> >> + { .compatible = "starfive,jh7110-pwm" },
> >> + { /* sentinel */ }
> >> +};
> >> +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match);
> >> +
> >> +static struct platform_driver starfive_pwm_ptc_driver = {
> >> + .probe = starfive_pwm_ptc_probe,
> >> + .remove = starfive_pwm_ptc_remove,
> >> + .driver = {
> >> + .name = "pwm-starfive-ptc",
> >
> > Here
> >
> >> + .of_match_table = starfive_pwm_ptc_of_match,
> >> + },
> >> +};
> >> +module_platform_driver(starfive_pwm_ptc_driver);
> >> +
> >> +MODULE_AUTHOR("Jieqin Chen");
> >> +MODULE_AUTHOR("Hal Feng <[email protected]>");
> >> +MODULE_DESCRIPTION("StarFive PWM PTC driver");
> >
> > ..and here you're also still calling the driver PTC without explaining why.
> >
> >> +MODULE_LICENSE("GPL");
> >> --
> >> 2.34.1
> >>
On Mon, Sep 25, 2023 at 06:27:16PM +0800, William Qiu wrote:
>
>
> On 2023/9/23 20:08, Emil Renner Berthing wrote:
> > William Qiu wrote:
> >> Add Pulse Width Modulation driver support for StarFive
> >> JH7100 and JH7110 SoC.
> >>
> >> Co-developed-by: Hal Feng <[email protected]>
> >> Signed-off-by: Hal Feng <[email protected]>
> >> Signed-off-by: William Qiu <[email protected]>
> >> ---
> >> MAINTAINERS | 7 ++
> >> drivers/pwm/Kconfig | 9 ++
> >> drivers/pwm/Makefile | 1 +
> >> drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++
> >> 4 files changed, 207 insertions(+)
> >> create mode 100644 drivers/pwm/pwm-starfive.c
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index bf0f54c24f81..bc2155bd2712 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
> >> F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
> >> F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
> >>
> >> +STARFIVE JH71X0 PWM DRIVERS
> >> +M: William Qiu <[email protected]>
> >> +M: Hal Feng <[email protected]>
> >> +S: Supported
> >> +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
> >> +F: drivers/pwm/pwm-starfive-ptc.c
> >> +
> >> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
> >> M: Emil Renner Berthing <[email protected]>
> >> M: Hal Feng <[email protected]>
> >> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> >> index 8ebcddf91f7b..e2ee0169f6e4 100644
> >> --- a/drivers/pwm/Kconfig
> >> +++ b/drivers/pwm/Kconfig
> >> @@ -569,6 +569,15 @@ config PWM_SPRD
> >> To compile this driver as a module, choose M here: the module
> >> will be called pwm-sprd.
> >>
> >> +config PWM_STARFIVE
> >> + tristate "StarFive PWM support"
> >> + depends on ARCH_STARFIVE || COMPILE_TEST
> >> + help
> >> + Generic PWM framework driver for StarFive SoCs.
> >> +
> >> + To compile this driver as a module, choose M here: the module
> >> + will be called pwm-starfive.
> >> +
> >> config PWM_STI
> >> tristate "STiH4xx PWM support"
> >> depends on ARCH_STI || COMPILE_TEST
> >> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> >> index c822389c2a24..93b954376873 100644
> >> --- a/drivers/pwm/Makefile
> >> +++ b/drivers/pwm/Makefile
> >> @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
> >> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
> >> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
> >> obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
> >> +obj-$(CONFIG_PWM_STARFIVE) += pwm-starfive.o
> >> obj-$(CONFIG_PWM_STI) += pwm-sti.o
> >> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> >> obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
> >> diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c
> >
> > Hi William,
> >
> > You never answered my questions about what PTC is short for and if there are
> > other PWMs on the JH7110. You just removed -ptc from the name of this file..
> >
> Hi Emil,
>
> The PTC, short for PWM/TIMER/CONUTER, comes from OpenCore's ip, but only PWM
> mode is used in the JH7110. So the register still has the word "PTC".
> s the best way to change all the prefix to STARFIVE?
This is the first time I see mentioned that this is based on an Open-
Cores IP. It's definitely something you want to note somewhere so that
others can reuse this driver if they've incorporated the same IP into
their device.
Given the above it might be better to name this something different
entirely. The original OpenCores PTC IP seems to be single-instance,
but that's about the only difference here (i.e. the OpenCores IP lists
one clock and one reset, which this driver supports).
So it'd be easy to turn this into a generic OpenCores driver and then
use the starfive compatible string(s) to parameterize (number of
instances, register stride, etc.).
Thierry