The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the
only significant differences being support for a wider range of word
sizes and the addition of 32-bit transmit and receive FIFOs.
Signed-off-by: Ben Wolsieffer <[email protected]>
---
Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index ae0f082bd377..5754d603f34f 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -23,6 +23,7 @@ properties:
compatible:
enum:
- st,stm32f4-spi
+ - st,stm32f7-spi
- st,stm32h7-spi
reg:
--
2.42.0
On Thu, Nov 02, 2023 at 03:37:20PM -0400, Ben Wolsieffer wrote:
> The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the
> only significant differences being support for a wider range of word
> sizes and the addition of 32-bit transmit and receive FIFOs.
A wider range of supported word sizes and some additional buffers,
implies that the F4 could be used as a fallback compatible. Does the
register map change incompatibly in the process of widening the FIFOs or
something like that?
Cheers,
Conor.
>
> Signed-off-by: Ben Wolsieffer <[email protected]>
> ---
> Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
> index ae0f082bd377..5754d603f34f 100644
> --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
> @@ -23,6 +23,7 @@ properties:
> compatible:
> enum:
> - st,stm32f4-spi
> + - st,stm32f7-spi
> - st,stm32h7-spi
>
> reg:
> --
> 2.42.0
>
Hi Conor,
On Fri, Nov 03, 2023 at 12:50:53PM +0000, Conor Dooley wrote:
> On Thu, Nov 02, 2023 at 03:37:20PM -0400, Ben Wolsieffer wrote:
> A wider range of supported word sizes and some additional buffers,
> implies that the F4 could be used as a fallback compatible. Does the
> register map change incompatibly in the process of widening the FIFOs or
> something like that?
Yes, the F4 has a single bit to select 8 or 16 bit word size, while the
F7 uses four bits to select an arbitrary word size from 4 to 16 bits.
This series supports the packing mode, to allow sending two <=8 bit
words with a single write to the FIFO, but even if we didn't want to
support this feature, the F7 would require setting the FRXTH bit (not
present in the F4) when using <=8 bit word sizes.
>
> Cheers,
> Conor.
On Fri, Nov 03, 2023 at 09:29:12AM -0400, Ben Wolsieffer wrote:
> Hi Conor,
>
> On Fri, Nov 03, 2023 at 12:50:53PM +0000, Conor Dooley wrote:
> > On Thu, Nov 02, 2023 at 03:37:20PM -0400, Ben Wolsieffer wrote:
> > A wider range of supported word sizes and some additional buffers,
> > implies that the F4 could be used as a fallback compatible. Does the
> > register map change incompatibly in the process of widening the FIFOs or
> > something like that?
>
> Yes, the F4 has a single bit to select 8 or 16 bit word size, while the
> F7 uses four bits to select an arbitrary word size from 4 to 16 bits.
> This series supports the packing mode, to allow sending two <=8 bit
> words with a single write to the FIFO, but even if we didn't want to
> support this feature, the F7 would require setting the FRXTH bit (not
> present in the F4) when using <=8 bit word sizes.
Oke.
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.