2023-11-03 20:19:12

by Jim Harris

Subject: [PATCH] cxl/region: fix x9 interleave typo

CXL supports x3, x6 and x12 - not x9.

Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
Signed-off-by: Jim Harris <[email protected]>
---
drivers/cxl/core/region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 6d63b8798c29..d295b3488e4a 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
return rc;

/*
- * Even for x3, x9, and x12 interleaves the region interleave must be a
+ * Even for x3, x6, and x12 interleaves the region interleave must be a
* power of 2 multiple of the host bridge interleave.
*/
if (!is_power_of_2(val / cxld->interleave_ways) ||

2023-11-03 20:28:53

by Dave Jiang

Subject: Re: [PATCH] cxl/region: fix x9 interleave typo

On 11/3/23 13:18, Jim Harris wrote:
> CXL supports x3, x6 and x12 - not x9.
>
> Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
> Signed-off-by: Jim Harris <[email protected]>

Reviewed-by: Dave Jiang <[email protected]>

Given it's a fix to a comment, the fixes tag is probably not necessary since it's not a code bug to backport to stable.

> ---
> drivers/cxl/core/region.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6d63b8798c29..d295b3488e4a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
> return rc;
>
> /*
> - * Even for x3, x9, and x12 interleaves the region interleave must be a
> + * Even for x3, x6, and x12 interleaves the region interleave must be a
> * power of 2 multiple of the host bridge interleave.
> */
> if (!is_power_of_2(val / cxld->interleave_ways) ||
>

2023-11-06 18:28:19

by fan

Subject: Re: [PATCH] cxl/region: fix x9 interleave typo

On Fri, Nov 03, 2023 at 08:18:34PM +0000, Jim Harris wrote:
> CXL supports x3, x6 and x12 - not x9.
>
> Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
> Signed-off-by: Jim Harris <[email protected]>
> ---

Reviewed-by: Fan Ni <[email protected]>

> drivers/cxl/core/region.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6d63b8798c29..d295b3488e4a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
> return rc;
>
> /*
> - * Even for x3, x9, and x12 interleaves the region interleave must be a
> + * Even for x3, x6, and x12 interleaves the region interleave must be a
> * power of 2 multiple of the host bridge interleave.
> */
> if (!is_power_of_2(val / cxld->interleave_ways) ||
>