From: Bjorn Helgaas <[email protected]>
Fix typos in some arch/ directories, mostly from "codespell arch/". No
code changes, only comment changes.
Bjorn Helgaas (8):
alpha: Fix typos
ARC: Fix typos
arm64: Fix typos
arm64: dts: Fix typos
KVM: arm64: Fix typos
MIPS: Fix typos
powerpc: Fix typos
sparc: Fix typos
arch/alpha/boot/bootpz.c | 4 ++--
arch/alpha/include/asm/core_marvel.h | 2 +-
arch/alpha/include/asm/fpu.h | 2 +-
arch/alpha/include/asm/sfp-machine.h | 2 +-
arch/alpha/include/asm/thread_info.h | 2 +-
arch/alpha/include/asm/wrperfmon.h | 2 +-
arch/alpha/include/uapi/asm/mman.h | 2 +-
arch/alpha/kernel/err_impl.h | 2 +-
arch/alpha/kernel/irq_i8259.c | 2 +-
arch/alpha/kernel/osf_sys.c | 2 +-
arch/alpha/kernel/pci_iommu.c | 4 ++--
arch/alpha/kernel/sys_eiger.c | 4 ++--
arch/alpha/kernel/sys_marvel.c | 2 +-
arch/alpha/kernel/sys_miata.c | 2 +-
arch/alpha/kernel/sys_takara.c | 2 +-
arch/alpha/lib/ev6-memcpy.S | 2 +-
arch/alpha/lib/ev6-stxcpy.S | 2 +-
arch/alpha/lib/ev67-strrchr.S | 2 +-
arch/alpha/lib/strrchr.S | 2 +-
arch/alpha/lib/stxcpy.S | 2 +-
arch/arc/boot/Makefile | 4 ++--
arch/arc/boot/dts/axc003.dtsi | 4 ++--
arch/arc/boot/dts/vdk_axs10x_mb.dtsi | 2 +-
arch/arc/include/asm/dsp.h | 2 +-
arch/arc/include/asm/entry-compact.h | 10 +++++-----
arch/arc/include/asm/entry.h | 4 ++--
arch/arc/include/asm/irq.h | 2 +-
arch/arc/include/asm/irqflags-compact.h | 2 +-
arch/arc/include/asm/mmu_context.h | 2 +-
arch/arc/include/asm/pgtable-bits-arcv2.h | 2 +-
arch/arc/include/asm/shmparam.h | 2 +-
arch/arc/include/asm/smp.h | 4 ++--
arch/arc/include/asm/thread_info.h | 2 +-
arch/arc/include/uapi/asm/swab.h | 2 +-
arch/arc/kernel/entry-arcv2.S | 8 ++++----
arch/arc/kernel/entry.S | 4 ++--
arch/arc/kernel/head.S | 2 +-
arch/arc/kernel/intc-arcv2.c | 2 +-
arch/arc/kernel/perf_event.c | 2 +-
arch/arc/kernel/setup.c | 2 +-
arch/arc/kernel/signal.c | 2 +-
arch/arc/kernel/traps.c | 2 +-
arch/arc/kernel/vmlinux.lds.S | 4 ++--
arch/arc/mm/tlbex.S | 8 ++++----
arch/arm64/Kconfig | 2 +-
.../boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 2 +-
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 2 +-
arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +-
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
.../boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sa8155p.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 2 +-
.../arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 2 +-
arch/arm64/boot/dts/renesas/draak.dtsi | 2 +-
arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts | 2 +-
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +-
arch/arm64/include/asm/assembler.h | 4 ++--
arch/arm64/include/asm/cpufeature.h | 4 ++--
arch/arm64/include/asm/kvm_hyp.h | 2 +-
arch/arm64/include/asm/pgtable.h | 2 +-
arch/arm64/include/asm/suspend.h | 2 +-
arch/arm64/include/asm/traps.h | 4 ++--
arch/arm64/kernel/acpi.c | 2 +-
arch/arm64/kernel/cpufeature.c | 6 +++---
arch/arm64/kernel/entry-common.c | 2 +-
arch/arm64/kernel/entry-ftrace.S | 2 +-
arch/arm64/kernel/entry.S | 2 +-
arch/arm64/kernel/ftrace.c | 2 +-
arch/arm64/kernel/machine_kexec.c | 2 +-
arch/arm64/kernel/probes/uprobes.c | 2 +-
arch/arm64/kernel/sdei.c | 2 +-
arch/arm64/kernel/smp.c | 2 +-
arch/arm64/kernel/traps.c | 2 +-
arch/arm64/kvm/arch_timer.c | 2 +-
arch/arm64/kvm/fpsimd.c | 2 +-
arch/arm64/kvm/hyp/nvhe/host.S | 2 +-
arch/arm64/kvm/hyp/nvhe/mm.c | 4 ++--
arch/arm64/kvm/inject_fault.c | 2 +-
arch/arm64/kvm/vgic/vgic-init.c | 2 +-
arch/arm64/kvm/vgic/vgic-its.c | 4 ++--
arch/mips/bcm47xx/buttons.c | 6 +++---
arch/mips/bcm63xx/clk.c | 4 ++--
arch/mips/boot/compressed/dbg.c | 2 +-
arch/mips/boot/elf2ecoff.c | 2 +-
arch/mips/cavium-octeon/csrc-octeon.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-boot-vector.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c | 4 ++--
arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-pko.c | 2 +-
arch/mips/cavium-octeon/octeon-platform.c | 2 +-
arch/mips/fw/arc/promlib.c | 6 +++---
arch/mips/include/asm/debug.h | 2 +-
arch/mips/include/asm/io.h | 4 ++--
arch/mips/include/asm/mach-au1x00/au1000_dma.h | 2 +-
arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 2 +-
.../mips/include/asm/mach-lantiq/falcon/lantiq_soc.h | 2 +-
.../include/asm/mach-loongson64/loongson_hwmon.h | 2 +-
.../mips/include/asm/mach-loongson64/loongson_regs.h | 2 +-
arch/mips/include/asm/mach-malta/spaces.h | 4 ++--
arch/mips/include/asm/mips-boards/bonito64.h | 2 +-
arch/mips/include/asm/mips-cpc.h | 2 +-
arch/mips/include/asm/mipsregs.h | 4 ++--
arch/mips/include/asm/octeon/cvmx-bootinfo.h | 2 +-
arch/mips/include/asm/octeon/cvmx-cmd-queue.h | 6 +++---
arch/mips/include/asm/octeon/cvmx-pko.h | 2 +-
arch/mips/include/asm/octeon/cvmx-pow.h | 4 ++--
arch/mips/include/asm/octeon/octeon-model.h | 4 ++--
arch/mips/include/asm/page.h | 2 +-
arch/mips/include/asm/pci.h | 2 +-
arch/mips/include/asm/pgtable-bits.h | 2 +-
arch/mips/include/asm/sgi/mc.h | 2 +-
arch/mips/include/asm/sn/klconfig.h | 2 +-
arch/mips/include/asm/sync.h | 2 +-
arch/mips/include/asm/thread_info.h | 2 +-
arch/mips/include/asm/timex.h | 2 +-
arch/mips/include/asm/vdso/vdso.h | 2 +-
arch/mips/include/uapi/asm/mman.h | 2 +-
arch/mips/include/uapi/asm/msgbuf.h | 2 +-
arch/mips/kernel/cpu-probe.c | 2 +-
arch/mips/kernel/kprobes.c | 2 +-
arch/mips/kernel/relocate.c | 2 +-
arch/mips/kernel/relocate_kernel.S | 2 +-
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/signal.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/kernel/vpe.c | 4 ++--
arch/mips/kvm/emulate.c | 2 +-
arch/mips/loongson2ef/common/platform.c | 2 +-
arch/mips/loongson64/smp.c | 2 +-
arch/mips/mm/c-r4k.c | 2 +-
arch/mips/mm/cex-gen.S | 2 +-
arch/mips/mm/tlb-r3k.c | 2 +-
arch/mips/mm/tlb-r4k.c | 2 +-
arch/mips/mm/tlbex.c | 4 ++--
arch/mips/net/bpf_jit_comp32.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/pci-alchemy.c | 2 +-
arch/mips/pci/pci-ar2315.c | 2 +-
arch/mips/pci/pci-lantiq.c | 2 +-
arch/mips/pci/pci-octeon.c | 2 +-
arch/mips/pci/pci-xtalk-bridge.c | 2 +-
arch/mips/pci/pcie-octeon.c | 2 +-
arch/mips/ralink/mt7621.c | 2 +-
arch/mips/txx9/generic/pci.c | 2 +-
arch/powerpc/boot/Makefile | 4 ++--
arch/powerpc/boot/dts/acadia.dts | 2 +-
arch/powerpc/boot/main.c | 2 +-
arch/powerpc/boot/ps3.c | 2 +-
arch/powerpc/include/asm/io.h | 2 +-
arch/powerpc/include/asm/opal-api.h | 4 ++--
arch/powerpc/include/asm/pmac_feature.h | 2 +-
arch/powerpc/include/asm/uninorth.h | 2 +-
arch/powerpc/include/uapi/asm/bootx.h | 2 +-
arch/powerpc/kernel/eeh_pe.c | 2 +-
arch/powerpc/kernel/fadump.c | 2 +-
arch/powerpc/kernel/misc_64.S | 4 ++--
arch/powerpc/kernel/process.c | 12 ++++++------
arch/powerpc/kernel/ptrace/ptrace-tm.c | 2 +-
arch/powerpc/kernel/smp.c | 2 +-
arch/powerpc/kernel/sysfs.c | 4 ++--
arch/powerpc/kvm/book3s_xive.c | 2 +-
arch/powerpc/mm/cacheflush.c | 2 +-
arch/powerpc/mm/nohash/kaslr_booke.c | 2 +-
arch/powerpc/platforms/512x/mpc512x_shared.c | 2 +-
arch/powerpc/platforms/cell/spufs/sched.c | 2 +-
arch/powerpc/platforms/maple/pci.c | 2 +-
arch/powerpc/platforms/powermac/pic.c | 2 +-
arch/powerpc/platforms/powermac/sleep.S | 2 +-
arch/powerpc/platforms/powernv/pci-sriov.c | 4 ++--
arch/powerpc/platforms/powernv/vas-window.c | 2 +-
arch/powerpc/platforms/pseries/vas.c | 2 +-
arch/powerpc/sysdev/xive/common.c | 4 ++--
arch/powerpc/sysdev/xive/native.c | 2 +-
arch/sparc/include/asm/hypervisor.h | 6 +++---
arch/sparc/include/asm/ldc.h | 2 +-
arch/sparc/include/asm/mmu_context_64.h | 4 ++--
arch/sparc/include/asm/switch_to_64.h | 2 +-
arch/sparc/kernel/irq_64.c | 2 +-
arch/sparc/kernel/kprobes.c | 2 +-
arch/sparc/kernel/ldc.c | 2 +-
arch/sparc/kernel/leon_pci_grpci2.c | 2 +-
arch/sparc/kernel/of_device_64.c | 2 +-
arch/sparc/kernel/pci.c | 2 +-
arch/sparc/kernel/pci_impl.h | 4 ++--
arch/sparc/kernel/pci_schizo.c | 4 ++--
arch/sparc/kernel/perf_event.c | 2 +-
arch/sparc/kernel/prom_irqtrans.c | 2 +-
arch/sparc/kernel/psycho_common.c | 2 +-
arch/sparc/kernel/signal_32.c | 2 +-
arch/sparc/kernel/signal_64.c | 2 +-
arch/sparc/mm/srmmu.c | 2 +-
arch/sparc/mm/tsb.c | 2 +-
arch/sparc/net/bpf_jit_comp_32.c | 6 +++---
199 files changed, 260 insertions(+), 260 deletions(-)
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/alpha". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: Ivan Kokshaysky <[email protected]>
Cc: Matt Turner <[email protected]>
Cc: [email protected]
---
arch/alpha/boot/bootpz.c | 4 ++--
arch/alpha/include/asm/core_marvel.h | 2 +-
arch/alpha/include/asm/fpu.h | 2 +-
arch/alpha/include/asm/sfp-machine.h | 2 +-
arch/alpha/include/asm/thread_info.h | 2 +-
arch/alpha/include/asm/wrperfmon.h | 2 +-
arch/alpha/include/uapi/asm/mman.h | 2 +-
arch/alpha/kernel/err_impl.h | 2 +-
arch/alpha/kernel/irq_i8259.c | 2 +-
arch/alpha/kernel/osf_sys.c | 2 +-
arch/alpha/kernel/pci_iommu.c | 4 ++--
arch/alpha/kernel/sys_eiger.c | 4 ++--
arch/alpha/kernel/sys_marvel.c | 2 +-
arch/alpha/kernel/sys_miata.c | 2 +-
arch/alpha/kernel/sys_takara.c | 2 +-
arch/alpha/lib/ev6-memcpy.S | 2 +-
arch/alpha/lib/ev6-stxcpy.S | 2 +-
arch/alpha/lib/ev67-strrchr.S | 2 +-
arch/alpha/lib/strrchr.S | 2 +-
arch/alpha/lib/stxcpy.S | 2 +-
20 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/alpha/boot/bootpz.c b/arch/alpha/boot/bootpz.c
index c6079308eab3..64680c10db79 100644
--- a/arch/alpha/boot/bootpz.c
+++ b/arch/alpha/boot/bootpz.c
@@ -326,7 +326,7 @@ start_kernel(void)
* 0x20000000, we have to ensure that the physical memory
* pages occupied by that image do NOT overlap the physical
* address range where the kernel wants to be run. This
- * causes real problems when attempting to cdecompress the
+ * causes real problems when attempting to decompress the
* former into the latter... :-(
*
* So, we may have to decompress/move the kernel/INITRD image
@@ -456,7 +456,7 @@ start_kernel(void)
#ifdef DEBUG_LAST_STEPS
srm_printk("Preparing INITRD info...\n");
#endif
- /* Finally, set the INITRD paramenters for the kernel. */
+ /* Finally, set the INITRD parameters for the kernel. */
((long *)(ZERO_PGE+256))[0] = initrd_image_start;
((long *)(ZERO_PGE+256))[1] = INITRD_IMAGE_SIZE;
diff --git a/arch/alpha/include/asm/core_marvel.h b/arch/alpha/include/asm/core_marvel.h
index d99f3a82e0e5..cf02c8f5c056 100644
--- a/arch/alpha/include/asm/core_marvel.h
+++ b/arch/alpha/include/asm/core_marvel.h
@@ -279,7 +279,7 @@ union IO7_IID {
#define IO7_DAC_OFFSET (1UL << 49)
/*
- * This is needed to satisify the IO() macro used in initializing the machvec
+ * This is needed to satisfy the IO() macro used in initializing the machvec
*/
#define MARVEL_IACK_SC \
((unsigned long) \
diff --git a/arch/alpha/include/asm/fpu.h b/arch/alpha/include/asm/fpu.h
index 30b24135dd7a..6c1823c21782 100644
--- a/arch/alpha/include/asm/fpu.h
+++ b/arch/alpha/include/asm/fpu.h
@@ -73,7 +73,7 @@ static inline unsigned long
swcr_update_status(unsigned long swcr, unsigned long fpcr)
{
/* EV6 implements most of the bits in hardware. Collect
- the acrued exception bits from the real fpcr. */
+ the accrued exception bits from the real fpcr. */
if (implver() == IMPLVER_EV6) {
swcr &= ~IEEE_STATUS_MASK;
swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
diff --git a/arch/alpha/include/asm/sfp-machine.h b/arch/alpha/include/asm/sfp-machine.h
index 5fe63afbd474..598e5067c5d0 100644
--- a/arch/alpha/include/asm/sfp-machine.h
+++ b/arch/alpha/include/asm/sfp-machine.h
@@ -49,7 +49,7 @@
#define _FP_KEEPNANFRACP 1
-/* Alpha Architecture Handbook, 4.7.10.4 sais that
+/* Alpha Architecture Handbook, 4.7.10.4 says that
* we should prefer any type of NaN in Fb, then Fa.
*/
#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
diff --git a/arch/alpha/include/asm/thread_info.h b/arch/alpha/include/asm/thread_info.h
index 4a4d00b37986..4f237e560a64 100644
--- a/arch/alpha/include/asm/thread_info.h
+++ b/arch/alpha/include/asm/thread_info.h
@@ -20,7 +20,7 @@ struct thread_info {
unsigned int ieee_state; /* see fpu.h */
unsigned cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
+ int preempt_count; /* 0 => preemptible, <0 => BUG */
unsigned int status; /* thread-synchronous flags */
int bpt_nsaved;
diff --git a/arch/alpha/include/asm/wrperfmon.h b/arch/alpha/include/asm/wrperfmon.h
index c97b82a1f7db..b11f09cb7fe6 100644
--- a/arch/alpha/include/asm/wrperfmon.h
+++ b/arch/alpha/include/asm/wrperfmon.h
@@ -59,7 +59,7 @@
/*
- * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
+ * The Alpha Architecture Handbook, vers. 4 (1998) appears to have a misprint
* in Table E-23 regarding the bits that set the event PCTR 1 counts.
* Hopefully what we have here is correct.
*/
diff --git a/arch/alpha/include/uapi/asm/mman.h b/arch/alpha/include/uapi/asm/mman.h
index 763929e814e9..095eba603593 100644
--- a/arch/alpha/include/uapi/asm/mman.h
+++ b/arch/alpha/include/uapi/asm/mman.h
@@ -61,7 +61,7 @@
#define MADV_HUGEPAGE 14 /* Worth backing with hugepages */
#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */
-#define MADV_DONTDUMP 16 /* Explicity exclude from the core dump,
+#define MADV_DONTDUMP 16 /* Explicitly exclude from core dump,
overrides the coredump filter bits */
#define MADV_DODUMP 17 /* Clear the MADV_NODUMP flag */
diff --git a/arch/alpha/kernel/err_impl.h b/arch/alpha/kernel/err_impl.h
index 737b958a586d..e368f0f62866 100644
--- a/arch/alpha/kernel/err_impl.h
+++ b/arch/alpha/kernel/err_impl.h
@@ -32,7 +32,7 @@ struct el_subpacket_handler {
#define SUBPACKET_HANDLER_INIT(c, h) {NULL, (c), (h)}
/*
- * Manipulate a field from a register given it's name. defines
+ * Manipulate a field from a register given its name. defines
* for the LSB (__S - shift count) and bitmask (__M) are required
*
* EXTRACT(u, f) - extracts the field and places it at bit position 0
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c
index 1dcf0d9038fd..657d776f15f7 100644
--- a/arch/alpha/kernel/irq_i8259.c
+++ b/arch/alpha/kernel/irq_i8259.c
@@ -147,7 +147,7 @@ isa_no_iack_sc_device_interrupt(unsigned long vector)
*/
/*
* The first read of gives you *all* interrupting lines.
- * Therefore, read the mask register and and out those lines
+ * Therefore, read the mask register and AND out those lines
* not enabled. Note that some documentation has 21 and a1
* write only. This is not true.
*/
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 5db88b627439..60273892fabb 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -826,7 +826,7 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer,
/*
* Alpha Architecture Handbook 4.7.7.3:
- * To be fully IEEE compiant, we must track the current IEEE
+ * To be fully IEEE compliant, we must track the current IEEE
* exception state in software, because spurious bits can be
* set in the trap shadow of a software-complete insn.
*/
diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
index c81183935e97..99de7bcaf24b 100644
--- a/arch/alpha/kernel/pci_iommu.c
+++ b/arch/alpha/kernel/pci_iommu.c
@@ -476,7 +476,7 @@ static void alpha_pci_free_coherent(struct device *dev, size_t size,
-1 : Not leader, physically adjacent to previous.
-2 : Not leader, virtually adjacent to previous.
Write dma_length of each leader with the combined lengths of
- the mergable followers. */
+ the mergeable followers. */
#define SG_ENT_VIRT_ADDRESS(SG) (sg_virt((SG)))
#define SG_ENT_PHYS_ADDRESS(SG) __pa(SG_ENT_VIRT_ADDRESS(SG))
@@ -495,7 +495,7 @@ sg_classify(struct device *dev, struct scatterlist *sg, struct scatterlist *end,
leader_length = leader->length;
next_paddr = SG_ENT_PHYS_ADDRESS(leader) + leader_length;
- /* we will not marge sg without device. */
+ /* we will not merge sg without device. */
max_seg_size = dev ? dma_get_max_seg_size(dev) : 0;
for (++sg; sg < end; ++sg) {
unsigned long addr, len;
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c
index aea8a54da4bc..fbe264a30a66 100644
--- a/arch/alpha/kernel/sys_eiger.c
+++ b/arch/alpha/kernel/sys_eiger.c
@@ -98,7 +98,7 @@ eiger_device_interrupt(unsigned long vector)
if (intstatus) {
/*
* This is a PCI interrupt. Check each bit and
- * despatch an interrupt if it's set.
+ * dispatch an interrupt if it's set.
*/
if (intstatus & 8) handle_irq(16+3);
@@ -148,7 +148,7 @@ eiger_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
/* The SRM console has already calculated out the IRQ value's for
option cards. As this works lets just read in the value already
- set and change it to a useable value by Linux.
+ set and change it to a usable value by Linux.
All the IRQ values generated by the console are greater than 90,
so we subtract 80 because it is (90 - allocated ISA IRQ's). */
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 1f99b03effc2..90a94f8816cc 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -258,7 +258,7 @@ init_io7_irqs(struct io7 *io7,
* They really should be sent to the local CPU to avoid having to
* traverse the mesh, but if it's not an SMP kernel, they have to
* go to the boot CPU. Send them all to the boot CPU for now,
- * as each secondary starts, it can redirect it's local device
+ * as each secondary starts, it can redirect its local device
* interrupts.
*/
printk(" Interrupts reported to CPU at PE %u\n", boot_cpuid);
diff --git a/arch/alpha/kernel/sys_miata.c b/arch/alpha/kernel/sys_miata.c
index 33b2798de8fc..3bde9c01a9ab 100644
--- a/arch/alpha/kernel/sys_miata.c
+++ b/arch/alpha/kernel/sys_miata.c
@@ -179,7 +179,7 @@ miata_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
};
const long min_idsel = 3, max_idsel = 20, irqs_per_slot = 5;
- /* the USB function of the 82c693 has it's interrupt connected to
+ /* the USB function of the 82c693 has its interrupt connected to
the 2nd 8259 controller. So we have to check for it first. */
if((slot == 7) && (PCI_FUNC(dev->devfn) == 3)) {
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c
index 9e2adb69bc74..aa65a7fb8fc6 100644
--- a/arch/alpha/kernel/sys_takara.c
+++ b/arch/alpha/kernel/sys_takara.c
@@ -93,7 +93,7 @@ takara_device_interrupt(unsigned long vector)
if (intstatus) {
/*
* This is a PCI interrupt. Check each bit and
- * despatch an interrupt if it's set.
+ * dispatch an interrupt if it's set.
*/
if (intstatus & 8) handle_irq(16+3);
diff --git a/arch/alpha/lib/ev6-memcpy.S b/arch/alpha/lib/ev6-memcpy.S
index 3ef43c26c8af..12b94117f394 100644
--- a/arch/alpha/lib/ev6-memcpy.S
+++ b/arch/alpha/lib/ev6-memcpy.S
@@ -181,7 +181,7 @@ $tail_bytes:
$misaligned:
mov $0, $4 # E : dest temp
and $0, 7, $1 # E : dest alignment mod8
- beq $1, $dest_0mod8 # U : life doesnt totally suck
+ beq $1, $dest_0mod8 # U : life doesn't totally suck
nop
$aligndest:
diff --git a/arch/alpha/lib/ev6-stxcpy.S b/arch/alpha/lib/ev6-stxcpy.S
index 65f5f7310d80..331eef1b90c5 100644
--- a/arch/alpha/lib/ev6-stxcpy.S
+++ b/arch/alpha/lib/ev6-stxcpy.S
@@ -129,7 +129,7 @@ __stxcpy:
ldq_u t1, 0(a1) # L : load first src word
and a0, 7, t0 # E : take care not to load a word ...
addq a1, 8, a1 # E :
- beq t0, stxcpy_aligned # U : ... if we wont need it (stall)
+ beq t0, stxcpy_aligned # U : ... if we won't need it (stall)
ldq_u t0, 0(a0) # L :
br stxcpy_aligned # L0 : Latency=3
diff --git a/arch/alpha/lib/ev67-strrchr.S b/arch/alpha/lib/ev67-strrchr.S
index ae7355f9ec56..b1903395dea3 100644
--- a/arch/alpha/lib/ev67-strrchr.S
+++ b/arch/alpha/lib/ev67-strrchr.S
@@ -76,7 +76,7 @@ $loop:
cmpbge zero, t0, t1 # E : bits set iff byte == zero
cmpbge zero, t2, t3 # E : bits set iff byte == c
- beq t1, $loop # U : if we havnt seen a null, loop
+ beq t1, $loop # U : if we haven't seen a null, loop
nop
/* Mask out character matches after terminator */
diff --git a/arch/alpha/lib/strrchr.S b/arch/alpha/lib/strrchr.S
index dd8e073b6cf2..f12045badb63 100644
--- a/arch/alpha/lib/strrchr.S
+++ b/arch/alpha/lib/strrchr.S
@@ -49,7 +49,7 @@ $loop:
xor t0, a1, t2 # e0 :
cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero
cmpbge zero, t2, t3 # e0 : bits set iff byte == c
- beq t1, $loop # .. e1 : if we havnt seen a null, loop
+ beq t1, $loop # .. e1 : if we haven't seen a null, loop
/* Mask out character matches after terminator */
$eos:
diff --git a/arch/alpha/lib/stxcpy.S b/arch/alpha/lib/stxcpy.S
index 58723b0a36d4..967be2eaeaf0 100644
--- a/arch/alpha/lib/stxcpy.S
+++ b/arch/alpha/lib/stxcpy.S
@@ -109,7 +109,7 @@ __stxcpy:
ldq_u t1, 0(a1) # e0 : load first src word
and a0, 7, t0 # .. e1 : take care not to load a word ...
addq a1, 8, a1 # e0 :
- beq t0, stxcpy_aligned # .. e1 : ... if we wont need it
+ beq t0, stxcpy_aligned # .. e1 : ... if we won't need it
ldq_u t0, 0(a0) # e0 :
br stxcpy_aligned # .. e1 :
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/arc". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: [email protected]
---
arch/arc/boot/Makefile | 4 ++--
arch/arc/boot/dts/axc003.dtsi | 4 ++--
arch/arc/boot/dts/vdk_axs10x_mb.dtsi | 2 +-
arch/arc/include/asm/dsp.h | 2 +-
arch/arc/include/asm/entry-compact.h | 10 +++++-----
arch/arc/include/asm/entry.h | 4 ++--
arch/arc/include/asm/irq.h | 2 +-
arch/arc/include/asm/irqflags-compact.h | 2 +-
arch/arc/include/asm/mmu_context.h | 2 +-
arch/arc/include/asm/pgtable-bits-arcv2.h | 2 +-
arch/arc/include/asm/shmparam.h | 2 +-
arch/arc/include/asm/smp.h | 4 ++--
arch/arc/include/asm/thread_info.h | 2 +-
arch/arc/include/uapi/asm/swab.h | 2 +-
arch/arc/kernel/entry-arcv2.S | 8 ++++----
arch/arc/kernel/entry.S | 4 ++--
arch/arc/kernel/head.S | 2 +-
arch/arc/kernel/intc-arcv2.c | 2 +-
arch/arc/kernel/perf_event.c | 2 +-
arch/arc/kernel/setup.c | 2 +-
arch/arc/kernel/signal.c | 2 +-
arch/arc/kernel/traps.c | 2 +-
arch/arc/kernel/vmlinux.lds.S | 4 ++--
arch/arc/mm/tlbex.S | 8 ++++----
24 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/arch/arc/boot/Makefile b/arch/arc/boot/Makefile
index 5648748c285f..5a8550124b73 100644
--- a/arch/arc/boot/Makefile
+++ b/arch/arc/boot/Makefile
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
-# uImage build relies on mkimage being availble on your host for ARC target
+# uImage build relies on mkimage being available on your host for ARC target
# You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage
-# and make sure it's reacable from your PATH
+# and make sure it's reachable from your PATH
OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index 3434c8131ecd..c0a812674ce9 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -119,9 +119,9 @@ mmc@15000 {
/*
* The DW APB ICTL intc on MB is connected to CPU intc via a
* DT "invisible" DW APB GPIO block, configured to simply pass thru
- * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
+ * interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c)
*
- * So here we mimic a direct connection betwen them, ignoring the
+ * So here we mimic a direct connection between them, ignoring the
* ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
* instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
*
diff --git a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
index 90a412026e64..0e0e2d337bf8 100644
--- a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
@@ -113,7 +113,7 @@ mmc@15000 {
/*
* Embedded Vision subsystem UIO mappings; only relevant for EV VDK
*
- * This node is intentionally put outside of MB above becase
+ * This node is intentionally put outside of MB above because
* it maps areas outside of MB's 0xez-0xfz.
*/
uio_ev: uio@d0000000 {
diff --git a/arch/arc/include/asm/dsp.h b/arch/arc/include/asm/dsp.h
index 202c78e56704..f496dbc4640b 100644
--- a/arch/arc/include/asm/dsp.h
+++ b/arch/arc/include/asm/dsp.h
@@ -12,7 +12,7 @@
/*
* DSP-related saved registers - need to be saved only when you are
* scheduled out.
- * structure fields name must correspond to aux register defenitions for
+ * structure fields name must correspond to aux register definitions for
* automatic offset calculation in DSP_AUX_SAVE_RESTORE macros
*/
struct dsp_callee_regs {
diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h
index a0e760eb35a8..4b8502df31d9 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -7,7 +7,7 @@
* Stack switching code can no longer reliably rely on the fact that
* if we are NOT in user mode, stack is switched to kernel mode.
* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
- * it's prologue including stack switching from user mode
+ * its prologue including stack switching from user mode
*
* Vineetg: Aug 28th 2008: Bug #94984
* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
@@ -58,7 +58,7 @@
* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
* 3. But before it could switch SP from USER to KERNEL stack
* a L2 IRQ "Interrupts" L1
- * Thay way although L2 IRQ happened in Kernel mode, stack is still
+ * That way although L2 IRQ happened in Kernel mode, stack is still
* not switched.
* To handle this, we may need to switch stack even if in kernel mode
* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
@@ -88,7 +88,7 @@
GET_CURR_TASK_ON_CPU r9
- /* With current tsk in r9, get it's kernel mode stack base */
+ /* With current tsk in r9, get its kernel mode stack base */
GET_TSK_STACK_BASE r9, r9
/* save U mode SP @ pt_regs->sp */
@@ -197,7 +197,7 @@
* NOTE:
*
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
- * for memory load operations. If used in that way interrupts are deffered
+ * for memory load operations. If used in that way interrupts are deferred
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro EXCEPTION_EPILOGUE
@@ -265,7 +265,7 @@
* NOTE:
*
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
- * for memory load operations. If used in that way interrupts are deffered
+ * for memory load operations. If used in that way interrupts are deferred
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro INTERRUPT_EPILOGUE LVL
diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h
index 49c2e090cb5c..4bcb64dbcc8f 100644
--- a/arch/arc/include/asm/entry.h
+++ b/arch/arc/include/asm/entry.h
@@ -7,7 +7,7 @@
#ifndef __ASM_ARC_ENTRY_H
#define __ASM_ARC_ENTRY_H
-#include <asm/unistd.h> /* For NR_syscalls defination */
+#include <asm/unistd.h> /* For NR_syscalls definition */
#include <asm/arcregs.h>
#include <asm/ptrace.h>
#include <asm/processor.h> /* For VMALLOC_START */
@@ -158,7 +158,7 @@
.endm
/*-------------------------------------------------------------
- * given a tsk struct, get to the base of it's kernel mode stack
+ * given a tsk struct, get to the base of its kernel mode stack
* tsk->thread_info is really a PAGE, whose bottom hoists stack
* which grows upwards towards thread_info
*------------------------------------------------------------*/
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index c574712ad865..9cd79263acba 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -10,7 +10,7 @@
* ARCv2 can support 240 interrupts in the core interrupts controllers and
* 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
* configurations of boards.
- * This doesnt affect ARCompact, but we change it to same value
+ * This doesn't affect ARCompact, but we change it to same value
*/
#define NR_IRQS 512
diff --git a/arch/arc/include/asm/irqflags-compact.h b/arch/arc/include/asm/irqflags-compact.h
index 0d63e568d64c..936a2f21f315 100644
--- a/arch/arc/include/asm/irqflags-compact.h
+++ b/arch/arc/include/asm/irqflags-compact.h
@@ -46,7 +46,7 @@
* IRQ Control Macros
*
* All of them have "memory" clobber (compiler barrier) which is needed to
- * ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
+ * ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available)
* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
*
* Noted at the time of Abilis Timer List corruption
diff --git a/arch/arc/include/asm/mmu_context.h b/arch/arc/include/asm/mmu_context.h
index dda471f5f05b..9963bb1a5733 100644
--- a/arch/arc/include/asm/mmu_context.h
+++ b/arch/arc/include/asm/mmu_context.h
@@ -165,7 +165,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* for retiring-mm. However destroy_context( ) still needs to do that because
* between mm_release( ) = >deactive_mm( ) and
* mmput => .. => __mmdrop( ) => destroy_context( )
- * there is a good chance that task gets sched-out/in, making it's ASID valid
+ * there is a good chance that task gets sched-out/in, making its ASID valid
* again (this teased me for a whole day).
*/
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h b/arch/arc/include/asm/pgtable-bits-arcv2.h
index f3eea3f30b2e..f8f85c04d7a8 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -66,7 +66,7 @@
* Other rules which cause the divergence from 1:1 mapping
*
* 1. Although ARC700 can do exclusive execute/write protection (meaning R
- * can be tracked independet of X/W unlike some other CPUs), still to
+ * can be tracked independent of X/W unlike some other CPUs), still to
* keep things consistent with other archs:
* -Write implies Read: W => R
* -Execute implies Read: X => R
diff --git a/arch/arc/include/asm/shmparam.h b/arch/arc/include/asm/shmparam.h
index 8b0251464ffd..719112af0f41 100644
--- a/arch/arc/include/asm/shmparam.h
+++ b/arch/arc/include/asm/shmparam.h
@@ -6,7 +6,7 @@
#ifndef __ARC_ASM_SHMPARAM_H
#define __ARC_ASM_SHMPARAM_H
-/* Handle upto 2 cache bins */
+/* Handle up to 2 cache bins */
#define SHMLBA (2 * PAGE_SIZE)
/* Enforce SHMLBA in shmat */
diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
index e0913f52c2cd..990f834909f0 100644
--- a/arch/arc/include/asm/smp.h
+++ b/arch/arc/include/asm/smp.h
@@ -77,7 +77,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
/*
* ARC700 doesn't support atomic Read-Modify-Write ops.
- * Originally Interrupts had to be disabled around code to gaurantee atomicity.
+ * Originally Interrupts had to be disabled around code to guarantee atomicity.
* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
* based on retry-if-irq-in-atomic (with hardware assist).
* However despite these, we provide the IRQ disabling variant
@@ -86,7 +86,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
* support needed.
*
* (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
- * gaurantted by the platform (not something which core handles).
+ * guaranteed by the platform (not something which core handles).
* Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
* disabling for atomicity.
*
diff --git a/arch/arc/include/asm/thread_info.h b/arch/arc/include/asm/thread_info.h
index 4c530cf131f3..12daaf3a61ea 100644
--- a/arch/arc/include/asm/thread_info.h
+++ b/arch/arc/include/asm/thread_info.h
@@ -38,7 +38,7 @@
struct thread_info {
unsigned long flags; /* low level flags */
unsigned long ksp; /* kernel mode stack top in __switch_to */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
+ int preempt_count; /* 0 => preemptible, <0 => BUG */
int cpu; /* current CPU */
unsigned long thr_ptr; /* TLS ptr */
struct task_struct *task; /* main task structure */
diff --git a/arch/arc/include/uapi/asm/swab.h b/arch/arc/include/uapi/asm/swab.h
index 02109cd48ee1..8d1f1ef44ba7 100644
--- a/arch/arc/include/uapi/asm/swab.h
+++ b/arch/arc/include/uapi/asm/swab.h
@@ -62,7 +62,7 @@
* 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem
*
* Joern suggested a better "C" algorithm which is great since
- * (1) It is portable to any architecure
+ * (1) It is portable to any architecture
* (2) At the same time it takes advantage of ARC ISA (rotate intrns)
*/
diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
index 2e49c81c8086..e238b5fd3c8c 100644
--- a/arch/arc/kernel/entry-arcv2.S
+++ b/arch/arc/kernel/entry-arcv2.S
@@ -5,7 +5,7 @@
* Copyright (C) 2013 Synopsys, Inc. (http://www.synopsys.com)
*/
-#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
+#include <linux/linkage.h> /* ARC_{ENTRY,EXIT} */
#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
#include <asm/errno.h>
#include <asm/arcregs.h>
@@ -31,7 +31,7 @@ VECTOR res_service ; Reset Vector
VECTOR mem_service ; Mem exception
VECTOR instr_service ; Instrn Error
VECTOR EV_MachineCheck ; Fatal Machine check
-VECTOR EV_TLBMissI ; Intruction TLB miss
+VECTOR EV_TLBMissI ; Instruction TLB miss
VECTOR EV_TLBMissD ; Data TLB miss
VECTOR EV_TLBProtV ; Protection Violation
VECTOR EV_PrivilegeV ; Privilege Violation
@@ -76,11 +76,11 @@ ENTRY(handle_interrupt)
# query in hard ISR path would return false (since .IE is set) which would
# trips genirq interrupt handling asserts.
#
- # So do a "soft" disable of interrutps here.
+ # So do a "soft" disable of interrupts here.
#
# Note this disable is only for consistent book-keeping as further interrupts
# will be disabled anyways even w/o this. Hardware tracks active interrupts
- # seperately in AUX_IRQ_ACT.active and will not take new interrupts
+ # separately in AUX_IRQ_ACT.active and will not take new interrupts
# unless this one returns (or higher prio becomes pending in 2-prio scheme)
IRQ_DISABLE
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 089f6680518f..3c7e74aba679 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -95,7 +95,7 @@ ENTRY(EV_MachineCheck)
lr r0, [efa]
mov r1, sp
- ; MC excpetions disable MMU
+ ; MC exceptions disable MMU
ARC_MMU_REENABLE r3
lsr r3, r10, 8
@@ -209,7 +209,7 @@ trap_with_param:
; ---------------------------------------------
; syscall TRAP
-; ABI: (r0-r7) upto 8 args, (r8) syscall number
+; ABI: (r0-r7) up to 8 args, (r8) syscall number
; ---------------------------------------------
ENTRY(EV_Trap)
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 9152782444b5..8d541f53fae3 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -165,7 +165,7 @@ ENTRY(first_lines_of_secondary)
; setup stack (fp, sp)
mov fp, 0
- ; set it's stack base to tsk->thread_info bottom
+ ; set its stack base to tsk->thread_info bottom
GET_TSK_STACK_BASE r0, sp
j start_kernel_secondary
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 678898757e47..f324f0e3341a 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -56,7 +56,7 @@ void arc_init_IRQ(void)
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
/*
- * ARCv2 core intc provides multiple interrupt priorities (upto 16).
+ * ARCv2 core intc provides multiple interrupt priorities (up to 16).
* Typical builds though have only two levels (0-high, 1-low)
* Linux by default uses lower prio 1 for most irqs, reserving 0 for
* NMI style interrupts in future (say perf)
diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index adff957962da..6e5a651cd75c 100644
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -38,7 +38,7 @@
* (based on a specific RTL build)
* Below is the static map between perf generic/arc specific event_id and
* h/w condition names.
- * At the time of probe, we loop thru each index and find it's name to
+ * At the time of probe, we loop thru each index and find its name to
* complete the mapping of perf event_id to h/w index as latter is needed
* to program the counter really
*/
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 4dcf8589b708..cbe0b678811e 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -392,7 +392,7 @@ static void arc_chk_core_config(struct cpuinfo_arc *info)
#ifdef CONFIG_ARC_HAS_DCCM
/*
* DCCM can be arbit placed in hardware.
- * Make sure it's placement/sz matches what Linux is built with
+ * Make sure its placement/sz matches what Linux is built with
*/
if ((unsigned int)__arc_dccm_base != info->dccm.base)
panic("Linux built with incorrect DCCM Base address\n");
diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
index 0b3bb529d246..5414d9f5c40c 100644
--- a/arch/arc/kernel/signal.c
+++ b/arch/arc/kernel/signal.c
@@ -9,7 +9,7 @@
* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
* -do_signal() supports TIF_RESTORE_SIGMASK
* -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
- * -sys_rt_sigsuspend() now comes from generic code, so discard arch implemen
+ * -sys_rt_sigsuspend() now comes from generic code, so discard arch implement
* -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
* -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and leaves
* the job to do_signal()
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index 9b9570b79362..a19751e824fb 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -89,7 +89,7 @@ int do_misaligned_access(unsigned long address, struct pt_regs *regs,
/*
* Entry point for miscll errors such as Nested Exceptions
- * -Duplicate TLB entry is handled seperately though
+ * -Duplicate TLB entry is handled separately though
*/
void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
{
diff --git a/arch/arc/kernel/vmlinux.lds.S b/arch/arc/kernel/vmlinux.lds.S
index 549c3f407918..61a1b2b96e1d 100644
--- a/arch/arc/kernel/vmlinux.lds.S
+++ b/arch/arc/kernel/vmlinux.lds.S
@@ -41,8 +41,8 @@ SECTIONS
#endif
/*
- * The reason for having a seperate subsection .init.ramfs is to
- * prevent objump from including it in kernel dumps
+ * The reason for having a separate subsection .init.ramfs is to
+ * prevent objdump from including it in kernel dumps
*
* Reason for having .init.ramfs above .init is to make sure that the
* binary blob is tucked away to one side, reducing the displacement
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index e054780a8fe0..dc65e87a531f 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -5,19 +5,19 @@
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (http://www.synopsys.com)
*
* Vineetg: April 2011 :
- * -MMU v1: moved out legacy code into a seperate file
+ * -MMU v1: moved out legacy code into a separate file
* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
* helps avoid a shift when preparing PD0 from PTE
*
* Vineetg: July 2009
- * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
- * entry, so that it doesn't knock out it's I-TLB entry
+ * -For MMU V2, we need not do heuristics at the time of committing a D-TLB
+ * entry, so that it doesn't knock out its I-TLB entry
* -Some more fine tuning:
* bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
*
* Vineetg: July 2009
* -Practically rewrote the I/D TLB Miss handlers
- * Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
+ * Now 40 and 135 instructions apiece as compared to 131 and 449 resp.
* Hence Leaner by 1.5 K
* Used Conditional arithmetic to replace excessive branching
* Also used short instructions wherever possible
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/arm64". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: [email protected]
---
arch/arm64/Kconfig | 2 +-
arch/arm64/include/asm/assembler.h | 4 ++--
arch/arm64/include/asm/cpufeature.h | 4 ++--
arch/arm64/include/asm/pgtable.h | 2 +-
arch/arm64/include/asm/suspend.h | 2 +-
arch/arm64/include/asm/traps.h | 4 ++--
arch/arm64/kernel/acpi.c | 2 +-
arch/arm64/kernel/cpufeature.c | 6 +++---
arch/arm64/kernel/entry-common.c | 2 +-
arch/arm64/kernel/entry-ftrace.S | 2 +-
arch/arm64/kernel/entry.S | 2 +-
arch/arm64/kernel/ftrace.c | 2 +-
arch/arm64/kernel/machine_kexec.c | 2 +-
arch/arm64/kernel/probes/uprobes.c | 2 +-
arch/arm64/kernel/sdei.c | 2 +-
arch/arm64/kernel/smp.c | 2 +-
arch/arm64/kernel/traps.c | 2 +-
17 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b071a00425d..1954035737cf 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2227,7 +2227,7 @@ config CMDLINE
default ""
help
Provide a set of default command-line options at build time by
- entering them here. As a minimum, you should specify the the
+ entering them here. As a minimum, you should specify the
root device (e.g. root=/dev/nfs).
choice
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 376a980f2bad..0b2e67fa9a11 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -390,7 +390,7 @@ alternative_endif
* [start, end) with dcache line size explicitly provided.
*
* op: operation passed to dc instruction
- * domain: domain used in dsb instruciton
+ * domain: domain used in dsb instruction
* start: starting virtual address of the region
* end: end virtual address of the region
* linesz: dcache line size
@@ -431,7 +431,7 @@ alternative_endif
* [start, end)
*
* op: operation passed to dc instruction
- * domain: domain used in dsb instruciton
+ * domain: domain used in dsb instruction
* start: starting virtual address of the region
* end: end virtual address of the region
* fixup: optional label to branch to on user fault
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index f6d416fe49b0..a0f4010c1e85 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -198,7 +198,7 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
* registers (e.g, SCTLR, TCR etc.) or patching the kernel via
* alternatives. The kernel patching is batched and performed at later
* point. The actions are always initiated only after the capability
- * is finalised. This is usally denoted by "enabling" the capability.
+ * is finalised. This is usually denoted by "enabling" the capability.
* The actions are initiated as follows :
* a) Action is triggered on all online CPUs, after the capability is
* finalised, invoked within the stop_machine() context from
@@ -250,7 +250,7 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
#define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
#define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
/*
- * The capabilitiy is detected on the Boot CPU and is used by kernel
+ * The capability is detected on the Boot CPU and is used by kernel
* during early boot. i.e, the capability should be "detected" and
* "enabled" as early as possibly on all booting CPUs.
*/
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index b19a8aee684c..25bf7d15a115 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -288,7 +288,7 @@ bool pgattr_change_is_safe(u64 old, u64 new);
* 1 0 | 1 0 1
* 1 1 | 0 1 x
*
- * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
+ * When hardware DBM is not present, the software PTE_DIRTY bit is updated via
* the page fault mechanism. Checking the dirty status of a pte becomes:
*
* PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/suspend.h
index 0cde2f473971..e65f33edf9d6 100644
--- a/arch/arm64/include/asm/suspend.h
+++ b/arch/arm64/include/asm/suspend.h
@@ -23,7 +23,7 @@ struct cpu_suspend_ctx {
* __cpu_suspend_enter()'s caller, and populated by __cpu_suspend_enter().
* This data must survive until cpu_resume() is called.
*
- * This struct desribes the size and the layout of the saved cpu state.
+ * This struct describes the size and the layout of the saved cpu state.
* The layout of the callee_saved_regs is defined by the implementation
* of __cpu_suspend_enter(), and cpu_resume(). This struct must be passed
* in by the caller as __cpu_suspend_enter()'s stack-frame is gone once it
diff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h
index eefe766d6161..03084ed290ac 100644
--- a/arch/arm64/include/asm/traps.h
+++ b/arch/arm64/include/asm/traps.h
@@ -52,8 +52,8 @@ static inline int in_entry_text(unsigned long ptr)
* CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
* to indicate whether this ESR has a RAS encoding. CPUs without this feature
* have a ISS-Valid bit in the same position.
- * If this bit is set, we know its not a RAS SError.
- * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
+ * If this bit is set, we know it's not a RAS SError.
+ * If it's clear, we need to know if the CPU supports RAS. Uncategorized RAS
* errors share the same encoding as an all-zeros encoding from a CPU that
* doesn't support RAS.
*/
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index dba8fcec7f33..7eca4273b415 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -128,7 +128,7 @@ static int __init acpi_fadt_sanity_check(void)
/*
* FADT is required on arm64; retrieve it to check its presence
- * and carry out revision and ACPI HW reduced compliancy tests
+ * and carry out revision and ACPI HW reduced compliance tests
*/
status = acpi_get_table(ACPI_SIG_FADT, 0, &table);
if (ACPI_FAILURE(status)) {
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 646591c67e7a..3089526900a8 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -748,7 +748,7 @@ static int search_cmp_ftr_reg(const void *id, const void *regp)
* entry.
*
* returns - Upon success, matching ftr_reg entry for id.
- * - NULL on failure. It is upto the caller to decide
+ * - NULL on failure. It is up to the caller to decide
* the impact of a failure.
*/
static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
@@ -874,7 +874,7 @@ static void __init sort_ftr_regs(void)
/*
* Initialise the CPU feature register from Boot CPU values.
- * Also initiliases the strict_mask for the register.
+ * Also initialises the strict_mask for the register.
* Any bits that are not covered by an arm64_ftr_bits entry are considered
* RES0 for the system-wide value, and must strictly match.
*/
@@ -3108,7 +3108,7 @@ static void verify_local_cpu_caps(u16 scope_mask)
/*
* We have to issue cpu_enable() irrespective of
* whether the CPU has it or not, as it is enabeld
- * system wide. It is upto the call back to take
+ * system wide. It is up to the call back to take
* appropriate action on this CPU.
*/
if (caps->cpu_enable)
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index 0fc94207e69a..80b5268578a8 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -660,7 +660,7 @@ static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr)
static void noinstr el0_dbg(struct pt_regs *regs, unsigned long esr)
{
- /* Only watchpoints write FAR_EL1, otherwise its UNKNOWN */
+ /* Only watchpoints write FAR_EL1, otherwise it's UNKNOWN */
unsigned long far = read_sysreg(far_el1);
enter_from_user_mode(regs);
diff --git a/arch/arm64/kernel/entry-ftrace.S b/arch/arm64/kernel/entry-ftrace.S
index f0c16640ef21..e24e7d8f8b61 100644
--- a/arch/arm64/kernel/entry-ftrace.S
+++ b/arch/arm64/kernel/entry-ftrace.S
@@ -94,7 +94,7 @@ SYM_CODE_START(ftrace_caller)
stp x29, x30, [sp, #FREGS_SIZE]
add x29, sp, #FREGS_SIZE
- /* Prepare arguments for the the tracer func */
+ /* Prepare arguments for the tracer func */
sub x0, x30, #AARCH64_INSN_SIZE // ip (callsite's BL insn)
mov x1, x9 // parent_ip (callsite's LR)
mov x3, sp // regs
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index a6030913cd58..00bdd1fa8151 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -547,7 +547,7 @@ SYM_CODE_START_LOCAL(__bad_stack)
mrs x0, tpidrro_el0
/*
- * Store the original GPRs to the new stack. The orginal SP (minus
+ * Store the original GPRs to the new stack. The original SP (minus
* PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
*/
sub sp, sp, #PT_REGS_SIZE
diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index a650f5e11fc5..6e00b39059ff 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -423,7 +423,7 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
return ret;
/*
- * When using mcount, callsites in modules may have been initalized to
+ * When using mcount, callsites in modules may have been initialized to
* call an arbitrary module PLT (which redirects to the _mcount stub)
* rather than the ftrace PLT we'll use at runtime (which redirects to
* the ftrace trampoline). We can ignore the old PLT when initializing
diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_kexec.c
index 078910db77a4..36721a7e7855 100644
--- a/arch/arm64/kernel/machine_kexec.c
+++ b/arch/arm64/kernel/machine_kexec.c
@@ -296,7 +296,7 @@ void crash_post_resume(void)
* marked as Reserved as memory was allocated via memblock_reserve().
*
* In hibernation, the pages which are Reserved and yet "nosave" are excluded
- * from the hibernation iamge. crash_is_nosave() does thich check for crash
+ * from the hibernation image. crash_is_nosave() does this check for crash
* dump kernel and will reduce the total size of hibernation image.
*/
diff --git a/arch/arm64/kernel/probes/uprobes.c b/arch/arm64/kernel/probes/uprobes.c
index d49aef2657cd..5016f7f681c0 100644
--- a/arch/arm64/kernel/probes/uprobes.c
+++ b/arch/arm64/kernel/probes/uprobes.c
@@ -122,7 +122,7 @@ void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
struct uprobe_task *utask = current->utask;
/*
- * Task has received a fatal signal, so reset back to probbed
+ * Task has received a fatal signal, so reset back to probed
* address.
*/
instruction_pointer_set(regs, utask->vaddr);
diff --git a/arch/arm64/kernel/sdei.c b/arch/arm64/kernel/sdei.c
index 255d12f881c2..931f317a9ffa 100644
--- a/arch/arm64/kernel/sdei.c
+++ b/arch/arm64/kernel/sdei.c
@@ -206,7 +206,7 @@ unsigned long sdei_arch_get_entry_point(int conduit)
/*
* do_sdei_event() returns one of:
* SDEI_EV_HANDLED - success, return to the interrupted context.
- * SDEI_EV_FAILED - failure, return this error code to firmare.
+ * SDEI_EV_FAILED - failure, return this error code to firmware.
* virtual-address - success, return to this address.
*/
unsigned long __kprobes do_sdei_event(struct pt_regs *regs,
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index defbab84e9e5..8b8e1320033b 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -351,7 +351,7 @@ void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
/*
* Now that the dying CPU is beyond the point of no return w.r.t.
- * in-kernel synchronisation, try to get the firwmare to help us to
+ * in-kernel synchronisation, try to get the firmware to help us to
* verify that it has really left the kernel before we consider
* clobbering anything it might still be using.
*/
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 215e6d7f2df8..e76c71c54c8c 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -897,7 +897,7 @@ void __noreturn panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigne
__show_regs(regs);
/*
- * We use nmi_panic to limit the potential for recusive overflows, and
+ * We use nmi_panic to limit the potential for recursive overflows, and
* to get a better stack trace.
*/
nmi_panic(NULL, "kernel stack overflow");
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/arm64/boot/dts". Only touches
comments, no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: Conor Dooley <[email protected]>
Cc: [email protected]
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 2 +-
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 2 +-
arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +-
arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sa8155p.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 2 +-
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 2 +-
arch/arm64/boot/dts/renesas/draak.dtsi | 2 +-
arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts | 2 +-
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +-
16 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
index 723af64a9cee..bac2a1ecfb9e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
@@ -16,7 +16,7 @@ &backlight {
* PWM backlight circuit on this PinePhone revision was changed since
* 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
* being off is around 20%. Duty cycle for the lowest brightness level
- * also varries quite a bit between individual boards, so the lowest
+ * also varies quite a bit between individual boards, so the lowest
* value here was chosen as a safe default.
*/
brightness-levels = <
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 65ebac3082e2..8891a6c17347 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -123,7 +123,7 @@ gic: interrupt-controller@78090000 {
#address-cells = <2>;
#size-cells = <2>;
interrupt-controller;
- interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
+ interrupts = <1 9 0xf04>; /* GIC Maintenance IRQ */
ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
<0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 988928c60f15..ee1303a68d50 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -109,7 +109,7 @@ gic: interrupt-controller@78010000 {
<0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
<0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
<0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
- interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
+ interrupts = <1 9 0xf04>; /* GIC Maintenance IRQ */
};
timer {
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6ed80ddf3369..6e83d288de53 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -645,7 +645,7 @@ tmuctrl_0: tmu@10060000 {
ufs: ufs@15570000 {
compatible = "samsung,exynos7-ufs";
reg = <0x15570000 0x100>, /* 0: HCI standard */
- <0x15570100 0x100>, /* 1: Vendor specificed */
+ <0x15570100 0x100>, /* 1: Vendor specified */
<0x15571000 0x200>, /* 2: UNIPRO */
<0x15572000 0x300>; /* 3: UFS protector */
reg-names = "hci", "vs_hci", "unipro", "ufsp";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index eefe3577d94e..459e43785c83 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -150,7 +150,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
- reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
+ reg = <0x0 0x06020000 0 0x20000>;/* GIC Translator */
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
index d4867d6cf47c..7436d041cca4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Device Tree file for Travese Ten64 (LS1088) board
+ * Device Tree file for Traverse Ten64 (LS1088) board
* Based on fsl-ls1088a-rdb.dts
* Copyright 2017-2020 NXP
* Copyright 2019-2021 Traverse Technologies
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 49d105eb4769..2b41fbdf136e 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -504,7 +504,7 @@ pinctrl_hog2: hog2grp {
/*
* This pin is used in the SCFW as a UART. Using it from
- * Linux would require rewritting the SCFW board file.
+ * Linux would require rewriting the SCFW board file.
*/
pinctrl_hog_scfw: hogscfwgrp {
fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 4f799b536a92..34fa2843fdc7 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -666,12 +666,12 @@ in-ports {
/*
* Not described input ports:
- * 0 - connected to Resource and Power Manger CPU ETM
+ * 0 - connected to Resource and Power Manager CPU ETM
* 1 - not-connected
* 2 - connected to Modem CPU ETM
* 3 - not-connected
* 5 - not-connected
- * 6 - connected trought funnel to Wireless CPU ETM
+ * 6 - connected through funnel to Wireless CPU ETM
* 7 - connected to STM component
*/
diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
index cbc84459a5ae..4e0e7dfe1b4a 100644
--- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
@@ -857,7 +857,7 @@ &sdhc1 {
status = "okay";
/*
- * This device is shipped with HS400 capabable eMMCs
+ * This device is shipped with HS400 capable eMMCs
* However various brands have been used in various product batches,
* including a Samsung eMMC (BGND3R) which features a quirk with HS400.
* Set the speed to HS200 as a safety measure.
diff --git a/arch/arm64/boot/dts/qcom/sa8155p.dtsi b/arch/arm64/boot/dts/qcom/sa8155p.dtsi
index ffb7ab695213..1bc86a8529e1 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8155p.dtsi
@@ -4,7 +4,7 @@
*
* SA8155P is an automotive variant of SM8150, with some minor changes.
* Most notably, the RPMhPD setup differs: MMCX and LCX/LMX rails are gone,
- * though the cmd-db doesn't reflect that and access attemps result in a bite.
+ * though the cmd-db doesn't reflect that and access attempts result in a bite.
*/
#include "sm8150.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index f9b96bd2477e..9dae5931dead 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -563,8 +563,8 @@ &sdc1_rclk {
*
* This has entries that are defined by Qcard even if they go to the main
* board. In cases where the pulls may be board dependent we defer those
- * settings to the board device tree. Drive strengths tend to be assinged here
- * but could conceivably be overwridden by board device trees.
+ * settings to the board device tree. Drive strengths tend to be assigned here
+ * but could conceivably be overridden by board device trees.
*/
&pm8350c_gpios {
diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
index 32a7bd59e1ec..8f89352aeb73 100644
--- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
+++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
@@ -168,7 +168,7 @@ vph_pwr: vph-pwr-regulator {
* Supply map from xiaomi-lavender specifies this as the supply for
* ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies
* this as a power domain. Set this as a fixed regulator with the same
- * voltage as lavender until display is needed to avoid unneccessarily
+ * voltage as lavender until display is needed to avoid unnecessarily
* using a deprecated binding (regulator-fixed-domain).
*/
vreg_s2b_1p05: vreg-s2b-regulator {
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
index b02a1dc5fecd..a4be5c6ebb47 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
@@ -305,7 +305,7 @@ vreg_l19a_2p7: ldo19 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
/*
- * The driver *really* doesn't want this regualtor to exist,
+ * The driver *really* doesn't want this regulator to exist,
* saying that it could not get the current voltage (-ENOTRECOVERABLE)
* even though it surely is used on these devices (as a voltage
* source for camera autofocus)
diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi
index ef3bb835d5c0..67c36f71f4cb 100644
--- a/arch/arm64/boot/dts/renesas/draak.dtsi
+++ b/arch/arm64/boot/dts/renesas/draak.dtsi
@@ -226,7 +226,7 @@ &audio_clk_b {
/*
* X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
* and R-Car Sound uses AUDIO_CLKB.
- * Note is that schematic indicates VI4_FIELD conection only
+ * Note is that schematic indicates VI4_FIELD connection only
* not AUDIO_CLKB at SoC page.
* And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
* SW60 should be 1-2.
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts
index 7ba1c28f70a9..ce55f82268b2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts
@@ -9,7 +9,7 @@
/*
* Notice:
* 1. rk3399-roc-pc-plus is powered by dc_12v directly.
- * 2. rk3399-roc-pc-plus has only vcc_bus_typec0 in schematic, which is coresponding
+ * 2. rk3399-roc-pc-plus has only vcc_bus_typec0 in schematic, which is corresponding
* to vcc_vbus_typec1 in rk3399-roc-pc.
* For simplicity, reserve the node name of vcc_vbus_typec1.
* 3. vcc5v0_host is actually 2 regulators (host0, 1) controlled by the same gpio.
diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
index 5db52f237253..e99e69027125 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
@@ -1415,7 +1415,7 @@ &usbss0 {
status = "disabled";
};
-/* TODO: role swich using ID pin */
+/* TODO: role switch using ID pin */
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>;
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/arm64". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: James Morse <[email protected]>
Cc: Suzuki K Poulose <[email protected]>
Cc: Zenghui Yu <[email protected]>
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
arch/arm64/include/asm/kvm_hyp.h | 2 +-
arch/arm64/kvm/arch_timer.c | 2 +-
arch/arm64/kvm/fpsimd.c | 2 +-
arch/arm64/kvm/hyp/nvhe/host.S | 2 +-
arch/arm64/kvm/hyp/nvhe/mm.c | 4 ++--
arch/arm64/kvm/inject_fault.c | 2 +-
arch/arm64/kvm/vgic/vgic-init.c | 2 +-
arch/arm64/kvm/vgic/vgic-its.c | 4 ++--
8 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
index 145ce73fc16c..3e2a1ac0c9bb 100644
--- a/arch/arm64/include/asm/kvm_hyp.h
+++ b/arch/arm64/include/asm/kvm_hyp.h
@@ -70,7 +70,7 @@ DECLARE_PER_CPU(struct kvm_nvhe_init_params, kvm_init_params);
/*
* Without an __arch_swab32(), we fall back to ___constant_swab32(), but the
* static inline can allow the compiler to out-of-line this. KVM always wants
- * the macro version as its always inlined.
+ * the macro version as it's always inlined.
*/
#define __kvm_swab32(x) ___constant_swab32(x)
diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c
index 13ba691b848f..ded8063b8813 100644
--- a/arch/arm64/kvm/arch_timer.c
+++ b/arch/arm64/kvm/arch_timer.c
@@ -746,7 +746,7 @@ static void kvm_timer_vcpu_load_nested_switch(struct kvm_vcpu *vcpu,
WARN_ON_ONCE(ret);
/*
- * The virtual offset behaviour is "interresting", as it
+ * The virtual offset behaviour is "interesting", as it
* always applies when HCR_EL2.E2H==0, but only when
* accessed from EL1 when HCR_EL2.E2H==1. So make sure we
* track E2H when putting the HV timer in "direct" mode.
diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c
index 8c1d0d4853df..571cf6eef1e1 100644
--- a/arch/arm64/kvm/fpsimd.c
+++ b/arch/arm64/kvm/fpsimd.c
@@ -117,7 +117,7 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu)
}
/*
- * Called just before entering the guest once we are no longer preemptable
+ * Called just before entering the guest once we are no longer preemptible
* and interrupts are disabled. If we have managed to run anything using
* FP while we were preemptible (such as off the back of an interrupt),
* then neither the host nor the guest own the FP hardware (and it was the
diff --git a/arch/arm64/kvm/hyp/nvhe/host.S b/arch/arm64/kvm/hyp/nvhe/host.S
index 7693a6757cd7..135cfb294ee5 100644
--- a/arch/arm64/kvm/hyp/nvhe/host.S
+++ b/arch/arm64/kvm/hyp/nvhe/host.S
@@ -110,7 +110,7 @@ SYM_FUNC_END(__host_enter)
* u64 elr, u64 par);
*/
SYM_FUNC_START(__hyp_do_panic)
- /* Prepare and exit to the host's panic funciton. */
+ /* Prepare and exit to the host's panic function. */
mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
PSR_MODE_EL1h)
msr spsr_el2, lr
diff --git a/arch/arm64/kvm/hyp/nvhe/mm.c b/arch/arm64/kvm/hyp/nvhe/mm.c
index 65a7a186d7b2..daf91a7989d7 100644
--- a/arch/arm64/kvm/hyp/nvhe/mm.c
+++ b/arch/arm64/kvm/hyp/nvhe/mm.c
@@ -155,7 +155,7 @@ int hyp_back_vmemmap(phys_addr_t back)
start = hyp_memory[i].base;
start = ALIGN_DOWN((u64)hyp_phys_to_page(start), PAGE_SIZE);
/*
- * The begining of the hyp_vmemmap region for the current
+ * The beginning of the hyp_vmemmap region for the current
* memblock may already be backed by the page backing the end
* the previous region, so avoid mapping it twice.
*/
@@ -408,7 +408,7 @@ static void *admit_host_page(void *arg)
return pop_hyp_memcache(host_mc, hyp_phys_to_virt);
}
-/* Refill our local memcache by poping pages from the one provided by the host. */
+/* Refill our local memcache by popping pages from the one provided by the host. */
int refill_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages,
struct kvm_hyp_memcache *host_mc)
{
diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
index 0bd93a5f21ce..a640e839848e 100644
--- a/arch/arm64/kvm/inject_fault.c
+++ b/arch/arm64/kvm/inject_fault.c
@@ -134,7 +134,7 @@ static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt, u32 addr)
if (vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE) {
fsr = DFSR_LPAE | DFSR_FSC_EXTABT_LPAE;
} else {
- /* no need to shuffle FS[4] into DFSR[10] as its 0 */
+ /* no need to shuffle FS[4] into DFSR[10] as it's 0 */
fsr = DFSR_FSC_EXTABT_nLPAE;
}
diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
index c8c3cb812783..a0a9badaa91c 100644
--- a/arch/arm64/kvm/vgic/vgic-init.c
+++ b/arch/arm64/kvm/vgic/vgic-init.c
@@ -309,7 +309,7 @@ int vgic_init(struct kvm *kvm)
vgic_lpi_translation_cache_init(kvm);
/*
- * If we have GICv4.1 enabled, unconditionnaly request enable the
+ * If we have GICv4.1 enabled, unconditionally request enable the
* v4 support so that we get HW-accelerated vSGIs. Otherwise, only
* enable it if we present a virtual ITS to the guest.
*/
diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c
index 2dad2d095160..39d8c15202e7 100644
--- a/arch/arm64/kvm/vgic/vgic-its.c
+++ b/arch/arm64/kvm/vgic/vgic-its.c
@@ -1337,8 +1337,8 @@ static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its,
}
/**
- * vgic_its_invall - invalidate all LPIs targetting a given vcpu
- * @vcpu: the vcpu for which the RD is targetted by an invalidation
+ * vgic_its_invall - invalidate all LPIs targeting a given vcpu
+ * @vcpu: the vcpu for which the RD is targeted by an invalidation
*
* Contrary to the INVALL command, this targets a RD instead of a
* collection, and we don't need to hold the its_lock, since no ITS is
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/mips". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: [email protected]
---
arch/mips/bcm47xx/buttons.c | 6 +++---
arch/mips/bcm63xx/clk.c | 4 ++--
arch/mips/boot/compressed/dbg.c | 2 +-
arch/mips/boot/elf2ecoff.c | 2 +-
arch/mips/cavium-octeon/csrc-octeon.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-boot-vector.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c | 4 ++--
arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c | 2 +-
arch/mips/cavium-octeon/executive/cvmx-pko.c | 2 +-
arch/mips/cavium-octeon/octeon-platform.c | 2 +-
arch/mips/fw/arc/promlib.c | 6 +++---
arch/mips/include/asm/debug.h | 2 +-
arch/mips/include/asm/io.h | 4 ++--
arch/mips/include/asm/mach-au1x00/au1000_dma.h | 2 +-
arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 2 +-
arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h | 2 +-
arch/mips/include/asm/mach-loongson64/loongson_hwmon.h | 2 +-
arch/mips/include/asm/mach-loongson64/loongson_regs.h | 2 +-
arch/mips/include/asm/mach-malta/spaces.h | 4 ++--
arch/mips/include/asm/mips-boards/bonito64.h | 2 +-
arch/mips/include/asm/mips-cpc.h | 2 +-
arch/mips/include/asm/mipsregs.h | 4 ++--
arch/mips/include/asm/octeon/cvmx-bootinfo.h | 2 +-
arch/mips/include/asm/octeon/cvmx-cmd-queue.h | 6 +++---
arch/mips/include/asm/octeon/cvmx-pko.h | 2 +-
arch/mips/include/asm/octeon/cvmx-pow.h | 4 ++--
arch/mips/include/asm/octeon/octeon-model.h | 4 ++--
arch/mips/include/asm/page.h | 2 +-
arch/mips/include/asm/pci.h | 2 +-
arch/mips/include/asm/pgtable-bits.h | 2 +-
arch/mips/include/asm/sgi/mc.h | 2 +-
arch/mips/include/asm/sn/klconfig.h | 2 +-
arch/mips/include/asm/sync.h | 2 +-
arch/mips/include/asm/thread_info.h | 2 +-
arch/mips/include/asm/timex.h | 2 +-
arch/mips/include/asm/vdso/vdso.h | 2 +-
arch/mips/include/uapi/asm/mman.h | 2 +-
arch/mips/include/uapi/asm/msgbuf.h | 2 +-
arch/mips/kernel/cpu-probe.c | 2 +-
arch/mips/kernel/kprobes.c | 2 +-
arch/mips/kernel/relocate.c | 2 +-
arch/mips/kernel/relocate_kernel.S | 2 +-
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/signal.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/kernel/vpe.c | 4 ++--
arch/mips/kvm/emulate.c | 2 +-
arch/mips/loongson2ef/common/platform.c | 2 +-
arch/mips/loongson64/smp.c | 2 +-
arch/mips/mm/c-r4k.c | 2 +-
arch/mips/mm/cex-gen.S | 2 +-
arch/mips/mm/tlb-r3k.c | 2 +-
arch/mips/mm/tlb-r4k.c | 2 +-
arch/mips/mm/tlbex.c | 4 ++--
arch/mips/net/bpf_jit_comp32.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/pci-alchemy.c | 2 +-
arch/mips/pci/pci-ar2315.c | 2 +-
arch/mips/pci/pci-lantiq.c | 2 +-
arch/mips/pci/pci-octeon.c | 2 +-
arch/mips/pci/pci-xtalk-bridge.c | 2 +-
arch/mips/pci/pcie-octeon.c | 2 +-
arch/mips/ralink/mt7621.c | 2 +-
arch/mips/txx9/generic/pci.c | 2 +-
65 files changed, 80 insertions(+), 80 deletions(-)
diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
index 437a737c01dd..46994f9bb821 100644
--- a/arch/mips/bcm47xx/buttons.c
+++ b/arch/mips/bcm47xx/buttons.c
@@ -147,21 +147,21 @@ static const struct gpio_keys_button
bcm47xx_buttons_buffalo_whr_g125[] __initconst = {
BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
BCM47XX_GPIO_KEY(4, KEY_RESTART),
- BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
+ BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
};
static const struct gpio_keys_button
bcm47xx_buttons_buffalo_whr_g54s[] __initconst = {
BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
BCM47XX_GPIO_KEY_H(4, KEY_RESTART),
- BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
+ BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
};
static const struct gpio_keys_button
bcm47xx_buttons_buffalo_whr_hp_g54[] __initconst = {
BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
BCM47XX_GPIO_KEY(4, KEY_RESTART),
- BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
+ BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
};
static const struct gpio_keys_button
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 86a6e2590866..3144965fb7dc 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -174,7 +174,7 @@ static void enetsw_set(struct clk *clk, int enable)
}
if (enable) {
- /* reset switch core afer clock change */
+ /* reset switch core after clock change */
bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
msleep(10);
bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
@@ -304,7 +304,7 @@ static void xtm_set(struct clk *clk, int enable)
bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
if (enable) {
- /* reset sar core afer clock change */
+ /* reset sar core after clock change */
bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
mdelay(1);
bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
index f6728a8fd1c3..98dfb2e59dfe 100644
--- a/arch/mips/boot/compressed/dbg.c
+++ b/arch/mips/boot/compressed/dbg.c
@@ -3,7 +3,7 @@
* MIPS-specific debug support for pre-boot environment
*
* NOTE: putc() is board specific, if your board have a 16550 compatible uart,
- * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
+ * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. otherwise, you
* need to implement your own putc().
*/
#include <linux/compiler.h>
diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
index 6972b97235da..549c5d6ef6d7 100644
--- a/arch/mips/boot/elf2ecoff.c
+++ b/arch/mips/boot/elf2ecoff.c
@@ -443,7 +443,7 @@ int main(int argc, char *argv[])
efh.f_symptr = 0;
efh.f_nsyms = 0;
efh.f_opthdr = sizeof eah;
- efh.f_flags = 0x100f; /* Stripped, not sharable. */
+ efh.f_flags = 0x100f; /* Stripped, not shareable. */
memset(esecs, 0, sizeof esecs);
strcpy(esecs[0].s_name, ".text");
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 124817609ce0..af62a210a40b 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -113,7 +113,7 @@ static struct clocksource clocksource_mips = {
unsigned long long notrace sched_clock(void)
{
- /* 64-bit arithmatic can overflow, so use 128-bit. */
+ /* 64-bit arithmetic can overflow, so use 128-bit. */
u64 t1, t2, t3;
unsigned long long rv;
u64 mult = clocksource_mips.mult;
diff --git a/arch/mips/cavium-octeon/executive/cvmx-boot-vector.c b/arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
index b7019d21808e..76446db66def 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
@@ -143,7 +143,7 @@ static void cvmx_boot_vector_init(void *mem)
uint64_t v = _cvmx_bootvector_data[i];
if (OCTEON_IS_OCTEON1PLUS() && (i == 0 || i == 7))
- v &= 0xffffffff00000000ull; /* KScratch not availble. */
+ v &= 0xffffffff00000000ull; /* KScratch not available */
cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 334bf8e577e5..628ebdf4b9c5 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -264,7 +264,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
* Convert !0 address_min and 0 address_max to special case of
* range that specifies an exact memory block to allocate. Do
* this before other checks and adjustments so that this
- * tranformation will be validated.
+ * transformation will be validated.
*/
if (address_min && !address_max)
address_max = address_min + req_size;
diff --git a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
index aa7bbf8d0df5..042a6bc44b5c 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
@@ -192,7 +192,7 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
}
/*
- * Shutdown a queue a free it's command buffers to the FPA. The
+ * Shutdown a queue and free its command buffers to the FPA. The
* hardware connected to the queue must be stopped before this
* function is called.
*
@@ -285,7 +285,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
/*
* Return the command buffer to be written to. The purpose of this
- * function is to allow CVMX routine access t othe low level buffer
+ * function is to allow CVMX routine access to the low level buffer
* for initial hardware setup. User applications should not call this
* function directly.
*
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
index 607b4e659579..1fceb7fd2c94 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
@@ -103,7 +103,7 @@ uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
/**
* Shift long sequences of zeros into the QLM JTAG chain. It is
* common to need to shift more than 32 bits of zeros into the
- * chain. This function is a convience wrapper around
+ * chain. This function is a convenience wrapper around
* cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
* zeros at a time.
*
diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index 15faca494c80..6e70b859a0ac 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -615,7 +615,7 @@ int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
/*
* Each packet has a 12 bytes of interframe gap, an 8 byte
* preamble, and a 4 byte CRC. These are not included in the
- * per word count. Multiply by 8 to covert to bits and divide
+ * per word count. Multiply by 8 to convert to bits and divide
* by 256 for limit granularity.
*/
pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index f76783c24338..5e1dd4e6e82f 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -973,7 +973,7 @@ int __init octeon_prune_device_tree(void)
* zero.
*/
- /* Asume that CS1 immediately follows. */
+ /* Assume that CS1 immediately follows. */
mio_boot_reg_cfg.u64 =
cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
region1_base = mio_boot_reg_cfg.s.base << 16;
diff --git a/arch/mips/fw/arc/promlib.c b/arch/mips/fw/arc/promlib.c
index 5e9e840a9314..93e1e70393ee 100644
--- a/arch/mips/fw/arc/promlib.c
+++ b/arch/mips/fw/arc/promlib.c
@@ -15,11 +15,11 @@
/*
* For 64bit kernels working with a 32bit ARC PROM pointer arguments
* for ARC calls need to reside in CKEG0/1. But as soon as the kernel
- * switches to it's first kernel thread stack is set to an address in
+ * switches to its first kernel thread stack is set to an address in
* XKPHYS, so anything on stack can't be used anymore. This is solved
- * by using a * static declartion variables are put into BSS, which is
+ * by using a * static declaration variables are put into BSS, which is
* linked to a CKSEG0 address. Since this is only used on UP platforms
- * there is not spinlock needed
+ * there is no spinlock needed
*/
#define O32_STATIC static
#else
diff --git a/arch/mips/include/asm/debug.h b/arch/mips/include/asm/debug.h
index c7013e1cb53f..e70392429246 100644
--- a/arch/mips/include/asm/debug.h
+++ b/arch/mips/include/asm/debug.h
@@ -10,7 +10,7 @@
/*
* mips_debugfs_dir corresponds to the "mips" directory at the top level
- * of the DebugFS hierarchy. MIPS-specific DebugFS entires should be
+ * of the DebugFS hierarchy. MIPS-specific DebugFS entries should be
* placed beneath this directory.
*/
extern struct dentry *mips_debugfs_dir;
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 062dd4e6b954..bba327dc1226 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -179,7 +179,7 @@ void iounmap(const volatile void __iomem *addr);
* address is not guaranteed to be usable directly as a virtual
* address.
*
- * This version of ioremap ensures that the memory is marked cachable by
+ * This version of ioremap ensures that the memory is marked cacheable by
* the CPU. Also enables full write-combining. Useful for some
* memory-like regions on I/O busses.
*/
@@ -197,7 +197,7 @@ void iounmap(const volatile void __iomem *addr);
* address is not guaranteed to be usable directly as a virtual
* address.
*
- * This version of ioremap ensures that the memory is marked uncachable
+ * This version of ioremap ensures that the memory is marked uncacheable
* but accelerated by means of write-combining feature. It is specifically
* useful for PCIe prefetchable windows, which may vastly improve a
* communications performance. If it was determined on boot stage, what
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index 0a0cd4270c6f..b82e513c8523 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -259,7 +259,7 @@ static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
if (!chan)
return;
/*
- * set_dma_mode is only allowed to change endianess, direction,
+ * set_dma_mode is only allowed to change endianness, direction,
* transfer size, device FIFO width, and coherency settings.
* Make sure anything else is masked off.
*/
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 82bc2766e2ec..d820b481ac56 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -435,7 +435,7 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
/**
* alchemy_gpio2_enable - Activate GPIO2 block.
*
- * The GPIO2 block must be enabled excplicitly to work. On systems
+ * The GPIO2 block must be enabled explicitly to work. On systems
* where this isn't done by the bootloader, this macro can be used.
*/
static inline void alchemy_gpio2_enable(void)
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index 5855ba1bd1ec..40eaa72e54d0 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -55,7 +55,7 @@ extern __iomem void *ltq_sys1_membase;
#define ltq_sys1_w32_mask(clear, set, reg) \
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
-/* allow the gpio and pinctrl drivers to talk to eachother */
+/* allow the gpio and pinctrl drivers to talk to each other */
extern int pinctrl_falcon_get_range_size(int id);
extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
diff --git a/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h b/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
index 545f91f2ae16..721eafc4644e 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
@@ -42,7 +42,7 @@ struct loongson_fan_policy {
/* period between two check. (Unit: S) */
u8 adjust_period;
- /* fan adjust usually depend on a temprature input */
+ /* fan adjust usually depend on a temperature input */
get_temp_fun depend_temp;
/* up_step/down_step used when type is STEP_SPEED_POLICY */
diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
index b5be7511f6cd..fec767507604 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
@@ -227,7 +227,7 @@ static inline void csr_writeq(u64 val, u32 reg)
#define LOONGSON_CSR_NODECNT 0x408
#define LOONGSON_CSR_CPUTEMP 0x428
-/* PerCore CSR, only accessable by local cores */
+/* PerCore CSR, only accessible by local cores */
#define LOONGSON_CSR_IPI_STATUS 0x1000
#define LOONGSON_CSR_IPI_EN 0x1004
#define LOONGSON_CSR_IPI_SET 0x1008
diff --git a/arch/mips/include/asm/mach-malta/spaces.h b/arch/mips/include/asm/mach-malta/spaces.h
index d7e54971ec66..1ce4ba97852f 100644
--- a/arch/mips/include/asm/mach-malta/spaces.h
+++ b/arch/mips/include/asm/mach-malta/spaces.h
@@ -23,13 +23,13 @@
* The kernel is still located in 0x80000000(kseg0). However,
* the physical mask has been shifted to 0x80000000 which exploits the alias
* on the Malta board. As a result of which, we override the __pa_symbol
- * to peform direct mapping from virtual to physical addresses. In other
+ * to perform direct mapping from virtual to physical addresses. In other
* words, the 0x80000000 virtual address maps to 0x80000000 physical address
* which in turn aliases to 0x0. We do this in order to be able to use a flat
* 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
* 0x10000000 - 0x1fffffff.
* The last 64KB of physical memory are reserved for correct HIGHMEM
- * macros arithmetics.
+ * macros arithmetic.
*
*/
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index 5368891d424b..31a31fe78d77 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -16,7 +16,7 @@
*/
/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
-/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
+/* This bonito64 version edited from bonito.h Revision 1.48 on 11/09/00 */
#ifndef _ASM_MIPS_BOARDS_BONITO64_H
#define _ASM_MIPS_BOARDS_BONITO64_H
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h
index b54453f1648c..5f3a7a9f42bf 100644
--- a/arch/mips/include/asm/mips-cpc.h
+++ b/arch/mips/include/asm/mips-cpc.h
@@ -22,7 +22,7 @@ extern void __iomem *mips_cpc_base;
* the CPC
*
* Returns the default physical base address of the Cluster Power Controller
- * memory mapped registers. This is platform dependant & must therefore be
+ * memory mapped registers. This is platform dependent & must therefore be
* implemented per-platform.
*/
extern phys_addr_t mips_cpc_default_phys_base(void);
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2d53704d9f24..ec58cb76d076 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -98,7 +98,7 @@
/*
* R4640/R4650 cp0 register names. These registers are listed
- * here only for completeness; without MMU these CPUs are not useable
+ * here only for completeness; without MMU these CPUs are not usable
* by Linux. A future ELKS port might take make Linux run on them
* though ...
*/
@@ -461,7 +461,7 @@
#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
-#define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
+#define EXCCODE_CACHEERR 30 /* Parity/ECC occurred on a core */
/* Implementation specific trap codes used by MIPS cores */
#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index c1c0b3230e0a..028bf1d6daee 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -114,7 +114,7 @@ struct cvmx_bootinfo {
/*
* flags indicating various configuration options. These
- * flags supercede the 'flags' variable and should be used
+ * flags supersede the 'flags' variable and should be used
* instead if available.
*/
uint32_t config_flags;
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index a07a36f7d814..67e1b2162b19 100644
--- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -145,7 +145,7 @@ typedef struct {
/**
* This structure contains the global state of all command queues.
* It is stored in a bootmem named block and shared by all
- * applications running on Octeon. Tickets are stored in a differnet
+ * applications running on Octeon. Tickets are stored in a different
* cache line that queue information to reduce the contention on the
* ll/sc used to get a ticket. If this is not the case, the update
* of queue state causes the ll/sc to fail quite often.
@@ -172,7 +172,7 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
int pool_size);
/**
- * Shutdown a queue a free it's command buffers to the FPA. The
+ * Shutdown a queue and free its command buffers to the FPA. The
* hardware connected to the queue must be stopped before this
* function is called.
*
@@ -194,7 +194,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
/**
* Return the command buffer to be written to. The purpose of this
- * function is to allow CVMX routine access t othe low level buffer
+ * function is to allow CVMX routine access to the low level buffer
* for initial hardware setup. User applications should not call this
* function directly.
*
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index 5fec8476e421..f18a7f24daf8 100644
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -91,7 +91,7 @@ typedef enum {
} cvmx_pko_status_t;
/**
- * This enumeration represents the differnet locking modes supported by PKO.
+ * This enumeration represents the different locking modes supported by PKO.
*/
typedef enum {
/*
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index a3b23811e0c3..21b4378244fa 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -1342,7 +1342,7 @@ static inline void cvmx_pow_tag_sw_wait(void)
* This function does NOT wait for previous tag switches to complete,
* so the caller must ensure that there is not a pending tag switch.
*
- * @wait: When set, call stalls until work becomes avaiable, or times out.
+ * @wait: When set, call stalls until work becomes available, or times out.
* If not set, returns immediately.
*
* Returns: the WQE pointer from POW. Returns NULL if no work
@@ -1376,7 +1376,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_
* This function waits for any previous tag switch to complete before
* requesting the new work.
*
- * @wait: When set, call stalls until work becomes avaiable, or times out.
+ * @wait: When set, call stalls until work becomes available, or times out.
* If not set, returns immediately.
*
* Returns: the WQE pointer from POW. Returns NULL if no work
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 6c68517c2770..e53b61a8e32f 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -54,7 +54,7 @@
#define OM_CHECK_SUBMODEL 0x02000000
/* Match all models previous than the one specified */
#define OM_MATCH_PREVIOUS_MODELS 0x04000000
-/* Ignores the minor revison on newer parts */
+/* Ignores the minor revision on newer parts */
#define OM_IGNORE_MINOR_REVISION 0x08000000
#define OM_FLAG_MASK 0xff000000
@@ -226,7 +226,7 @@
#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
/*
- * CN3XXX models with old revision enconding
+ * CN3XXX models with old revision encoding
*/
#define OCTEON_CN38XX_PASS1 0x000d0000
#define OCTEON_CN38XX_PASS2 0x000d0001
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 5978a8dfb917..ef9585d96f6b 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -173,7 +173,7 @@ static inline unsigned long ___pa(unsigned long x)
if (IS_ENABLED(CONFIG_64BIT)) {
/*
* For MIPS64 the virtual address may either be in one of
- * the compatibility segements ckseg0 or ckseg1, or it may
+ * the compatibility segments ckseg0 or ckseg1, or it may
* be in xkphys.
*/
return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 3fd6e22c108b..d993df6302dc 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -23,7 +23,7 @@
#ifdef CONFIG_PCI_DRIVERS_LEGACY
/*
- * Each pci channel is a top-level PCI bus seem by CPU. A machine with
+ * Each PCI channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 421e78c30253..088623ba7b8b 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -201,7 +201,7 @@ enum pgtable_bits {
* The final layouts of the PTE bits are:
*
* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
- * 32-bit, R1 or earler: CCC D V G M A W R P
+ * 32-bit, R1 or earlier: CCC D V G M A W R P
* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
*/
diff --git a/arch/mips/include/asm/sgi/mc.h b/arch/mips/include/asm/sgi/mc.h
index 3a070cec97e7..5e96f9d32624 100644
--- a/arch/mips/include/asm/sgi/mc.h
+++ b/arch/mips/include/asm/sgi/mc.h
@@ -96,7 +96,7 @@ struct sgimc_regs {
volatile u32 lbursttp; /* Time period for long bursts */
/* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
- * be the same size. The size encoding for supported SIMMs is bellow */
+ * be the same size. The size encoding for supported SIMMs is below */
u32 _unused11[9];
volatile u32 mconfig0; /* Memory config register zero */
u32 _unused12;
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
index 117f85e4bef5..3d1670b3e052 100644
--- a/arch/mips/include/asm/sn/klconfig.h
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -851,7 +851,7 @@ typedef union kldev_s { /* for device structure allocation */
/*
* TBD - Allocation issues.
*
- * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
+ * Do we need to Mark off separate heaps for lboard_t, rboard_t, component,
* errinfo and allocate from them, or have a single heap and allocate all
* structures from it. Debug is easier in the former method since we can
* dump all similar structs in one command, but there will be lots of holes,
diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h
index aabd097933fe..44c04a82d0b7 100644
--- a/arch/mips/include/asm/sync.h
+++ b/arch/mips/include/asm/sync.h
@@ -19,7 +19,7 @@
*
* Ordering barriers can be more efficient than completion barriers, since:
*
- * a) Ordering barriers only require memory access instructions which preceed
+ * a) Ordering barriers only require memory access instructions which precede
* them in program order (older instructions) to reach a point in the
* load/store datapath beyond which reordering is not possible before
* allowing memory access instructions which follow them (younger
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index ecae7470faa4..b9d76e8ac5a2 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -27,7 +27,7 @@ struct thread_info {
unsigned long flags; /* low level flags */
unsigned long tp_value; /* thread pointer */
__u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
+ int preempt_count; /* 0 => preemptible, <0 => BUG */
struct pt_regs *regs;
long syscall; /* syscall number */
};
diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
index 2e107886f97a..7ef06dcdc46e 100644
--- a/arch/mips/include/asm/timex.h
+++ b/arch/mips/include/asm/timex.h
@@ -46,7 +46,7 @@ typedef unsigned int cycles_t;
*
* There is a suggested workaround and also the erratum can't strike if
* the compare interrupt isn't being used as the clock source device.
- * However for now the implementaton of this function doesn't get these
+ * However for now the implementation of this function doesn't get these
* fine details right.
*/
static inline int can_use_mips_counter(unsigned int prid)
diff --git a/arch/mips/include/asm/vdso/vdso.h b/arch/mips/include/asm/vdso/vdso.h
index a327ca21270e..6cd88191fefa 100644
--- a/arch/mips/include/asm/vdso/vdso.h
+++ b/arch/mips/include/asm/vdso/vdso.h
@@ -32,7 +32,7 @@ static inline unsigned long get_vdso_base(void)
#else
/*
* Get the base load address of the VDSO. We have to avoid generating
- * relocations and references to the GOT because ld.so does not peform
+ * relocations and references to the GOT because ld.so does not perform
* relocations on the VDSO. We use the current offset from the VDSO base
* and perform a PC-relative branch which gives the absolute address in
* ra, and take the difference. The assembler chokes on
diff --git a/arch/mips/include/uapi/asm/mman.h b/arch/mips/include/uapi/asm/mman.h
index c6e1fc77c996..9c48d9a21aa0 100644
--- a/arch/mips/include/uapi/asm/mman.h
+++ b/arch/mips/include/uapi/asm/mman.h
@@ -88,7 +88,7 @@
#define MADV_HUGEPAGE 14 /* Worth backing with hugepages */
#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */
-#define MADV_DONTDUMP 16 /* Explicity exclude from the core dump,
+#define MADV_DONTDUMP 16 /* Explicitly exclude from core dump,
overrides the coredump filter bits */
#define MADV_DODUMP 17 /* Clear the MADV_NODUMP flag */
diff --git a/arch/mips/include/uapi/asm/msgbuf.h b/arch/mips/include/uapi/asm/msgbuf.h
index 128af72f2dfe..d546642fc67e 100644
--- a/arch/mips/include/uapi/asm/msgbuf.h
+++ b/arch/mips/include/uapi/asm/msgbuf.h
@@ -62,7 +62,7 @@ struct msqid64_ds {
unsigned long __unused5;
};
#else
-#warning no endianess set
+#warning no endianness set
#endif
#endif /* _ASM_MSGBUF_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b406d8bfb15a..2f4fafdc5fcc 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1139,7 +1139,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
* This processor doesn't have an MMU, so it's not
* "real easy" to run Linux on it. It is left purely
* for documentation. Commented out because it shares
- * it's c0_prid id number with the TX3900.
+ * its c0_prid id number with the TX3900.
*/
c->cputype = CPU_R4650;
__cpu_name[cpu] = "R4650";
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index 316b27d0d2fb..dc39f5b3fb83 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -55,7 +55,7 @@ NOKPROBE_SYMBOL(insn_has_delayslot);
* one; putting breakpoint on top of atomic ll/sc pair is bad idea;
* so we need to prevent it and refuse kprobes insertion for such
* instructions; cannot do much about breakpoint in the middle of
- * ll/sc pair; it is upto user to avoid those places
+ * ll/sc pair; it is up to user to avoid those places
*/
static int insn_has_ll_or_sc(union mips_instruction insn)
{
diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c
index 58fc8d089402..7eeeaf1ff95d 100644
--- a/arch/mips/kernel/relocate.c
+++ b/arch/mips/kernel/relocate.c
@@ -380,7 +380,7 @@ void *__init relocate_kernel(void)
}
#endif /* CONFIG_USE_OF */
- /* Copy the kernel to it's new location */
+ /* Copy the kernel to its new location */
memcpy(loc_new, &_text, kernel_length);
/* Perform relocations on the new kernel */
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index 8f0a7263a9d6..de894a0211d7 100644
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -70,7 +70,7 @@ copy_word:
done:
#ifdef CONFIG_SMP
/* kexec_flag reset is signal to other CPUs what kernel
- was moved to it's location. Note - we need relocated address
+ was moved to its location. Note - we need relocated address
of kexec_flag. */
bal 1f
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2d2ca024bd47..f849667c2c57 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -146,7 +146,7 @@ static unsigned long __init init_initrd(void)
/*
* Board specific code or command line parser should have
* already set up initrd_start and initrd_end. In these cases
- * perfom sanity checks and use them if all looks good.
+ * perform sanity checks and use them if all looks good.
*/
if (!initrd_start || initrd_end <= initrd_start)
goto disable;
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 479999b7f2de..a8e20fdc7afd 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -569,7 +569,7 @@ void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
return (void __user __force *)(-1UL);
/*
- * FPU emulator may have it's own trampoline active just
+ * FPU emulator may have its own trampoline active just
* above the user stack, 16-bytes before the next lowest
* 16 byte boundary. Try to avoid trashing it.
*/
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 246c6a6b0261..6aaa83834d07 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2418,7 +2418,7 @@ void __init trap_init(void)
set_except_vector(i, handle_reserved);
/*
- * Copy the EJTAG debug exception vector handler code to it's final
+ * Copy the EJTAG debug exception vector handler code to its final
* destination.
*/
if (cpu_has_ejtag && board_ejtag_handler_setup)
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index e9a0cfd02ae2..737d0d4fdcd3 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -6,9 +6,9 @@
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2013 Imagination Technologies Ltd.
*
- * VPE spport module for loading a MIPS SP program into VPE1. The SP
+ * VPE support module for loading a MIPS SP program into VPE1. The SP
* environment is rather simple since there are no TLBs. It needs
- * to be relocatable (or partiall linked). Initialize your stack in
+ * to be relocatable (or partially linked). Initialize your stack in
* the startup-code. The loader looks for the symbol __start and sets
* up the execution to resume from there. To load and run, simply do
* a cat SP 'binary' to the /dev/vpe1 device.
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index e64372b8f66a..0feec52222fb 100644
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -531,7 +531,7 @@ static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
* to be used for a period of time, but the exact ktime corresponding to the
* final Count that must be restored is not known.
*
- * It is gauranteed that a timer interrupt immediately after restore will be
+ * It is guaranteed that a timer interrupt immediately after restore will be
* handled, but not if CP0_Compare is exactly at @count. That case should
* already be handled when the hardware timer state is saved.
*
diff --git a/arch/mips/loongson2ef/common/platform.c b/arch/mips/loongson2ef/common/platform.c
index 0084820cffaa..b10300a527af 100644
--- a/arch/mips/loongson2ef/common/platform.c
+++ b/arch/mips/loongson2ef/common/platform.c
@@ -17,7 +17,7 @@ static int __init loongson2_cpufreq_init(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
- /* Only 2F revision and it's successors support CPUFreq */
+ /* Only 2F revision and its successors support CPUFreq */
if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
return platform_device_register(&loongson2_cpufreq_device);
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e015a26a40f7..4f6c714430da 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -516,7 +516,7 @@ static void __init loongson3_prepare_cpus(unsigned int max_cpus)
}
/*
- * Setup the PC, SP, and GP of a secondary processor and start it runing!
+ * Setup the PC, SP, and GP of a secondary processor and start it running!
*/
static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
{
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 187d1c16361c..20d37773b162 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1654,7 +1654,7 @@ static void coherency_setup(void)
/*
* c0_status.cu=0 specifies that updates by the sc instruction use
- * the coherency mode specified by the TLB; 1 means cachable
+ * the coherency mode specified by the TLB; 1 means cacheable
* coherent update on write will be used. Not all processors have
* this bit and; some wire it to zero, others like Toshiba had the
* silly idea of putting something else there ...
diff --git a/arch/mips/mm/cex-gen.S b/arch/mips/mm/cex-gen.S
index 45dff5cd4b8e..e528583d1331 100644
--- a/arch/mips/mm/cex-gen.S
+++ b/arch/mips/mm/cex-gen.S
@@ -25,7 +25,7 @@
* This is a very bad place to be. Our cache error
* detection has triggered. If we have write-back data
* in the cache, we may not be able to recover. As a
- * first-order desperate measure, turn off KSEG0 cacheing.
+ * first-order desperate measure, turn off KSEG0 caching.
*/
mfc0 k0,CP0_CONFIG
li k1,~CONF_CM_CMASK
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 53dfa2b9316b..22a8f488ae1d 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -183,7 +183,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
int idx, pid;
/*
- * Handle debugger faulting in for debugee.
+ * Handle debugger faulting in for debuggee.
*/
if (current->active_mm != vma->vm_mm)
return;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 93c2d695588a..128a0a5ec2b7 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -301,7 +301,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
int idx, pid;
/*
- * Handle debugger faulting in for debugee.
+ * Handle debugger faulting in for debuggee.
*/
if (current->active_mm != vma->vm_mm)
return;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index b4e1c783e617..4017fa0e2f68 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -789,7 +789,7 @@ void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
if (check_for_high_segbits) {
/*
- * The kernel currently implicitely assumes that the
+ * The kernel currently implicitly assumes that the
* MIPS SEGBITS parameter for the processor is
* (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
* allocate virtual addresses outside the maximum
@@ -1715,7 +1715,7 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
/*
* Check if PTE is present, if not then jump to LABEL. PTR points to
* the page table where this PTE is located, PTE will be re-loaded
- * with it's original value.
+ * with its original value.
*/
static void
build_pte_present(u32 **p, struct uasm_reloc **r,
diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c
index ace5db3fbd17..40a878b672f5 100644
--- a/arch/mips/net/bpf_jit_comp32.c
+++ b/arch/mips/net/bpf_jit_comp32.c
@@ -95,7 +95,7 @@
/*
* Mapping of 64-bit eBPF registers to 32-bit native MIPS registers.
*
- * 1) Native register pairs are ordered according to CPU endiannes, following
+ * 1) Native register pairs are ordered according to CPU endianness, following
* the MIPS convention for passing 64-bit arguments and return values.
* 2) The eBPF return value, arguments and callee-saved registers are mapped
* to their native MIPS equivalents.
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index 0d1b36ba1c21..068113f5c49d 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -49,7 +49,7 @@ static int loongson_pcibios_config_access(unsigned char access_type,
*/
#ifdef CONFIG_CS5536
/* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
- * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
+ * access the registers PCI_MSR_ADDR, PCI_MSR_DATA_LO,
* PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
* will not go this branch, but the others. so, no calling dead
* loop here.
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 1c722dd0c130..58625d1b6465 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -453,7 +453,7 @@ static int alchemy_pci_probe(struct platform_device *pdev)
/* we can't ioremap the entire pci config space because it's too large,
* nor can we dynamically ioremap it because some drivers use the
- * PCI config routines from within atomic contex and that becomes a
+ * PCI config routines from within atomic context and that becomes a
* problem in get_vm_area(). Instead we use one wired TLB entry to
* handle all config accesses for all busses.
*/
diff --git a/arch/mips/pci/pci-ar2315.c b/arch/mips/pci/pci-ar2315.c
index e17d862cfa4c..a925842ee125 100644
--- a/arch/mips/pci/pci-ar2315.c
+++ b/arch/mips/pci/pci-ar2315.c
@@ -16,7 +16,7 @@
* the CFG_SEL bit in the PCI_MISC_CONFIG register.
*
* Devices on the bus can perform DMA requests via chip BAR1. PCI host
- * controller BARs are programmend as if an external device is programmed.
+ * controller BARs are programmed as if an external device is programmed.
* Which means that during configuration, IDSEL pin of the chip should be
* asserted.
*
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 80f7293166bb..68a8cefed420 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -152,7 +152,7 @@ static int ltq_pci_startup(struct platform_device *pdev)
temp_buffer &= ~0xf0000;
/* enable internal arbiter */
temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
- /* enable internal PCI master reqest */
+ /* enable internal PCI master request */
temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
/* enable EBU request */
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index d19d9d456309..36d12cea3512 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -376,7 +376,7 @@ static void octeon_pci_initialize(void)
ctl_status.s.timer = 1;
cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
- /* Deassert PCI reset and advertize PCX Host Mode Device Capability
+ /* Deassert PCI reset and advertise PCX Host Mode Device Capability
(64b) */
cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
cvmx_read_csr(CVMX_CIU_SOFT_PRST);
diff --git a/arch/mips/pci/pci-xtalk-bridge.c b/arch/mips/pci/pci-xtalk-bridge.c
index 68d5211afea8..45ddbaa6c123 100644
--- a/arch/mips/pci/pci-xtalk-bridge.c
+++ b/arch/mips/pci/pci-xtalk-bridge.c
@@ -114,7 +114,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
*
* The function is complicated by the ultimate brokenness of the IOC3 chip
* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
- * accesses and does only decode parts of it's address space.
+ * accesses and does only decode parts of its address space.
*/
static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *value)
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index c9edd3fb380d..2583e318e8c6 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -1037,7 +1037,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
in_fif_p_count = dbg_data.s.data & 0xff;
} while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
- /* Update in_fif_p_count for it's offset with respect to out_p_count */
+ /* Update in_fif_p_count for its offset with respect to out_p_count */
in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
/* Read the OUT_P_COUNT from the debug select */
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 137781d0bd0a..5a9fd3fe41d7 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -175,7 +175,7 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
* mips_cm_probe() wipes out bootloader
* config for CM regions and we have to configure them
* again. This SoC cannot talk to pamlbus devices
- * witout proper iocu region set up.
+ * without proper iocu region set up.
*
* FIXME: it would be better to do this with values
* from DT, but we need this very early because
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 5ae30b78d38d..d9249f5a632e 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -348,7 +348,7 @@ static void final_fixup(struct pci_dev *dev)
unsigned char bist;
int ret;
- /* Do build-in self test */
+ /* Do built-in self test */
ret = pci_read_config_byte(dev, PCI_BIST, &bist);
if ((ret != PCIBIOS_SUCCESSFUL) || !(bist & PCI_BIST_CAPABLE))
return;
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/sparc". Only touches
comments, no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: [email protected]
---
arch/sparc/include/asm/hypervisor.h | 6 +++---
arch/sparc/include/asm/ldc.h | 2 +-
arch/sparc/include/asm/mmu_context_64.h | 4 ++--
arch/sparc/include/asm/switch_to_64.h | 2 +-
arch/sparc/kernel/irq_64.c | 2 +-
arch/sparc/kernel/kprobes.c | 2 +-
arch/sparc/kernel/ldc.c | 2 +-
arch/sparc/kernel/leon_pci_grpci2.c | 2 +-
arch/sparc/kernel/of_device_64.c | 2 +-
arch/sparc/kernel/pci.c | 2 +-
arch/sparc/kernel/pci_impl.h | 4 ++--
arch/sparc/kernel/pci_schizo.c | 4 ++--
arch/sparc/kernel/perf_event.c | 2 +-
arch/sparc/kernel/prom_irqtrans.c | 2 +-
arch/sparc/kernel/psycho_common.c | 2 +-
arch/sparc/kernel/signal_32.c | 2 +-
arch/sparc/kernel/signal_64.c | 2 +-
arch/sparc/mm/srmmu.c | 2 +-
arch/sparc/mm/tsb.c | 2 +-
arch/sparc/net/bpf_jit_comp_32.c | 6 +++---
20 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h
index 08650d503cc2..f220edcf17c7 100644
--- a/arch/sparc/include/asm/hypervisor.h
+++ b/arch/sparc/include/asm/hypervisor.h
@@ -430,7 +430,7 @@ unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count,
* ERRORS: No errors defined.
*
* Return the hypervisor ID handle for the current CPU. Use by a
- * virtual CPU to discover it's own identity.
+ * virtual CPU to discover its own identity.
*/
#define HV_FAST_CPU_MYID 0x16
@@ -1221,7 +1221,7 @@ unsigned long sun4v_con_write(unsigned long buffer,
* EBADALIGNED software state description is not correctly
* aligned
*
- * This allows the guest to report it's soft state to the hypervisor. There
+ * This allows the guest to report its soft state to the hypervisor. There
* are two primary components to this state. The first part states whether
* the guest software is running or not. The second containts optional
* details specific to the software.
@@ -1502,7 +1502,7 @@ struct hv_trap_trace_entry {
* configuration error of some sort.
*
* The dump services provide an opaque buffer into which the
- * hypervisor can place it's internal state in order to assist in
+ * hypervisor can place its internal state in order to assist in
* debugging such situations. The contents are opaque and extremely
* platform and hypervisor implementation specific. The guest, during
* a core dump, requests that the hypervisor update any information in
diff --git a/arch/sparc/include/asm/ldc.h b/arch/sparc/include/asm/ldc.h
index ca973955ca86..4294738d40be 100644
--- a/arch/sparc/include/asm/ldc.h
+++ b/arch/sparc/include/asm/ldc.h
@@ -13,7 +13,7 @@ void ldom_power_off(void);
* or data becomes available on the receive side.
*
* For non-RAW links, if the LDC_EVENT_RESET event arrives the
- * driver should reset all of it's internal state and reinvoke
+ * driver should reset all of its internal state and reinvoke
* ldc_connect() to try and bring the link up again.
*
* For RAW links, ldc_connect() is not used. Instead the driver
diff --git a/arch/sparc/include/asm/mmu_context_64.h b/arch/sparc/include/asm/mmu_context_64.h
index 799e797c5cdd..08160bf9a0f4 100644
--- a/arch/sparc/include/asm/mmu_context_64.h
+++ b/arch/sparc/include/asm/mmu_context_64.h
@@ -93,7 +93,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str
/* We have to be extremely careful here or else we will miss
* a TSB grow if we switch back and forth between a kernel
- * thread and an address space which has it's TSB size increased
+ * thread and an address space which has its TSB size increased
* on another processor.
*
* It is possible to play some games in order to optimize the
@@ -118,7 +118,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str
*
* At that point cpu0 continues to use a stale TSB, the one from
* before the TSB grow performed on cpu1. cpu1 did not cross-call
- * cpu0 to update it's TSB because at that point the cpu_vm_mask
+ * cpu0 to update its TSB because at that point the cpu_vm_mask
* only had cpu1 set in it.
*/
tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
diff --git a/arch/sparc/include/asm/switch_to_64.h b/arch/sparc/include/asm/switch_to_64.h
index 14f3c49bfdbc..d93963ff7caa 100644
--- a/arch/sparc/include/asm/switch_to_64.h
+++ b/arch/sparc/include/asm/switch_to_64.h
@@ -15,7 +15,7 @@ do { \
* for l0/l1. It will use one for 'next' and the other to hold
* the output value of 'last'. 'next' is not referenced again
* past the invocation of switch_to in the scheduler, so we need
- * not preserve it's value. Hairy, but it lets us remove 2 loads
+ * not preserve its value. Hairy, but it lets us remove 2 loads
* and 2 stores in this critical code path. -DaveM
*/
#define switch_to(prev, next, last) \
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c
index 72da2e10e255..5280e325d4d6 100644
--- a/arch/sparc/kernel/irq_64.c
+++ b/arch/sparc/kernel/irq_64.c
@@ -980,7 +980,7 @@ void notrace init_irqwork_curcpu(void)
*
* On SMP this gets invoked from the CPU trampoline before
* the cpu has fully taken over the trap table from OBP,
- * and it's kernel stack + %g6 thread register state is
+ * and its kernel stack + %g6 thread register state is
* not fully cooked yet.
*
* Therefore you cannot make any OBP calls, not even prom_printf,
diff --git a/arch/sparc/kernel/kprobes.c b/arch/sparc/kernel/kprobes.c
index 535c7b35cb59..191bbaca9921 100644
--- a/arch/sparc/kernel/kprobes.c
+++ b/arch/sparc/kernel/kprobes.c
@@ -230,7 +230,7 @@ static unsigned long __kprobes relbranch_fixup(u32 insn, struct kprobe *p,
return regs->tnpc;
}
-/* If INSN is an instruction which writes it's PC location
+/* If INSN is an instruction which writes its PC location
* into a destination register, fix that up.
*/
static void __kprobes retpc_fixup(struct pt_regs *regs, u32 insn,
diff --git a/arch/sparc/kernel/ldc.c b/arch/sparc/kernel/ldc.c
index c0fa3ef6cf01..7f3cdb6f644d 100644
--- a/arch/sparc/kernel/ldc.c
+++ b/arch/sparc/kernel/ldc.c
@@ -1854,7 +1854,7 @@ static int read_nonraw(struct ldc_channel *lp, void *buf, unsigned int size)
* This seems the best behavior because this allows
* a user of the LDC layer to start with a small
* RX buffer for ldc_read() calls and use -EMSGSIZE
- * as a cue to enlarge it's read buffer.
+ * as a cue to enlarge its read buffer.
*/
err = -EMSGSIZE;
break;
diff --git a/arch/sparc/kernel/leon_pci_grpci2.c b/arch/sparc/kernel/leon_pci_grpci2.c
index 60b6bdf7761f..282b49d496ea 100644
--- a/arch/sparc/kernel/leon_pci_grpci2.c
+++ b/arch/sparc/kernel/leon_pci_grpci2.c
@@ -586,7 +586,7 @@ static void grpci2_hw_init(struct grpci2_priv *priv)
REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
- * Each AHB master has it's own mapping registers. Max 16 AHB masters.
+ * Each AHB master has its own mapping registers. Max 16 AHB masters.
*/
for (i = 0; i < 16; i++)
REGSTORE(regs->ahbmst_map[i], priv->pci_area);
diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c
index d3842821a5a0..c350c58c7f69 100644
--- a/arch/sparc/kernel/of_device_64.c
+++ b/arch/sparc/kernel/of_device_64.c
@@ -560,7 +560,7 @@ static unsigned int __init build_one_device_irq(struct platform_device *op,
*
* If we hit a bus type or situation we cannot handle, we
* stop and assume that the original IRQ number was in a
- * format which has special meaning to it's immediate parent.
+ * format which has special meaning to its immediate parent.
*/
pp = dp->parent;
ip = NULL;
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index f66005ce4cb5..50a0927a84a6 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -311,7 +311,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
/* We can't actually use the firmware value, we have
* to read what is in the register right now. One
* reason is that in the case of IDE interfaces the
- * firmware can sample the value before the the IDE
+ * firmware can sample the value before the IDE
* interface is programmed into native mode.
*/
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
diff --git a/arch/sparc/kernel/pci_impl.h b/arch/sparc/kernel/pci_impl.h
index f31761f51757..83718876f1d4 100644
--- a/arch/sparc/kernel/pci_impl.h
+++ b/arch/sparc/kernel/pci_impl.h
@@ -19,9 +19,9 @@
* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
* underneath. Each PCI bus module uses an IOMMU (shared by both
* PBMs of a controller, or per-PBM), and if a streaming buffer
- * is present, each PCI bus module has it's own. (ie. the IOMMU
+ * is present, each PCI bus module has its own. (ie. the IOMMU
* might be shared between PBMs, the STC is never shared)
- * Furthermore, each PCI bus module controls it's own autonomous
+ * Furthermore, each PCI bus module controls its own autonomous
* PCI bus.
*/
diff --git a/arch/sparc/kernel/pci_schizo.c b/arch/sparc/kernel/pci_schizo.c
index 23b47f7fdb1d..4104007a0256 100644
--- a/arch/sparc/kernel/pci_schizo.c
+++ b/arch/sparc/kernel/pci_schizo.c
@@ -142,7 +142,7 @@ static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
/* This is __REALLY__ dangerous. When we put the
* streaming buffer into diagnostic mode to probe
- * it's tags and error status, we _must_ clear all
+ * its tags and error status, we _must_ clear all
* of the line tag valid bits before re-enabling
* the streaming buffer. If any dirty data lives
* in the STC when we do this, we will end up
@@ -272,7 +272,7 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
pbm->name, type_string);
/* Put the IOMMU into diagnostic mode and probe
- * it's TLB for entries with error status.
+ * its TLB for entries with error status.
*
* It is very possible for another DVMA to occur
* while we do this probe, and corrupt the system
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index a58ae9c42803..f02a283a8e8f 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -979,7 +979,7 @@ static void calculate_single_pcr(struct cpu_hw_events *cpuc)
static void sparc_pmu_start(struct perf_event *event, int flags);
-/* On this PMU each PIC has it's own PCR control register. */
+/* On this PMU each PIC has its own PCR control register. */
static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
{
int i;
diff --git a/arch/sparc/kernel/prom_irqtrans.c b/arch/sparc/kernel/prom_irqtrans.c
index 426bd08cb2ab..5752bfd73ac0 100644
--- a/arch/sparc/kernel/prom_irqtrans.c
+++ b/arch/sparc/kernel/prom_irqtrans.c
@@ -394,7 +394,7 @@ static unsigned int schizo_irq_build(struct device_node *dp,
iclr = schizo_ino_to_iclr(pbm_regs, ino);
/* On Schizo, no inofixup occurs. This is because each
- * INO has it's own IMAP register. On Psycho and Sabre
+ * INO has its own IMAP register. On Psycho and Sabre
* there is only one IMAP register for each PCI slot even
* though four different INOs can be generated by each
* PCI slot.
diff --git a/arch/sparc/kernel/psycho_common.c b/arch/sparc/kernel/psycho_common.c
index 5ee74b4c0cf4..4557ef18f371 100644
--- a/arch/sparc/kernel/psycho_common.c
+++ b/arch/sparc/kernel/psycho_common.c
@@ -50,7 +50,7 @@ static void psycho_check_stc_error(struct pci_pbm_info *pbm)
spin_lock(&stc_buf_lock);
/* This is __REALLY__ dangerous. When we put the streaming
- * buffer into diagnostic mode to probe it's tags and error
+ * buffer into diagnostic mode to probe its tags and error
* status, we _must_ clear all of the line tag valid bits
* before re-enabling the streaming buffer. If any dirty data
* lives in the STC when we do this, we will end up
diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c
index 89b93c7136e7..478014d2e59b 100644
--- a/arch/sparc/kernel/signal_32.c
+++ b/arch/sparc/kernel/signal_32.c
@@ -473,7 +473,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
*
* %g7 is used as the "thread register". %g6 is not used in
* any fixed manner. %g6 is used as a scratch register and
- * a compiler temporary, but it's value is never used across
+ * a compiler temporary, but its value is never used across
* a system call. Therefore %g6 is usable for orig_i0 storage.
*/
if (pt_regs_is_syscall(regs) && (regs->psr & PSR_C))
diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c
index b4e410976e0d..2d64566a1f88 100644
--- a/arch/sparc/kernel/signal_64.c
+++ b/arch/sparc/kernel/signal_64.c
@@ -494,7 +494,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
*
* %g7 is used as the "thread register". %g6 is not used in
* any fixed manner. %g6 is used as a scratch register and
- * a compiler temporary, but it's value is never used across
+ * a compiler temporary, but its value is never used across
* a system call. Therefore %g6 is usable for orig_i0 storage.
*/
if (pt_regs_is_syscall(regs) &&
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 8393faa3e596..852085ada368 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -1513,7 +1513,7 @@ static void __init init_viking(void)
/*
* We need this to make sure old viking takes no hits
- * on it's cache for dma snoops to workaround the
+ * on its cache for dma snoops to workaround the
* "load from non-cacheable memory" interrupt bug.
* This is only necessary because of the new way in
* which we use the IOMMU.
diff --git a/arch/sparc/mm/tsb.c b/arch/sparc/mm/tsb.c
index 5e2931a18409..5351d4128e74 100644
--- a/arch/sparc/mm/tsb.c
+++ b/arch/sparc/mm/tsb.c
@@ -385,7 +385,7 @@ static unsigned long tsb_size_to_rss_limit(unsigned long new_size)
* will not trigger any longer.
*
* The TSB can be anywhere from 8K to 1MB in size, in increasing powers
- * of two. The TSB must be aligned to it's size, so f.e. a 512K TSB
+ * of two. The TSB must be aligned to its size, so f.e. a 512K TSB
* must be 512K aligned. It also must be physically contiguous, so we
* cannot use vmalloc().
*
diff --git a/arch/sparc/net/bpf_jit_comp_32.c b/arch/sparc/net/bpf_jit_comp_32.c
index a74e5004c6c8..da2df1e84ed4 100644
--- a/arch/sparc/net/bpf_jit_comp_32.c
+++ b/arch/sparc/net/bpf_jit_comp_32.c
@@ -300,7 +300,7 @@ do { *prog++ = BR_OPC | WDISP22(OFF); \
*
* The most common case is to emit a branch at the end of such
* a code sequence. So this would be two instructions, the
- * branch and it's delay slot.
+ * branch and its delay slot.
*
* Therefore by default the branch emitters calculate the branch
* offset field as:
@@ -309,13 +309,13 @@ do { *prog++ = BR_OPC | WDISP22(OFF); \
*
* This "addrs[i] - 8" is the address of the branch itself or
* what "." would be in assembler notation. The "8" part is
- * how we take into consideration the branch and it's delay
+ * how we take into consideration the branch and its delay
* slot mentioned above.
*
* Sometimes we need to emit a branch earlier in the code
* sequence. And in these situations we adjust "destination"
* to accommodate this difference. For example, if we needed
- * to emit a branch (and it's delay slot) right before the
+ * to emit a branch (and its delay slot) right before the
* final instruction emitted for a BPF opcode, we'd use
* "destination + 4" instead of just plain "destination" above.
*
--
2.34.1
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/powerpc". Only touches
comments, no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: Nicholas Piggin <[email protected]>
Cc: Christophe Leroy <[email protected]>
Cc: [email protected]
---
arch/powerpc/boot/Makefile | 4 ++--
arch/powerpc/boot/dts/acadia.dts | 2 +-
arch/powerpc/boot/main.c | 2 +-
arch/powerpc/boot/ps3.c | 2 +-
arch/powerpc/include/asm/io.h | 2 +-
arch/powerpc/include/asm/opal-api.h | 4 ++--
arch/powerpc/include/asm/pmac_feature.h | 2 +-
arch/powerpc/include/asm/uninorth.h | 2 +-
arch/powerpc/include/uapi/asm/bootx.h | 2 +-
arch/powerpc/kernel/eeh_pe.c | 2 +-
arch/powerpc/kernel/fadump.c | 2 +-
arch/powerpc/kernel/misc_64.S | 4 ++--
arch/powerpc/kernel/process.c | 12 ++++++------
arch/powerpc/kernel/ptrace/ptrace-tm.c | 2 +-
arch/powerpc/kernel/smp.c | 2 +-
arch/powerpc/kernel/sysfs.c | 4 ++--
arch/powerpc/kvm/book3s_xive.c | 2 +-
arch/powerpc/mm/cacheflush.c | 2 +-
arch/powerpc/mm/nohash/kaslr_booke.c | 2 +-
arch/powerpc/platforms/512x/mpc512x_shared.c | 2 +-
arch/powerpc/platforms/cell/spufs/sched.c | 2 +-
arch/powerpc/platforms/maple/pci.c | 2 +-
arch/powerpc/platforms/powermac/pic.c | 2 +-
arch/powerpc/platforms/powermac/sleep.S | 2 +-
arch/powerpc/platforms/powernv/pci-sriov.c | 4 ++--
arch/powerpc/platforms/powernv/vas-window.c | 2 +-
arch/powerpc/platforms/pseries/vas.c | 2 +-
arch/powerpc/sysdev/xive/common.c | 4 ++--
arch/powerpc/sysdev/xive/native.c | 2 +-
29 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 968aee2025b8..9c2b6e527ed1 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -108,8 +108,8 @@ DTC_FLAGS ?= -p 1024
# these files into the build dir, fix up any includes and ensure that dependent
# files are copied in the right order.
-# these need to be seperate variables because they are copied out of different
-# directories in the kernel tree. Sure you COULd merge them, but it's a
+# these need to be separate variables because they are copied out of different
+# directories in the kernel tree. Sure you COULD merge them, but it's a
# cure-is-worse-than-disease situation.
zlib-decomp-$(CONFIG_KERNEL_GZIP) := decompress_inflate.c
zlib-$(CONFIG_KERNEL_GZIP) := inffast.c inflate.c inftrees.c
diff --git a/arch/powerpc/boot/dts/acadia.dts b/arch/powerpc/boot/dts/acadia.dts
index deb52e41ab84..5fedda811378 100644
--- a/arch/powerpc/boot/dts/acadia.dts
+++ b/arch/powerpc/boot/dts/acadia.dts
@@ -172,7 +172,7 @@ ieee1588@ef602800 {
reg = <0xef602800 0x60>;
interrupt-parent = <&UIC0>;
interrupts = <0x4 0x4>;
- /* This thing is a bit weird. It has it's own UIC
+ /* This thing is a bit weird. It has its own UIC
* that it uses to generate snapshot triggers. We
* don't really support this device yet, and it needs
* work to figure this out.
diff --git a/arch/powerpc/boot/main.c b/arch/powerpc/boot/main.c
index cae31a6e8f02..2c0e2a1cab01 100644
--- a/arch/powerpc/boot/main.c
+++ b/arch/powerpc/boot/main.c
@@ -188,7 +188,7 @@ static inline void prep_esm_blob(struct addr_range vmlinux, void *chosen) { }
/* A buffer that may be edited by tools operating on a zImage binary so as to
* edit the command line passed to vmlinux (by setting /chosen/bootargs).
- * The buffer is put in it's own section so that tools may locate it easier.
+ * The buffer is put in its own section so that tools may locate it easier.
*/
static char cmdline[BOOT_COMMAND_LINE_SIZE]
__attribute__((__section__("__builtin_cmdline")));
diff --git a/arch/powerpc/boot/ps3.c b/arch/powerpc/boot/ps3.c
index f157717ae814..89ff46b8b225 100644
--- a/arch/powerpc/boot/ps3.c
+++ b/arch/powerpc/boot/ps3.c
@@ -25,7 +25,7 @@ BSS_STACK(4096);
/* A buffer that may be edited by tools operating on a zImage binary so as to
* edit the command line passed to vmlinux (by setting /chosen/bootargs).
- * The buffer is put in it's own section so that tools may locate it easier.
+ * The buffer is put in its own section so that tools may locate it easier.
*/
static char cmdline[BOOT_COMMAND_LINE_SIZE]
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 5220274a6277..7fb001ab3109 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -989,7 +989,7 @@ static inline phys_addr_t page_to_phys(struct page *page)
}
/*
- * 32 bits still uses virt_to_bus() for it's implementation of DMA
+ * 32 bits still uses virt_to_bus() for its implementation of DMA
* mappings se we have to keep it defined here. We also have some old
* drivers (shame shame shame) that use bus_to_virt() and haven't been
* fixed yet so I need to define it here.
diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index a2bc4b95e703..8c9d4b26bf57 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -1027,10 +1027,10 @@ struct opal_i2c_request {
* The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
* with individual elements being 16 bits wide to fetch the system
* wide EPOW status. Each element in the buffer will contain the
- * EPOW status in it's bit representation for a particular EPOW sub
+ * EPOW status in its bit representation for a particular EPOW sub
* class as defined here. So multiple detailed EPOW status bits
* specific for any sub class can be represented in a single buffer
- * element as it's bit representation.
+ * element as its bit representation.
*/
/* System EPOW type */
diff --git a/arch/powerpc/include/asm/pmac_feature.h b/arch/powerpc/include/asm/pmac_feature.h
index 2495866f2e97..420e2878ae67 100644
--- a/arch/powerpc/include/asm/pmac_feature.h
+++ b/arch/powerpc/include/asm/pmac_feature.h
@@ -192,7 +192,7 @@ static inline long pmac_call_feature(int selector, struct device_node* node,
/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value)
* enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
- * it's reset line
+ * its reset line
*/
#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6)
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
index e278299b9b37..6949b5daa37d 100644
--- a/arch/powerpc/include/asm/uninorth.h
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -144,7 +144,7 @@
#define UNI_N_HWINIT_STATE_SLEEPING 0x01
#define UNI_N_HWINIT_STATE_RUNNING 0x02
/* This last bit appear to be used by the bootROM to know the second
- * CPU has started and will enter it's sleep loop with IP=0
+ * CPU has started and will enter its sleep loop with IP=0
*/
#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
diff --git a/arch/powerpc/include/uapi/asm/bootx.h b/arch/powerpc/include/uapi/asm/bootx.h
index 6728c7e24e58..1b8c121071d9 100644
--- a/arch/powerpc/include/uapi/asm/bootx.h
+++ b/arch/powerpc/include/uapi/asm/bootx.h
@@ -108,7 +108,7 @@ typedef struct boot_infos
/* ALL BELOW NEW (vers. 4) */
/* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
- (non-PCI) only. On PCI, memory is contiguous and it's size is in the
+ (non-PCI) only. On PCI, memory is contiguous and its size is in the
device-tree. */
boot_info_map_entry_t
physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index e0ce81279624..95164511fd12 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -527,7 +527,7 @@ EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
* eeh_pe_mark_isolated
* @pe: EEH PE
*
- * Record that a PE has been isolated by marking the PE and it's children as
+ * Record that a PE has been isolated by marking the PE and its children as
* EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices
* as pci_channel_io_frozen.
*/
diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
index d14eda1e8589..81c3229a6013 100644
--- a/arch/powerpc/kernel/fadump.c
+++ b/arch/powerpc/kernel/fadump.c
@@ -705,7 +705,7 @@ void crash_fadump(struct pt_regs *regs, const char *str)
* old_cpu == -1 means this is the first CPU which has come here,
* go ahead and trigger fadump.
*
- * old_cpu != -1 means some other CPU has already on it's way
+ * old_cpu != -1 means some other CPU has already on its way
* to trigger fadump, just keep looping here.
*/
this_cpu = smp_processor_id();
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 1a8cdafd68e8..91123e102db4 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -192,7 +192,7 @@ _GLOBAL(scom970_read)
xori r0,r0,MSR_EE
mtmsrd r0,1
- /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
+ /* rotate 24 bits SCOM address 8 bits left and mask out its low 8 bits
* (including parity). On current CPUs they must be 0'd,
* and finally or in RW bit
*/
@@ -226,7 +226,7 @@ _GLOBAL(scom970_write)
xori r0,r0,MSR_EE
mtmsrd r0,1
- /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
+ /* rotate 24 bits SCOM address 8 bits left and mask out its low 8 bits
* (including parity). On current CPUs they must be 0'd.
*/
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 392404688cec..3e738be554a4 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1647,7 +1647,7 @@ void arch_setup_new_exec(void)
* cases will happen:
*
* 1. The correct thread is running, the wrong thread is not
- * In this situation, the correct thread is woken and proceeds to pass it's
+ * In this situation, the correct thread is woken and proceeds to pass its
* condition check.
*
* 2. Neither threads are running
@@ -1657,15 +1657,15 @@ void arch_setup_new_exec(void)
* for the wrong thread, or they will execute the condition check immediately.
*
* 3. The wrong thread is running, the correct thread is not
- * The wrong thread will be woken, but will fail it's condition check and
+ * The wrong thread will be woken, but will fail its condition check and
* re-execute wait. The correct thread, when scheduled, will execute either
- * it's condition check (which will pass), or wait, which returns immediately
- * when called the first time after the thread is scheduled, followed by it's
+ * its condition check (which will pass), or wait, which returns immediately
+ * when called the first time after the thread is scheduled, followed by its
* condition check (which will pass).
*
* 4. Both threads are running
- * Both threads will be woken. The wrong thread will fail it's condition check
- * and execute another wait, while the correct thread will pass it's condition
+ * Both threads will be woken. The wrong thread will fail its condition check
+ * and execute another wait, while the correct thread will pass its condition
* check.
*
* @t: the task to set the thread ID for
diff --git a/arch/powerpc/kernel/ptrace/ptrace-tm.c b/arch/powerpc/kernel/ptrace/ptrace-tm.c
index 210ea834e603..447bff87fd21 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-tm.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-tm.c
@@ -12,7 +12,7 @@ void flush_tmregs_to_thread(struct task_struct *tsk)
{
/*
* If task is not current, it will have been flushed already to
- * it's thread_struct during __switch_to().
+ * its thread_struct during __switch_to().
*
* A reclaim flushes ALL the state or if not in TM save TM SPRs
* in the appropriate thread structures from live.
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index ab691c89d787..4e0c62897405 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -1564,7 +1564,7 @@ static void add_cpu_to_masks(int cpu)
/*
* This CPU will not be in the online mask yet so we need to manually
- * add it to it's own thread sibling mask.
+ * add it to its own thread sibling mask.
*/
map_cpu_to_node(cpu, cpu_to_node(cpu));
cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 0f39a6b84132..b842c83ab497 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -139,7 +139,7 @@ static unsigned long dscr_default;
* @val: Returned cpu specific DSCR default value
*
* This function returns the per cpu DSCR default value
- * for any cpu which is contained in it's PACA structure.
+ * for any cpu which is contained in its PACA structure.
*/
static void read_dscr(void *val)
{
@@ -152,7 +152,7 @@ static void read_dscr(void *val)
* @val: New cpu specific DSCR default value to update
*
* This function updates the per cpu DSCR default value
- * for any cpu which is contained in it's PACA structure.
+ * for any cpu which is contained in its PACA structure.
*/
static void write_dscr(void *val)
{
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index 29a382249770..1362c672387e 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -531,7 +531,7 @@ static int xive_vm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
xc->cppr = xive_prio_from_guest(new_cppr);
/*
- * IPIs are synthetized from MFRR and thus don't need
+ * IPIs are synthesized from MFRR and thus don't need
* any special EOI handling. The underlying interrupt
* used to signal MFRR changes is EOId when fetched from
* the queue.
diff --git a/arch/powerpc/mm/cacheflush.c b/arch/powerpc/mm/cacheflush.c
index 15189592da09..7186516eca52 100644
--- a/arch/powerpc/mm/cacheflush.c
+++ b/arch/powerpc/mm/cacheflush.c
@@ -78,7 +78,7 @@ EXPORT_SYMBOL(flush_icache_range);
#ifdef CONFIG_HIGHMEM
/**
- * flush_dcache_icache_phys() - Flush a page by it's physical address
+ * flush_dcache_icache_phys() - Flush a page by its physical address
* @physaddr: the physical address of the page
*/
static void flush_dcache_icache_phys(unsigned long physaddr)
diff --git a/arch/powerpc/mm/nohash/kaslr_booke.c b/arch/powerpc/mm/nohash/kaslr_booke.c
index b4f2786a7d2b..7ac97a28c1b3 100644
--- a/arch/powerpc/mm/nohash/kaslr_booke.c
+++ b/arch/powerpc/mm/nohash/kaslr_booke.c
@@ -376,7 +376,7 @@ notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
create_kaslr_tlb_entry(1, tlb_virt, tlb_phys);
}
- /* Copy the kernel to it's new location and run */
+ /* Copy the kernel to its new location and run */
memcpy((void *)kernstart_virt_addr, (void *)_stext, kernel_sz);
flush_icache_range(kernstart_virt_addr, kernstart_virt_addr + kernel_sz);
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 8f75e9574c27..8c1f3b629fc7 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -279,7 +279,7 @@ static void __init mpc512x_setup_diu(void)
* and so negatively affect boot time. Instead we reserve the
* already configured frame buffer area so that it won't be
* destroyed. The starting address of the area to reserve and
- * also it's length is passed to memblock_reserve(). It will be
+ * also its length is passed to memblock_reserve(). It will be
* freed later on first open of fbdev, when splash image is not
* needed any more.
*/
diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c
index 99bd027a7f7c..610ca8570682 100644
--- a/arch/powerpc/platforms/cell/spufs/sched.c
+++ b/arch/powerpc/platforms/cell/spufs/sched.c
@@ -868,7 +868,7 @@ static int __spu_deactivate(struct spu_context *ctx, int force, int max_prio)
}
/**
- * spu_deactivate - unbind a context from it's physical spu
+ * spu_deactivate - unbind a context from its physical spu
* @ctx: spu context to unbind
*
* Unbind @ctx from the physical spu it is running on and schedule
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index b911b31717cc..b9ff37c7f6f0 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -595,7 +595,7 @@ void __init maple_pci_init(void)
/* Probe root PCI hosts, that is on U3 the AGP host and the
* HyperTransport host. That one is actually "kept" around
- * and actually added last as it's resource management relies
+ * and actually added last as its resource management relies
* on the AGP resources to have been setup first
*/
root = of_find_node_by_path("/");
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 7135ea1d7db6..2202bf77c7a3 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -2,7 +2,7 @@
/*
* Support for the interrupt controllers found on Power Macintosh,
* currently Apple's "Grand Central" interrupt controller in all
- * it's incarnations. OpenPIC support used on newer machines is
+ * its incarnations. OpenPIC support used on newer machines is
* in a separate file
*
* Copyright (C) 1997 Paul Mackerras ([email protected])
diff --git a/arch/powerpc/platforms/powermac/sleep.S b/arch/powerpc/platforms/powermac/sleep.S
index d497a60003d2..822ed70cdcbf 100644
--- a/arch/powerpc/platforms/powermac/sleep.S
+++ b/arch/powerpc/platforms/powermac/sleep.S
@@ -176,7 +176,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
* memory location containing the PC to resume from
* at address 0.
* - On Core99, we must store the wakeup vector at
- * address 0x80 and eventually it's parameters
+ * address 0x80 and eventually its parameters
* at address 0x84. I've have some trouble with those
* parameters however and I no longer use them.
*/
diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c
index 59882da3e742..cc7b1dd54ac6 100644
--- a/arch/powerpc/platforms/powernv/pci-sriov.c
+++ b/arch/powerpc/platforms/powernv/pci-sriov.c
@@ -238,7 +238,7 @@ void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
} else if (pdev->is_physfn) {
/*
* For PFs adjust their allocated IOV resources to match what
- * the PHB can support using it's M64 BAR table.
+ * the PHB can support using its M64 BAR table.
*/
pnv_pci_ioda_fixup_iov_resources(pdev);
}
@@ -658,7 +658,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
list_add_tail(&pe->list, &phb->ioda.pe_list);
mutex_unlock(&phb->ioda.pe_list_mutex);
- /* associate this pe to it's pdn */
+ /* associate this pe to its pdn */
list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
if (vf_pdn->busno == vf_bus &&
vf_pdn->devfn == vf_devfn) {
diff --git a/arch/powerpc/platforms/powernv/vas-window.c b/arch/powerpc/platforms/powernv/vas-window.c
index b664838008c1..5147df3a18ac 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -1059,7 +1059,7 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
}
} else {
/*
- * Interrupt hanlder or fault window setup failed. Means
+ * Interrupt handler or fault window setup failed. Means
* NX can not generate fault for page fault. So not
* opening for user space tx window.
*/
diff --git a/arch/powerpc/platforms/pseries/vas.c b/arch/powerpc/platforms/pseries/vas.c
index b1f25bac280b..d8a8c4ccf051 100644
--- a/arch/powerpc/platforms/pseries/vas.c
+++ b/arch/powerpc/platforms/pseries/vas.c
@@ -228,7 +228,7 @@ static irqreturn_t pseries_vas_irq_handler(int irq, void *data)
struct pseries_vas_window *txwin = data;
/*
- * The thread hanlder will process this interrupt if it is
+ * The thread handler will process this interrupt if it is
* already running.
*/
atomic_inc(&txwin->pending_faults);
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index a289cb97c1d7..fa01818c1972 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -383,7 +383,7 @@ static unsigned int xive_get_irq(void)
* CPU.
*
* If we find that there is indeed more in there, we call
- * force_external_irq_replay() to make Linux synthetize an
+ * force_external_irq_replay() to make Linux synthesize an
* external interrupt on the next call to local_irq_restore().
*/
static void xive_do_queue_eoi(struct xive_cpu *xc)
@@ -874,7 +874,7 @@ static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
*
* This also tells us that it's in flight to a host queue
* or has already been fetched but hasn't been EOIed yet
- * by the host. This it's potentially using up a host
+ * by the host. Thus it's potentially using up a host
* queue slot. This is important to know because as long
* as this is the case, we must not hard-unmask it when
* "returning" that interrupt to the host.
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index f1c0fa6ece21..517b963e3e6a 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -415,7 +415,7 @@ static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
return;
}
- /* Grab it's CAM value */
+ /* Grab its CAM value */
rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
if (rc) {
pr_err("Failed to get pool VP info CPU %d\n", cpu);
--
2.34.1
On 1/3/24 15:15, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/alpha". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: Ivan Kokshaysky <[email protected]>
> Cc: Matt Turner <[email protected]>
> Cc: [email protected]
> ---
> arch/alpha/boot/bootpz.c | 4 ++--
> arch/alpha/include/asm/core_marvel.h | 2 +-
> arch/alpha/include/asm/fpu.h | 2 +-
> arch/alpha/include/asm/sfp-machine.h | 2 +-
> arch/alpha/include/asm/thread_info.h | 2 +-
> arch/alpha/include/asm/wrperfmon.h | 2 +-
> arch/alpha/include/uapi/asm/mman.h | 2 +-
> arch/alpha/kernel/err_impl.h | 2 +-
> arch/alpha/kernel/irq_i8259.c | 2 +-
> arch/alpha/kernel/osf_sys.c | 2 +-
> arch/alpha/kernel/pci_iommu.c | 4 ++--
> arch/alpha/kernel/sys_eiger.c | 4 ++--
> arch/alpha/kernel/sys_marvel.c | 2 +-
> arch/alpha/kernel/sys_miata.c | 2 +-
> arch/alpha/kernel/sys_takara.c | 2 +-
> arch/alpha/lib/ev6-memcpy.S | 2 +-
> arch/alpha/lib/ev6-stxcpy.S | 2 +-
> arch/alpha/lib/ev67-strrchr.S | 2 +-
> arch/alpha/lib/strrchr.S | 2 +-
> arch/alpha/lib/stxcpy.S | 2 +-
> 20 files changed, 23 insertions(+), 23 deletions(-)
>
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On 1/3/24 15:15, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arc". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: [email protected]
> ---
> arch/arc/boot/Makefile | 4 ++--
> arch/arc/boot/dts/axc003.dtsi | 4 ++--
> arch/arc/boot/dts/vdk_axs10x_mb.dtsi | 2 +-
> arch/arc/include/asm/dsp.h | 2 +-
> arch/arc/include/asm/entry-compact.h | 10 +++++-----
> arch/arc/include/asm/entry.h | 4 ++--
> arch/arc/include/asm/irq.h | 2 +-
> arch/arc/include/asm/irqflags-compact.h | 2 +-
> arch/arc/include/asm/mmu_context.h | 2 +-
> arch/arc/include/asm/pgtable-bits-arcv2.h | 2 +-
> arch/arc/include/asm/shmparam.h | 2 +-
> arch/arc/include/asm/smp.h | 4 ++--
> arch/arc/include/asm/thread_info.h | 2 +-
> arch/arc/include/uapi/asm/swab.h | 2 +-
> arch/arc/kernel/entry-arcv2.S | 8 ++++----
> arch/arc/kernel/entry.S | 4 ++--
> arch/arc/kernel/head.S | 2 +-
> arch/arc/kernel/intc-arcv2.c | 2 +-
> arch/arc/kernel/perf_event.c | 2 +-
> arch/arc/kernel/setup.c | 2 +-
> arch/arc/kernel/signal.c | 2 +-
> arch/arc/kernel/traps.c | 2 +-
> arch/arc/kernel/vmlinux.lds.S | 4 ++--
> arch/arc/mm/tlbex.S | 8 ++++----
> 24 files changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h b/arch/arc/include/asm/pgtable-bits-arcv2.h
> index f3eea3f30b2e..f8f85c04d7a8 100644
> --- a/arch/arc/include/asm/pgtable-bits-arcv2.h
> +++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
> @@ -66,7 +66,7 @@
> * Other rules which cause the divergence from 1:1 mapping
> *
> * 1. Although ARC700 can do exclusive execute/write protection (meaning R
> - * can be tracked independet of X/W unlike some other CPUs), still to
> + * can be tracked independent of X/W unlike some other CPUs), still to
independently
> * keep things consistent with other archs:
> * -Write implies Read: W => R
> * -Execute implies Read: X => R
> diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
> index 0b3bb529d246..5414d9f5c40c 100644
> --- a/arch/arc/kernel/signal.c
> +++ b/arch/arc/kernel/signal.c
> @@ -9,7 +9,7 @@
> * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
> * -do_signal() supports TIF_RESTORE_SIGMASK
> * -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
> - * -sys_rt_sigsuspend() now comes from generic code, so discard arch implemen
> + * -sys_rt_sigsuspend() now comes from generic code, so discard arch implement
implementation
> * -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
> * -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and leaves
> * the job to do_signal()
But in any case:
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On 1/3/24 15:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/powerpc". Only touches
> comments, no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: Nicholas Piggin <[email protected]>
> Cc: Christophe Leroy <[email protected]>
> Cc: [email protected]
> ---
> arch/powerpc/boot/Makefile | 4 ++--
> arch/powerpc/boot/dts/acadia.dts | 2 +-
> arch/powerpc/boot/main.c | 2 +-
> arch/powerpc/boot/ps3.c | 2 +-
> arch/powerpc/include/asm/io.h | 2 +-
> arch/powerpc/include/asm/opal-api.h | 4 ++--
> arch/powerpc/include/asm/pmac_feature.h | 2 +-
> arch/powerpc/include/asm/uninorth.h | 2 +-
> arch/powerpc/include/uapi/asm/bootx.h | 2 +-
> arch/powerpc/kernel/eeh_pe.c | 2 +-
> arch/powerpc/kernel/fadump.c | 2 +-
> arch/powerpc/kernel/misc_64.S | 4 ++--
> arch/powerpc/kernel/process.c | 12 ++++++------
> arch/powerpc/kernel/ptrace/ptrace-tm.c | 2 +-
> arch/powerpc/kernel/smp.c | 2 +-
> arch/powerpc/kernel/sysfs.c | 4 ++--
> arch/powerpc/kvm/book3s_xive.c | 2 +-
> arch/powerpc/mm/cacheflush.c | 2 +-
> arch/powerpc/mm/nohash/kaslr_booke.c | 2 +-
> arch/powerpc/platforms/512x/mpc512x_shared.c | 2 +-
> arch/powerpc/platforms/cell/spufs/sched.c | 2 +-
> arch/powerpc/platforms/maple/pci.c | 2 +-
> arch/powerpc/platforms/powermac/pic.c | 2 +-
> arch/powerpc/platforms/powermac/sleep.S | 2 +-
> arch/powerpc/platforms/powernv/pci-sriov.c | 4 ++--
> arch/powerpc/platforms/powernv/vas-window.c | 2 +-
> arch/powerpc/platforms/pseries/vas.c | 2 +-
> arch/powerpc/sysdev/xive/common.c | 4 ++--
> arch/powerpc/sysdev/xive/native.c | 2 +-
> 29 files changed, 40 insertions(+), 40 deletions(-)
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On 1/3/24 15:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/sparc". Only touches
> comments, no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: [email protected]
> ---
> arch/sparc/include/asm/hypervisor.h | 6 +++---
> arch/sparc/include/asm/ldc.h | 2 +-
> arch/sparc/include/asm/mmu_context_64.h | 4 ++--
> arch/sparc/include/asm/switch_to_64.h | 2 +-
> arch/sparc/kernel/irq_64.c | 2 +-
> arch/sparc/kernel/kprobes.c | 2 +-
> arch/sparc/kernel/ldc.c | 2 +-
> arch/sparc/kernel/leon_pci_grpci2.c | 2 +-
> arch/sparc/kernel/of_device_64.c | 2 +-
> arch/sparc/kernel/pci.c | 2 +-
> arch/sparc/kernel/pci_impl.h | 4 ++--
> arch/sparc/kernel/pci_schizo.c | 4 ++--
> arch/sparc/kernel/perf_event.c | 2 +-
> arch/sparc/kernel/prom_irqtrans.c | 2 +-
> arch/sparc/kernel/psycho_common.c | 2 +-
> arch/sparc/kernel/signal_32.c | 2 +-
> arch/sparc/kernel/signal_64.c | 2 +-
> arch/sparc/mm/srmmu.c | 2 +-
> arch/sparc/mm/tsb.c | 2 +-
> arch/sparc/net/bpf_jit_comp_32.c | 6 +++---
> 20 files changed, 27 insertions(+), 27 deletions(-)
>
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On 1/3/24 15:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/mips". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: [email protected]
> ---
> arch/mips/bcm47xx/buttons.c | 6 +++---
> arch/mips/bcm63xx/clk.c | 4 ++--
> arch/mips/boot/compressed/dbg.c | 2 +-
> arch/mips/boot/elf2ecoff.c | 2 +-
> arch/mips/cavium-octeon/csrc-octeon.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-boot-vector.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c | 4 ++--
> arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-pko.c | 2 +-
> arch/mips/cavium-octeon/octeon-platform.c | 2 +-
> arch/mips/fw/arc/promlib.c | 6 +++---
> arch/mips/include/asm/debug.h | 2 +-
> arch/mips/include/asm/io.h | 4 ++--
> arch/mips/include/asm/mach-au1x00/au1000_dma.h | 2 +-
> arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 2 +-
> arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h | 2 +-
> arch/mips/include/asm/mach-loongson64/loongson_hwmon.h | 2 +-
> arch/mips/include/asm/mach-loongson64/loongson_regs.h | 2 +-
> arch/mips/include/asm/mach-malta/spaces.h | 4 ++--
> arch/mips/include/asm/mips-boards/bonito64.h | 2 +-
> arch/mips/include/asm/mips-cpc.h | 2 +-
> arch/mips/include/asm/mipsregs.h | 4 ++--
> arch/mips/include/asm/octeon/cvmx-bootinfo.h | 2 +-
> arch/mips/include/asm/octeon/cvmx-cmd-queue.h | 6 +++---
> arch/mips/include/asm/octeon/cvmx-pko.h | 2 +-
> arch/mips/include/asm/octeon/cvmx-pow.h | 4 ++--
> arch/mips/include/asm/octeon/octeon-model.h | 4 ++--
> arch/mips/include/asm/page.h | 2 +-
> arch/mips/include/asm/pci.h | 2 +-
> arch/mips/include/asm/pgtable-bits.h | 2 +-
> arch/mips/include/asm/sgi/mc.h | 2 +-
> arch/mips/include/asm/sn/klconfig.h | 2 +-
> arch/mips/include/asm/sync.h | 2 +-
> arch/mips/include/asm/thread_info.h | 2 +-
> arch/mips/include/asm/timex.h | 2 +-
> arch/mips/include/asm/vdso/vdso.h | 2 +-
> arch/mips/include/uapi/asm/mman.h | 2 +-
> arch/mips/include/uapi/asm/msgbuf.h | 2 +-
> arch/mips/kernel/cpu-probe.c | 2 +-
> arch/mips/kernel/kprobes.c | 2 +-
> arch/mips/kernel/relocate.c | 2 +-
> arch/mips/kernel/relocate_kernel.S | 2 +-
> arch/mips/kernel/setup.c | 2 +-
> arch/mips/kernel/signal.c | 2 +-
> arch/mips/kernel/traps.c | 2 +-
> arch/mips/kernel/vpe.c | 4 ++--
> arch/mips/kvm/emulate.c | 2 +-
> arch/mips/loongson2ef/common/platform.c | 2 +-
> arch/mips/loongson64/smp.c | 2 +-
> arch/mips/mm/c-r4k.c | 2 +-
> arch/mips/mm/cex-gen.S | 2 +-
> arch/mips/mm/tlb-r3k.c | 2 +-
> arch/mips/mm/tlb-r4k.c | 2 +-
> arch/mips/mm/tlbex.c | 4 ++--
> arch/mips/net/bpf_jit_comp32.c | 2 +-
> arch/mips/pci/ops-loongson2.c | 2 +-
> arch/mips/pci/pci-alchemy.c | 2 +-
> arch/mips/pci/pci-ar2315.c | 2 +-
> arch/mips/pci/pci-lantiq.c | 2 +-
> arch/mips/pci/pci-octeon.c | 2 +-
> arch/mips/pci/pci-xtalk-bridge.c | 2 +-
> arch/mips/pci/pcie-octeon.c | 2 +-
> arch/mips/ralink/mt7621.c | 2 +-
> arch/mips/txx9/generic/pci.c | 2 +-
> 65 files changed, 80 insertions(+), 80 deletions(-)
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On 1/3/24 15:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arm64". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: James Morse <[email protected]>
> Cc: Suzuki K Poulose <[email protected]>
> Cc: Zenghui Yu <[email protected]>
> Cc: Catalin Marinas <[email protected]>
> Cc: Will Deacon <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> ---
> arch/arm64/include/asm/kvm_hyp.h | 2 +-
> arch/arm64/kvm/arch_timer.c | 2 +-
> arch/arm64/kvm/fpsimd.c | 2 +-
> arch/arm64/kvm/hyp/nvhe/host.S | 2 +-
> arch/arm64/kvm/hyp/nvhe/mm.c | 4 ++--
> arch/arm64/kvm/inject_fault.c | 2 +-
> arch/arm64/kvm/vgic/vgic-init.c | 2 +-
> arch/arm64/kvm/vgic/vgic-its.c | 4 ++--
> 8 files changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On 1/3/24 15:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arm64/boot/dts". Only touches
> comments, no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: Conor Dooley <[email protected]>
> Cc: [email protected]
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 2 +-
> arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 2 +-
> arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +-
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
> arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts | 2 +-
> arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
> arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sa8155p.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++--
> arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 2 +-
> arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 2 +-
> arch/arm64/boot/dts/renesas/draak.dtsi | 2 +-
> arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts | 2 +-
> arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +-
> 16 files changed, 18 insertions(+), 18 deletions(-)
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On 1/3/24 15:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arm64". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: [email protected]
> ---
> arch/arm64/Kconfig | 2 +-
> arch/arm64/include/asm/assembler.h | 4 ++--
> arch/arm64/include/asm/cpufeature.h | 4 ++--
> arch/arm64/include/asm/pgtable.h | 2 +-
> arch/arm64/include/asm/suspend.h | 2 +-
> arch/arm64/include/asm/traps.h | 4 ++--
> arch/arm64/kernel/acpi.c | 2 +-
> arch/arm64/kernel/cpufeature.c | 6 +++---
> arch/arm64/kernel/entry-common.c | 2 +-
> arch/arm64/kernel/entry-ftrace.S | 2 +-
> arch/arm64/kernel/entry.S | 2 +-
> arch/arm64/kernel/ftrace.c | 2 +-
> arch/arm64/kernel/machine_kexec.c | 2 +-
> arch/arm64/kernel/probes/uprobes.c | 2 +-
> arch/arm64/kernel/sdei.c | 2 +-
> arch/arm64/kernel/smp.c | 2 +-
> arch/arm64/kernel/traps.c | 2 +-
> 17 files changed, 22 insertions(+), 22 deletions(-)
Reviewed-by: Randy Dunlap <[email protected]>
Thanks.
--
#Randy
On Wed, Jan 03, 2024 at 04:31:31PM -0800, Randy Dunlap wrote:
> On 1/3/24 15:15, Bjorn Helgaas wrote:
> ...
> > --- a/arch/arc/include/asm/pgtable-bits-arcv2.h
> > +++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
> > @@ -66,7 +66,7 @@
> > * Other rules which cause the divergence from 1:1 mapping
> > *
> > * 1. Although ARC700 can do exclusive execute/write protection (meaning R
> > - * can be tracked independet of X/W unlike some other CPUs), still to
> > + * can be tracked independent of X/W unlike some other CPUs), still to
>
> independently
Indeed, embarrassing, thanks.
> > * keep things consistent with other archs:
> > * -Write implies Read: W => R
> > * -Execute implies Read: X => R
>
> > diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
> > index 0b3bb529d246..5414d9f5c40c 100644
> > --- a/arch/arc/kernel/signal.c
> > +++ b/arch/arc/kernel/signal.c
> > @@ -9,7 +9,7 @@
> > * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
> > * -do_signal() supports TIF_RESTORE_SIGMASK
> > * -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
> > - * -sys_rt_sigsuspend() now comes from generic code, so discard arch implemen
> > + * -sys_rt_sigsuspend() now comes from generic code, so discard arch implement
>
> implementation
Thanks again.
Added these and a couple other ones to my local copy in case there's a
v2:
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h b/arch/arc/include/asm/pgtable-bits-arcv2.h
index f8f85c04d7a8..8ebec1b21d24 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -66,7 +66,7 @@
* Other rules which cause the divergence from 1:1 mapping
*
* 1. Although ARC700 can do exclusive execute/write protection (meaning R
- * can be tracked independent of X/W unlike some other CPUs), still to
+ * can be tracked independently of X/W unlike some other CPUs), still to
* keep things consistent with other archs:
* -Write implies Read: W => R
* -Execute implies Read: X => R
diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
index 5414d9f5c40c..3490d005e6d4 100644
--- a/arch/arc/kernel/signal.c
+++ b/arch/arc/kernel/signal.c
@@ -8,15 +8,16 @@
*
* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
* -do_signal() supports TIF_RESTORE_SIGMASK
- * -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
- * -sys_rt_sigsuspend() now comes from generic code, so discard arch implement
+ * -do_signal() no longer needs oldset, required by OLD sys_sigsuspend
+ * -sys_rt_sigsuspend() now comes from generic code, so discard arch
+ * implementation
* -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
* -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and leaves
* the job to do_signal()
*
* vineetg: July 2009
* -Modified Code to support the uClibc provided userland sigreturn stub
- * to avoid kernel synthesing it on user stack at runtime, costing TLB
+ * to avoid kernel synthesizing it on user stack at runtime, costing TLB
* probes and Cache line flushes.
*
* vineetg: July 2009
On Wed, Jan 03, 2024 at 05:16:03PM -0600, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/mips". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: [email protected]
> ---
> arch/mips/bcm47xx/buttons.c | 6 +++---
> arch/mips/bcm63xx/clk.c | 4 ++--
> arch/mips/boot/compressed/dbg.c | 2 +-
> arch/mips/boot/elf2ecoff.c | 2 +-
> arch/mips/cavium-octeon/csrc-octeon.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-boot-vector.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c | 4 ++--
> arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c | 2 +-
> arch/mips/cavium-octeon/executive/cvmx-pko.c | 2 +-
> arch/mips/cavium-octeon/octeon-platform.c | 2 +-
> arch/mips/fw/arc/promlib.c | 6 +++---
> arch/mips/include/asm/debug.h | 2 +-
> arch/mips/include/asm/io.h | 4 ++--
> arch/mips/include/asm/mach-au1x00/au1000_dma.h | 2 +-
> arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 2 +-
> arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h | 2 +-
> arch/mips/include/asm/mach-loongson64/loongson_hwmon.h | 2 +-
> arch/mips/include/asm/mach-loongson64/loongson_regs.h | 2 +-
> arch/mips/include/asm/mach-malta/spaces.h | 4 ++--
> arch/mips/include/asm/mips-boards/bonito64.h | 2 +-
> arch/mips/include/asm/mips-cpc.h | 2 +-
> arch/mips/include/asm/mipsregs.h | 4 ++--
> arch/mips/include/asm/octeon/cvmx-bootinfo.h | 2 +-
> arch/mips/include/asm/octeon/cvmx-cmd-queue.h | 6 +++---
> arch/mips/include/asm/octeon/cvmx-pko.h | 2 +-
> arch/mips/include/asm/octeon/cvmx-pow.h | 4 ++--
> arch/mips/include/asm/octeon/octeon-model.h | 4 ++--
> arch/mips/include/asm/page.h | 2 +-
> arch/mips/include/asm/pci.h | 2 +-
> arch/mips/include/asm/pgtable-bits.h | 2 +-
> arch/mips/include/asm/sgi/mc.h | 2 +-
> arch/mips/include/asm/sn/klconfig.h | 2 +-
> arch/mips/include/asm/sync.h | 2 +-
> arch/mips/include/asm/thread_info.h | 2 +-
> arch/mips/include/asm/timex.h | 2 +-
> arch/mips/include/asm/vdso/vdso.h | 2 +-
> arch/mips/include/uapi/asm/mman.h | 2 +-
> arch/mips/include/uapi/asm/msgbuf.h | 2 +-
> arch/mips/kernel/cpu-probe.c | 2 +-
> arch/mips/kernel/kprobes.c | 2 +-
> arch/mips/kernel/relocate.c | 2 +-
> arch/mips/kernel/relocate_kernel.S | 2 +-
> arch/mips/kernel/setup.c | 2 +-
> arch/mips/kernel/signal.c | 2 +-
> arch/mips/kernel/traps.c | 2 +-
> arch/mips/kernel/vpe.c | 4 ++--
> arch/mips/kvm/emulate.c | 2 +-
> arch/mips/loongson2ef/common/platform.c | 2 +-
> arch/mips/loongson64/smp.c | 2 +-
> arch/mips/mm/c-r4k.c | 2 +-
> arch/mips/mm/cex-gen.S | 2 +-
> arch/mips/mm/tlb-r3k.c | 2 +-
> arch/mips/mm/tlb-r4k.c | 2 +-
> arch/mips/mm/tlbex.c | 4 ++--
> arch/mips/net/bpf_jit_comp32.c | 2 +-
> arch/mips/pci/ops-loongson2.c | 2 +-
> arch/mips/pci/pci-alchemy.c | 2 +-
> arch/mips/pci/pci-ar2315.c | 2 +-
> arch/mips/pci/pci-lantiq.c | 2 +-
> arch/mips/pci/pci-octeon.c | 2 +-
> arch/mips/pci/pci-xtalk-bridge.c | 2 +-
> arch/mips/pci/pcie-octeon.c | 2 +-
> arch/mips/ralink/mt7621.c | 2 +-
> arch/mips/txx9/generic/pci.c | 2 +-
> 65 files changed, 80 insertions(+), 80 deletions(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
On 2024/1/4 7:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arm64". Only touches comments,
> no code changes.
Reviewed-by: Zenghui Yu <[email protected]>
Thanks!
On 2024-01-04 00:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/sparc". Only touches
> comments, no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: [email protected]
Applied to my for-next branch.
Thanks,
Andreas
On 2024/1/4 07:16, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arm64". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
> Cc: James Morse <[email protected]>
> Cc: Suzuki K Poulose <[email protected]>
> Cc: Zenghui Yu <[email protected]>
> Cc: Catalin Marinas <[email protected]>
> Cc: Will Deacon <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
Oliver, mind taking it into 6.9?
On Sat, Feb 24, 2024 at 12:39:34PM +0800, Zenghui Yu wrote:
> On 2024/1/4 07:16, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas <[email protected]>
> >
> > Fix typos, most reported by "codespell arch/arm64". Only touches comments,
> > no code changes.
> >
> > Signed-off-by: Bjorn Helgaas <[email protected]>
> > Cc: James Morse <[email protected]>
> > Cc: Suzuki K Poulose <[email protected]>
> > Cc: Zenghui Yu <[email protected]>
> > Cc: Catalin Marinas <[email protected]>
> > Cc: Will Deacon <[email protected]>
> > Cc: [email protected]
> > Cc: [email protected]
>
> Oliver, mind taking it into 6.9?
Thanks for the nudge!
--
Thanks,
Oliver
On Wed, 3 Jan 2024 17:16:02 -0600, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arm64". Only touches comments,
> no code changes.
>
>
Applied to kvmarm/next, thanks!
[5/8] KVM: arm64: Fix typos
https://git.kernel.org/kvmarm/kvmarm/c/75841d89f3ed
--
Best,
Oliver
On 1/4/24 11:02, Bjorn Helgaas wrote:
>>> diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
>>> index 0b3bb529d246..5414d9f5c40c 100644
>>> --- a/arch/arc/kernel/signal.c
>>> +++ b/arch/arc/kernel/signal.c
>>> @@ -9,7 +9,7 @@
>>> * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
>>> * -do_signal() supports TIF_RESTORE_SIGMASK
>>> * -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
>>> - * -sys_rt_sigsuspend() now comes from generic code, so discard arch implemen
>>> + * -sys_rt_sigsuspend() now comes from generic code, so discard arch implement
>>
> Thanks again.
>
> Added these and a couple other ones to my local copy in case there's a
> v2:
Sorry this slipped thru cracks. I don't see it upstream and given some
pending fixes for Linus can pick this up.
So I take v1 + the fixlet below or do you have any more local changes
and prefer respin/resending ?
Thx,
-Vineet
>
> diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h b/arch/arc/include/asm/pgtable-bits-arcv2.h
> index f8f85c04d7a8..8ebec1b21d24 100644
> --- a/arch/arc/include/asm/pgtable-bits-arcv2.h
> +++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
> @@ -66,7 +66,7 @@
> * Other rules which cause the divergence from 1:1 mapping
> *
> * 1. Although ARC700 can do exclusive execute/write protection (meaning R
> - * can be tracked independent of X/W unlike some other CPUs), still to
> + * can be tracked independently of X/W unlike some other CPUs), still to
> * keep things consistent with other archs:
> * -Write implies Read: W => R
> * -Execute implies Read: X => R
> diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
> index 5414d9f5c40c..3490d005e6d4 100644
> --- a/arch/arc/kernel/signal.c
> +++ b/arch/arc/kernel/signal.c
> @@ -8,15 +8,16 @@
> *
> * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
> * -do_signal() supports TIF_RESTORE_SIGMASK
> - * -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
> - * -sys_rt_sigsuspend() now comes from generic code, so discard arch implement
> + * -do_signal() no longer needs oldset, required by OLD sys_sigsuspend
> + * -sys_rt_sigsuspend() now comes from generic code, so discard arch
> + * implementation
> * -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
> * -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and leaves
> * the job to do_signal()
> *
> * vineetg: July 2009
> * -Modified Code to support the uClibc provided userland sigreturn stub
> - * to avoid kernel synthesing it on user stack at runtime, costing TLB
> + * to avoid kernel synthesizing it on user stack at runtime, costing TLB
> * probes and Cache line flushes.
> *
> * vineetg: July 2009
From: Bjorn Helgaas <[email protected]>
Fix typos, most reported by "codespell arch/arc". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
---
arch/arc/boot/Makefile | 4 ++--
arch/arc/boot/dts/axc003.dtsi | 4 ++--
arch/arc/boot/dts/vdk_axs10x_mb.dtsi | 2 +-
arch/arc/include/asm/dsp.h | 2 +-
arch/arc/include/asm/entry-compact.h | 10 +++++-----
arch/arc/include/asm/entry.h | 4 ++--
arch/arc/include/asm/irq.h | 2 +-
arch/arc/include/asm/irqflags-compact.h | 2 +-
arch/arc/include/asm/mmu_context.h | 2 +-
arch/arc/include/asm/pgtable-bits-arcv2.h | 2 +-
arch/arc/include/asm/shmparam.h | 2 +-
arch/arc/include/asm/smp.h | 4 ++--
arch/arc/include/asm/thread_info.h | 2 +-
arch/arc/include/uapi/asm/swab.h | 2 +-
arch/arc/kernel/entry-arcv2.S | 8 ++++----
arch/arc/kernel/entry.S | 4 ++--
arch/arc/kernel/head.S | 2 +-
arch/arc/kernel/intc-arcv2.c | 2 +-
arch/arc/kernel/perf_event.c | 2 +-
arch/arc/kernel/setup.c | 2 +-
arch/arc/kernel/signal.c | 7 ++++---
arch/arc/kernel/traps.c | 2 +-
arch/arc/kernel/vmlinux.lds.S | 4 ++--
arch/arc/mm/tlb.c | 4 ++--
arch/arc/mm/tlbex.S | 8 ++++----
25 files changed, 45 insertions(+), 44 deletions(-)
diff --git a/arch/arc/boot/Makefile b/arch/arc/boot/Makefile
index 5648748c285f..5a8550124b73 100644
--- a/arch/arc/boot/Makefile
+++ b/arch/arc/boot/Makefile
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
-# uImage build relies on mkimage being availble on your host for ARC target
+# uImage build relies on mkimage being available on your host for ARC target
# You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage
-# and make sure it's reacable from your PATH
+# and make sure it's reachable from your PATH
OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index 3434c8131ecd..c0a812674ce9 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -119,9 +119,9 @@ mmc@15000 {
/*
* The DW APB ICTL intc on MB is connected to CPU intc via a
* DT "invisible" DW APB GPIO block, configured to simply pass thru
- * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
+ * interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c)
*
- * So here we mimic a direct connection betwen them, ignoring the
+ * So here we mimic a direct connection between them, ignoring the
* ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
* instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
*
diff --git a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
index 90a412026e64..0e0e2d337bf8 100644
--- a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
@@ -113,7 +113,7 @@ mmc@15000 {
/*
* Embedded Vision subsystem UIO mappings; only relevant for EV VDK
*
- * This node is intentionally put outside of MB above becase
+ * This node is intentionally put outside of MB above because
* it maps areas outside of MB's 0xez-0xfz.
*/
uio_ev: uio@d0000000 {
diff --git a/arch/arc/include/asm/dsp.h b/arch/arc/include/asm/dsp.h
index 202c78e56704..f496dbc4640b 100644
--- a/arch/arc/include/asm/dsp.h
+++ b/arch/arc/include/asm/dsp.h
@@ -12,7 +12,7 @@
/*
* DSP-related saved registers - need to be saved only when you are
* scheduled out.
- * structure fields name must correspond to aux register defenitions for
+ * structure fields name must correspond to aux register definitions for
* automatic offset calculation in DSP_AUX_SAVE_RESTORE macros
*/
struct dsp_callee_regs {
diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h
index 92c3e9f13252..00946fe04c9b 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -7,7 +7,7 @@
* Stack switching code can no longer reliably rely on the fact that
* if we are NOT in user mode, stack is switched to kernel mode.
* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
- * it's prologue including stack switching from user mode
+ * its prologue including stack switching from user mode
*
* Vineetg: Aug 28th 2008: Bug #94984
* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
@@ -143,7 +143,7 @@
* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
* 3. But before it could switch SP from USER to KERNEL stack
* a L2 IRQ "Interrupts" L1
- * Thay way although L2 IRQ happened in Kernel mode, stack is still
+ * That way although L2 IRQ happened in Kernel mode, stack is still
* not switched.
* To handle this, we may need to switch stack even if in kernel mode
* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
@@ -173,7 +173,7 @@
GET_CURR_TASK_ON_CPU r9
- /* With current tsk in r9, get it's kernel mode stack base */
+ /* With current tsk in r9, get its kernel mode stack base */
GET_TSK_STACK_BASE r9, r9
/* save U mode SP @ pt_regs->sp */
@@ -282,7 +282,7 @@
* NOTE:
*
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
- * for memory load operations. If used in that way interrupts are deffered
+ * for memory load operations. If used in that way interrupts are deferred
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro EXCEPTION_EPILOGUE
@@ -350,7 +350,7 @@
* NOTE:
*
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
- * for memory load operations. If used in that way interrupts are deffered
+ * for memory load operations. If used in that way interrupts are deferred
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro INTERRUPT_EPILOGUE LVL
diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h
index cf1ba376e992..38c35722cebf 100644
--- a/arch/arc/include/asm/entry.h
+++ b/arch/arc/include/asm/entry.h
@@ -7,7 +7,7 @@
#ifndef __ASM_ARC_ENTRY_H
#define __ASM_ARC_ENTRY_H
-#include <asm/unistd.h> /* For NR_syscalls defination */
+#include <asm/unistd.h> /* For NR_syscalls definition */
#include <asm/arcregs.h>
#include <asm/ptrace.h>
#include <asm/processor.h> /* For VMALLOC_START */
@@ -56,7 +56,7 @@
.endm
/*-------------------------------------------------------------
- * given a tsk struct, get to the base of it's kernel mode stack
+ * given a tsk struct, get to the base of its kernel mode stack
* tsk->thread_info is really a PAGE, whose bottom hoists stack
* which grows upwards towards thread_info
*------------------------------------------------------------*/
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index c574712ad865..9cd79263acba 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -10,7 +10,7 @@
* ARCv2 can support 240 interrupts in the core interrupts controllers and
* 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
* configurations of boards.
- * This doesnt affect ARCompact, but we change it to same value
+ * This doesn't affect ARCompact, but we change it to same value
*/
#define NR_IRQS 512
diff --git a/arch/arc/include/asm/irqflags-compact.h b/arch/arc/include/asm/irqflags-compact.h
index 0d63e568d64c..936a2f21f315 100644
--- a/arch/arc/include/asm/irqflags-compact.h
+++ b/arch/arc/include/asm/irqflags-compact.h
@@ -46,7 +46,7 @@
* IRQ Control Macros
*
* All of them have "memory" clobber (compiler barrier) which is needed to
- * ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
+ * ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available)
* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
*
* Noted at the time of Abilis Timer List corruption
diff --git a/arch/arc/include/asm/mmu_context.h b/arch/arc/include/asm/mmu_context.h
index dda471f5f05b..9963bb1a5733 100644
--- a/arch/arc/include/asm/mmu_context.h
+++ b/arch/arc/include/asm/mmu_context.h
@@ -165,7 +165,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* for retiring-mm. However destroy_context( ) still needs to do that because
* between mm_release( ) = >deactive_mm( ) and
* mmput => .. => __mmdrop( ) => destroy_context( )
- * there is a good chance that task gets sched-out/in, making it's ASID valid
+ * there is a good chance that task gets sched-out/in, making its ASID valid
* again (this teased me for a whole day).
*/
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h b/arch/arc/include/asm/pgtable-bits-arcv2.h
index f3eea3f30b2e..8ebec1b21d24 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -66,7 +66,7 @@
* Other rules which cause the divergence from 1:1 mapping
*
* 1. Although ARC700 can do exclusive execute/write protection (meaning R
- * can be tracked independet of X/W unlike some other CPUs), still to
+ * can be tracked independently of X/W unlike some other CPUs), still to
* keep things consistent with other archs:
* -Write implies Read: W => R
* -Execute implies Read: X => R
diff --git a/arch/arc/include/asm/shmparam.h b/arch/arc/include/asm/shmparam.h
index 8b0251464ffd..719112af0f41 100644
--- a/arch/arc/include/asm/shmparam.h
+++ b/arch/arc/include/asm/shmparam.h
@@ -6,7 +6,7 @@
#ifndef __ARC_ASM_SHMPARAM_H
#define __ARC_ASM_SHMPARAM_H
-/* Handle upto 2 cache bins */
+/* Handle up to 2 cache bins */
#define SHMLBA (2 * PAGE_SIZE)
/* Enforce SHMLBA in shmat */
diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
index e0913f52c2cd..990f834909f0 100644
--- a/arch/arc/include/asm/smp.h
+++ b/arch/arc/include/asm/smp.h
@@ -77,7 +77,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
/*
* ARC700 doesn't support atomic Read-Modify-Write ops.
- * Originally Interrupts had to be disabled around code to gaurantee atomicity.
+ * Originally Interrupts had to be disabled around code to guarantee atomicity.
* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
* based on retry-if-irq-in-atomic (with hardware assist).
* However despite these, we provide the IRQ disabling variant
@@ -86,7 +86,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
* support needed.
*
* (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
- * gaurantted by the platform (not something which core handles).
+ * guaranteed by the platform (not something which core handles).
* Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
* disabling for atomicity.
*
diff --git a/arch/arc/include/asm/thread_info.h b/arch/arc/include/asm/thread_info.h
index 4c530cf131f3..12daaf3a61ea 100644
--- a/arch/arc/include/asm/thread_info.h
+++ b/arch/arc/include/asm/thread_info.h
@@ -38,7 +38,7 @@
struct thread_info {
unsigned long flags; /* low level flags */
unsigned long ksp; /* kernel mode stack top in __switch_to */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
+ int preempt_count; /* 0 => preemptible, <0 => BUG */
int cpu; /* current CPU */
unsigned long thr_ptr; /* TLS ptr */
struct task_struct *task; /* main task structure */
diff --git a/arch/arc/include/uapi/asm/swab.h b/arch/arc/include/uapi/asm/swab.h
index 02109cd48ee1..8d1f1ef44ba7 100644
--- a/arch/arc/include/uapi/asm/swab.h
+++ b/arch/arc/include/uapi/asm/swab.h
@@ -62,7 +62,7 @@
* 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem
*
* Joern suggested a better "C" algorithm which is great since
- * (1) It is portable to any architecure
+ * (1) It is portable to any architecture
* (2) At the same time it takes advantage of ARC ISA (rotate intrns)
*/
diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
index 2e49c81c8086..e238b5fd3c8c 100644
--- a/arch/arc/kernel/entry-arcv2.S
+++ b/arch/arc/kernel/entry-arcv2.S
@@ -5,7 +5,7 @@
* Copyright (C) 2013 Synopsys, Inc. (http://www.synopsys.com)
*/
-#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
+#include <linux/linkage.h> /* ARC_{ENTRY,EXIT} */
#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
#include <asm/errno.h>
#include <asm/arcregs.h>
@@ -31,7 +31,7 @@ VECTOR res_service ; Reset Vector
VECTOR mem_service ; Mem exception
VECTOR instr_service ; Instrn Error
VECTOR EV_MachineCheck ; Fatal Machine check
-VECTOR EV_TLBMissI ; Intruction TLB miss
+VECTOR EV_TLBMissI ; Instruction TLB miss
VECTOR EV_TLBMissD ; Data TLB miss
VECTOR EV_TLBProtV ; Protection Violation
VECTOR EV_PrivilegeV ; Privilege Violation
@@ -76,11 +76,11 @@ ENTRY(handle_interrupt)
# query in hard ISR path would return false (since .IE is set) which would
# trips genirq interrupt handling asserts.
#
- # So do a "soft" disable of interrutps here.
+ # So do a "soft" disable of interrupts here.
#
# Note this disable is only for consistent book-keeping as further interrupts
# will be disabled anyways even w/o this. Hardware tracks active interrupts
- # seperately in AUX_IRQ_ACT.active and will not take new interrupts
+ # separately in AUX_IRQ_ACT.active and will not take new interrupts
# unless this one returns (or higher prio becomes pending in 2-prio scheme)
IRQ_DISABLE
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 089f6680518f..3c7e74aba679 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -95,7 +95,7 @@ ENTRY(EV_MachineCheck)
lr r0, [efa]
mov r1, sp
- ; MC excpetions disable MMU
+ ; MC exceptions disable MMU
ARC_MMU_REENABLE r3
lsr r3, r10, 8
@@ -209,7 +209,7 @@ trap_with_param:
; ---------------------------------------------
; syscall TRAP
-; ABI: (r0-r7) upto 8 args, (r8) syscall number
+; ABI: (r0-r7) up to 8 args, (r8) syscall number
; ---------------------------------------------
ENTRY(EV_Trap)
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 9152782444b5..8d541f53fae3 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -165,7 +165,7 @@ ENTRY(first_lines_of_secondary)
; setup stack (fp, sp)
mov fp, 0
- ; set it's stack base to tsk->thread_info bottom
+ ; set its stack base to tsk->thread_info bottom
GET_TSK_STACK_BASE r0, sp
j start_kernel_secondary
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 678898757e47..f324f0e3341a 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -56,7 +56,7 @@ void arc_init_IRQ(void)
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
/*
- * ARCv2 core intc provides multiple interrupt priorities (upto 16).
+ * ARCv2 core intc provides multiple interrupt priorities (up to 16).
* Typical builds though have only two levels (0-high, 1-low)
* Linux by default uses lower prio 1 for most irqs, reserving 0 for
* NMI style interrupts in future (say perf)
diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index adff957962da..6e5a651cd75c 100644
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -38,7 +38,7 @@
* (based on a specific RTL build)
* Below is the static map between perf generic/arc specific event_id and
* h/w condition names.
- * At the time of probe, we loop thru each index and find it's name to
+ * At the time of probe, we loop thru each index and find its name to
* complete the mapping of perf event_id to h/w index as latter is needed
* to program the counter really
*/
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index d08a5092c2b4..7b6a9beba9db 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -390,7 +390,7 @@ static void arc_chk_core_config(struct cpuinfo_arc *info)
#ifdef CONFIG_ARC_HAS_DCCM
/*
* DCCM can be arbit placed in hardware.
- * Make sure it's placement/sz matches what Linux is built with
+ * Make sure its placement/sz matches what Linux is built with
*/
if ((unsigned int)__arc_dccm_base != info->dccm.base)
panic("Linux built with incorrect DCCM Base address\n");
diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
index 8f6f4a542964..fefa705a8638 100644
--- a/arch/arc/kernel/signal.c
+++ b/arch/arc/kernel/signal.c
@@ -8,15 +8,16 @@
*
* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
* -do_signal() supports TIF_RESTORE_SIGMASK
- * -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
- * -sys_rt_sigsuspend() now comes from generic code, so discard arch implemen
+ * -do_signal() no longer needs oldset, required by OLD sys_sigsuspend
+ * -sys_rt_sigsuspend() now comes from generic code, so discard arch
+ * implementation
* -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
* -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and leaves
* the job to do_signal()
*
* vineetg: July 2009
* -Modified Code to support the uClibc provided userland sigreturn stub
- * to avoid kernel synthesing it on user stack at runtime, costing TLB
+ * to avoid kernel synthesizing it on user stack at runtime, costing TLB
* probes and Cache line flushes.
*
* vineetg: July 2009
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index 9b9570b79362..a19751e824fb 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -89,7 +89,7 @@ int do_misaligned_access(unsigned long address, struct pt_regs *regs,
/*
* Entry point for miscll errors such as Nested Exceptions
- * -Duplicate TLB entry is handled seperately though
+ * -Duplicate TLB entry is handled separately though
*/
void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
{
diff --git a/arch/arc/kernel/vmlinux.lds.S b/arch/arc/kernel/vmlinux.lds.S
index 549c3f407918..61a1b2b96e1d 100644
--- a/arch/arc/kernel/vmlinux.lds.S
+++ b/arch/arc/kernel/vmlinux.lds.S
@@ -41,8 +41,8 @@ SECTIONS
#endif
/*
- * The reason for having a seperate subsection .init.ramfs is to
- * prevent objump from including it in kernel dumps
+ * The reason for having a separate subsection .init.ramfs is to
+ * prevent objdump from including it in kernel dumps
*
* Reason for having .init.ramfs above .init is to make sure that the
* binary blob is tucked away to one side, reducing the displacement
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index ad702b49aeb3..cae4a7aae0ed 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -212,7 +212,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long flags;
/* If range @start to @end is more than 32 TLB entries deep,
- * its better to move to a new ASID rather than searching for
+ * it's better to move to a new ASID rather than searching for
* individual entries and then shooting them down
*
* The calc above is rough, doesn't account for unaligned parts,
@@ -408,7 +408,7 @@ static void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *p
* -More importantly it makes this handler inconsistent with fast-path
* TLB Refill handler which always deals with "current"
*
- * Lets see the use cases when current->mm != vma->mm and we land here
+ * Let's see the use cases when current->mm != vma->mm and we land here
* 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
* Here VM wants to pre-install a TLB entry for user stack while
* current->mm still points to pre-execve mm (hence the condition).
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index e054780a8fe0..dc65e87a531f 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -5,19 +5,19 @@
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (http://www.synopsys.com)
*
* Vineetg: April 2011 :
- * -MMU v1: moved out legacy code into a seperate file
+ * -MMU v1: moved out legacy code into a separate file
* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
* helps avoid a shift when preparing PD0 from PTE
*
* Vineetg: July 2009
- * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
- * entry, so that it doesn't knock out it's I-TLB entry
+ * -For MMU V2, we need not do heuristics at the time of committing a D-TLB
+ * entry, so that it doesn't knock out its I-TLB entry
* -Some more fine tuning:
* bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
*
* Vineetg: July 2009
* -Practically rewrote the I/D TLB Miss handlers
- * Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
+ * Now 40 and 135 instructions apiece as compared to 131 and 449 resp.
* Hence Leaner by 1.5 K
* Used Conditional arithmetic to replace excessive branching
* Also used short instructions wherever possible
--
2.34.1
On 3/29/24 15:14, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <[email protected]>
>
> Fix typos, most reported by "codespell arch/arc". Only touches comments,
> no code changes.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
Added to ARC for-curr.
Thx,
-Vineet
From: Bjorn Helgaas <[email protected]>
IMS (Interrupt Message Store) support appeared in v6.2, but there are no
users yet.
Remove it for now. We can add it back when a user comes along.
Bjorn Helgaas (3):
Revert "PCI/MSI: Provide stubs for IMS functions"
Revert "PCI/MSI: Provide pci_ims_alloc/free_irq()"
Revert "PCI/MSI: Provide IMS (Interrupt Message Store) support"
drivers/pci/msi/api.c | 50 -------------------------------
drivers/pci/msi/irqdomain.c | 59 -------------------------------------
include/linux/pci.h | 26 ----------------
3 files changed, 135 deletions(-)
--
2.34.1
From: Bjorn Helgaas <[email protected]>
This reverts commit 41efa431244f6498833ff8ee8dde28c4924c5479.
IMS (Interrupt Message Store) support appeared in v6.2, but there are no
users yet.
Remove it for now. We can add it back when a user comes along. If this is
re-added later, this could be squashed with these commits:
0194425af0c8 ("PCI/MSI: Provide IMS (Interrupt Message Store) support")
c9e5bea27383 ("PCI/MSI: Provide pci_ims_alloc/free_irq()")
which added the non-stub implementations.
Signed-off-by: Bjorn Helgaas <[email protected]>
---
include/linux/pci.h | 34 ++++++++--------------------------
1 file changed, 8 insertions(+), 26 deletions(-)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 16493426a04f..abbef75b2b92 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1658,8 +1658,6 @@ struct msix_entry {
u16 entry; /* Driver uses to specify entry, OS writes */
};
-struct msi_domain_template;
-
#ifdef CONFIG_PCI_MSI
int pci_msi_vec_count(struct pci_dev *dev);
void pci_disable_msi(struct pci_dev *dev);
@@ -1692,11 +1690,6 @@ void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
void pci_free_irq_vectors(struct pci_dev *dev);
int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
-bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
- unsigned int hwsize, void *data);
-struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
- const struct irq_affinity_desc *affdesc);
-void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
#else
static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
@@ -1760,25 +1753,6 @@ static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
{
return cpu_possible_mask;
}
-
-static inline bool pci_create_ims_domain(struct pci_dev *pdev,
- const struct msi_domain_template *template,
- unsigned int hwsize, void *data)
-{ return false; }
-
-static inline struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev,
- union msi_instance_cookie *icookie,
- const struct irq_affinity_desc *affdesc)
-{
- struct msi_map map = { .index = -ENOSYS, };
-
- return map;
-}
-
-static inline void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map)
-{
-}
-
#endif
/**
@@ -2690,6 +2664,14 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
#endif
+struct msi_domain_template;
+
+bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
+ unsigned int hwsize, void *data);
+struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
+ const struct irq_affinity_desc *affdesc);
+void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
+
#include <linux/dma-mapping.h>
#define pci_printk(level, pdev, fmt, arg...) \
--
2.34.1
From: Bjorn Helgaas <[email protected]>
This reverts commit c9e5bea273834a63b5e9ba90ad94b305ba50704e.
IMS (Interrupt Message Store) support appeared in v6.2, but there are no
users yet.
Remove it for now. We can add it back when a user comes along. If this is
re-added later, the relevant part of 41efa431244f ("PCI/MSI: Provide stubs
for IMS functions") should be squashed into it.
Signed-off-by: Bjorn Helgaas <[email protected]>
---
drivers/pci/msi/api.c | 50 -------------------------------------------
include/linux/pci.h | 3 ---
2 files changed, 53 deletions(-)
diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c
index be679aa5db64..3c1cd29c5cf2 100644
--- a/drivers/pci/msi/api.c
+++ b/drivers/pci/msi/api.c
@@ -365,56 +365,6 @@ const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
}
EXPORT_SYMBOL(pci_irq_get_affinity);
-/**
- * pci_ims_alloc_irq - Allocate an interrupt on a PCI/IMS interrupt domain
- * @dev: The PCI device to operate on
- * @icookie: Pointer to an IMS implementation specific cookie for this
- * IMS instance (PASID, queue ID, pointer...).
- * The cookie content is copied into the MSI descriptor for the
- * interrupt chip callbacks or domain specific setup functions.
- * @affdesc: Optional pointer to an interrupt affinity descriptor
- *
- * There is no index for IMS allocations as IMS is an implementation
- * specific storage and does not have any direct associations between
- * index, which might be a pure software construct, and device
- * functionality. This association is established by the driver either via
- * the index - if there is a hardware table - or in case of purely software
- * managed IMS implementation the association happens via the
- * irq_write_msi_msg() callback of the implementation specific interrupt
- * chip, which utilizes the provided @icookie to store the MSI message in
- * the appropriate place.
- *
- * Return: A struct msi_map
- *
- * On success msi_map::index contains the allocated index (>= 0) and
- * msi_map::virq the allocated Linux interrupt number (> 0).
- *
- * On fail msi_map::index contains the error code and msi_map::virq
- * is set to 0.
- */
-struct msi_map pci_ims_alloc_irq(struct pci_dev *dev, union msi_instance_cookie *icookie,
- const struct irq_affinity_desc *affdesc)
-{
- return msi_domain_alloc_irq_at(&dev->dev, MSI_SECONDARY_DOMAIN, MSI_ANY_INDEX,
- affdesc, icookie);
-}
-EXPORT_SYMBOL_GPL(pci_ims_alloc_irq);
-
-/**
- * pci_ims_free_irq - Allocate an interrupt on a PCI/IMS interrupt domain
- * which was allocated via pci_ims_alloc_irq()
- * @dev: The PCI device to operate on
- * @map: A struct msi_map describing the interrupt to free as
- * returned from pci_ims_alloc_irq()
- */
-void pci_ims_free_irq(struct pci_dev *dev, struct msi_map map)
-{
- if (WARN_ON_ONCE(map.index < 0 || map.virq <= 0))
- return;
- msi_domain_free_irqs_range(&dev->dev, MSI_SECONDARY_DOMAIN, map.index, map.index);
-}
-EXPORT_SYMBOL_GPL(pci_ims_free_irq);
-
/**
* pci_free_irq_vectors() - Free previously allocated IRQs for a device
* @dev: the PCI device to operate on
diff --git a/include/linux/pci.h b/include/linux/pci.h
index abbef75b2b92..3deb3e42d990 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -2668,9 +2668,6 @@ struct msi_domain_template;
bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
unsigned int hwsize, void *data);
-struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
- const struct irq_affinity_desc *affdesc);
-void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
#include <linux/dma-mapping.h>
--
2.34.1
From: Bjorn Helgaas <[email protected]>
This reverts commit 0194425af0c87acaad457989a2c6d90dba58e776.
IMS (Interrupt Message Store) support appeared in v6.2, but there are no
users yet.
Remove it for now. We can add it back when a user comes along. If this is
re-added later, the relevant part of 41efa431244f ("PCI/MSI: Provide stubs
for IMS functions") should be squashed into it.
Signed-off-by: Bjorn Helgaas <[email protected]>
---
drivers/pci/msi/irqdomain.c | 59 -------------------------------------
include/linux/pci.h | 5 ----
2 files changed, 64 deletions(-)
diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c
index cfd84a899c82..03d2dd25790d 100644
--- a/drivers/pci/msi/irqdomain.c
+++ b/drivers/pci/msi/irqdomain.c
@@ -355,65 +355,6 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask,
return (supported & feature_mask) == feature_mask;
}
-/**
- * pci_create_ims_domain - Create a secondary IMS domain for a PCI device
- * @pdev: The PCI device to operate on
- * @template: The MSI info template which describes the domain
- * @hwsize: The size of the hardware entry table or 0 if the domain
- * is purely software managed
- * @data: Optional pointer to domain specific data to be stored
- * in msi_domain_info::data
- *
- * Return: True on success, false otherwise
- *
- * An IMS domain is expected to have the following constraints:
- * - The index space is managed by the core code
- *
- * - There is no requirement for consecutive index ranges
- *
- * - The interrupt chip must provide the following callbacks:
- * - irq_mask()
- * - irq_unmask()
- * - irq_write_msi_msg()
- *
- * - The interrupt chip must provide the following optional callbacks
- * when the irq_mask(), irq_unmask() and irq_write_msi_msg() callbacks
- * cannot operate directly on hardware, e.g. in the case that the
- * interrupt message store is in queue memory:
- * - irq_bus_lock()
- * - irq_bus_unlock()
- *
- * These callbacks are invoked from preemptible task context and are
- * allowed to sleep. In this case the mandatory callbacks above just
- * store the information. The irq_bus_unlock() callback is supposed
- * to make the change effective before returning.
- *
- * - Interrupt affinity setting is handled by the underlying parent
- * interrupt domain and communicated to the IMS domain via
- * irq_write_msi_msg().
- *
- * The domain is automatically destroyed when the PCI device is removed.
- */
-bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
- unsigned int hwsize, void *data)
-{
- struct irq_domain *domain = dev_get_msi_domain(&pdev->dev);
-
- if (!domain || !irq_domain_is_msi_parent(domain))
- return false;
-
- if (template->info.bus_token != DOMAIN_BUS_PCI_DEVICE_IMS ||
- !(template->info.flags & MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS) ||
- !(template->info.flags & MSI_FLAG_FREE_MSI_DESCS) ||
- !template->chip.irq_mask || !template->chip.irq_unmask ||
- !template->chip.irq_write_msi_msg || template->chip.irq_set_affinity)
- return false;
-
- return msi_create_device_irq_domain(&pdev->dev, MSI_SECONDARY_DOMAIN, template,
- hwsize, data, NULL);
-}
-EXPORT_SYMBOL_GPL(pci_create_ims_domain);
-
/*
* Users of the generic MSI infrastructure expect a device to have a single ID,
* so with DMA aliases we have to pick the least-worst compromise. Devices with
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3deb3e42d990..98fb20bcd054 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -2664,11 +2664,6 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
#endif
-struct msi_domain_template;
-
-bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
- unsigned int hwsize, void *data);
-
#include <linux/dma-mapping.h>
#define pci_printk(level, pdev, fmt, arg...) \
--
2.34.1
> From: Bjorn Helgaas <[email protected]>
> Sent: Tuesday, April 2, 2024 7:23 AM
>
> From: Bjorn Helgaas <[email protected]>
>
> This reverts commit 41efa431244f6498833ff8ee8dde28c4924c5479.
>
> IMS (Interrupt Message Store) support appeared in v6.2, but there are no
> users yet.
>
> Remove it for now. We can add it back when a user comes along. If this is
> re-added later, this could be squashed with these commits:
>
> 0194425af0c8 ("PCI/MSI: Provide IMS (Interrupt Message Store) support")
> c9e5bea27383 ("PCI/MSI: Provide pci_ims_alloc/free_irq()")
>
> which added the non-stub implementations.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Kevin Tian <[email protected]>
> From: Bjorn Helgaas <[email protected]>
> Sent: Tuesday, April 2, 2024 7:23 AM
>
> From: Bjorn Helgaas <[email protected]>
>
> This reverts commit 0194425af0c87acaad457989a2c6d90dba58e776.
>
> IMS (Interrupt Message Store) support appeared in v6.2, but there are no
> users yet.
>
> Remove it for now. We can add it back when a user comes along. If this is
> re-added later, the relevant part of 41efa431244f ("PCI/MSI: Provide stubs
> for IMS functions") should be squashed into it.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Kevin Tian <[email protected]>
> From: Bjorn Helgaas <[email protected]>
> Sent: Tuesday, April 2, 2024 7:23 AM
>
> From: Bjorn Helgaas <[email protected]>
>
> IMS (Interrupt Message Store) support appeared in v6.2, but there are no
> users yet.
>
> Remove it for now. We can add it back when a user comes along.
>
> Bjorn Helgaas (3):
> Revert "PCI/MSI: Provide stubs for IMS functions"
> Revert "PCI/MSI: Provide pci_ims_alloc/free_irq()"
> Revert "PCI/MSI: Provide IMS (Interrupt Message Store) support"
>
What about the other IMS related commits which are also dead
code after above are reverted?
fa5745aca1dc ("iommu/amd: Enable PCI/IMS")
810531a1af53 ("iommu/vt-d: Enable PCI/IMS")
6e24c8877329 ("x86/apic/msi: Enable PCI/IMS")
e23d4192bf9b ("genirq/msi: Provide constants for PCI/IMS support")
> From: Bjorn Helgaas <[email protected]>
> Sent: Tuesday, April 2, 2024 7:23 AM
>
> From: Bjorn Helgaas <[email protected]>
>
> This reverts commit c9e5bea273834a63b5e9ba90ad94b305ba50704e.
>
> IMS (Interrupt Message Store) support appeared in v6.2, but there are no
> users yet.
>
> Remove it for now. We can add it back when a user comes along. If this is
> re-added later, the relevant part of 41efa431244f ("PCI/MSI: Provide stubs
> for IMS functions") should be squashed into it.
>
> Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Kevin Tian <[email protected]>
On Tue, Apr 02, 2024 at 02:45:50AM +0000, Tian, Kevin wrote:
> > From: Bjorn Helgaas <[email protected]>
> > Sent: Tuesday, April 2, 2024 7:23 AM
> >
> > From: Bjorn Helgaas <[email protected]>
> >
> > IMS (Interrupt Message Store) support appeared in v6.2, but there are no
> > users yet.
> >
> > Remove it for now. We can add it back when a user comes along.
> >
> > Bjorn Helgaas (3):
> > Revert "PCI/MSI: Provide stubs for IMS functions"
> > Revert "PCI/MSI: Provide pci_ims_alloc/free_irq()"
> > Revert "PCI/MSI: Provide IMS (Interrupt Message Store) support"
> >
>
> What about the other IMS related commits which are also dead
> code after above are reverted?
>
> fa5745aca1dc ("iommu/amd: Enable PCI/IMS")
> 810531a1af53 ("iommu/vt-d: Enable PCI/IMS")
> 6e24c8877329 ("x86/apic/msi: Enable PCI/IMS")
> e23d4192bf9b ("genirq/msi: Provide constants for PCI/IMS support")
Thanks, I didn't catch those; will add in a v2.
Also, sorry for inadvertently sending this in the middle of an
unrelated thread. I copied --in-reply-to from my notes when I
shouldn't have.
Bjorn