2024-04-02 14:34:38

by Frank Li

Subject: [PATCH v3 01/11] PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode

From: Richard Zhu <[email protected]>

Both IMX8MM_EP and IMX8MP_EP have the "IMX6_PCIE_FLAG_HAS_APP_RESET"
set indeed. Otherwise, the LTSSM_EN bit wouldn't be asserted anymore.
That's the root cause that PCIe link is down when i.MX8MM and i.MX8MP
PCIe are in the EP mode.

Fixes: 0c9651c21f2a ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET")
Signed-off-by: Richard Zhu <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 99a60270b26cd..e43eda6b33ca7 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1568,7 +1568,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MM_EP] = {
.variant = IMX8MM_EP,
- .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
+ .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
+ IMX6_PCIE_FLAG_HAS_PHYDRV,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mm-iomuxc-gpr",
.clk_names = imx8mm_clks,
@@ -1579,7 +1580,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
- .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
+ .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
+ IMX6_PCIE_FLAG_HAS_PHYDRV,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mp-iomuxc-gpr",
.clk_names = imx8mm_clks,

--
2.34.1

2024-04-27 09:01:51

by Manivannan Sadhasivam

Subject: Re: [PATCH v3 01/11] PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode

On Tue, Apr 02, 2024 at 10:33:37AM -0400, Frank Li wrote:
> From: Richard Zhu <[email protected]>
>
> Both IMX8MM_EP and IMX8MP_EP have the "IMX6_PCIE_FLAG_HAS_APP_RESET"
> set indeed. Otherwise, the LTSSM_EN bit wouldn't be asserted anymore.
> That's the root cause that PCIe link is down when i.MX8MM and i.MX8MP
> PCIe are in the EP mode.
>

This commit message is difficult to understand. I think the issue you are fixing
is that these 2 SoCs do not control the 'apps_reset', due to which the LTSSM
state is not configured properly.

Referring Link Down is confusing at its best. Is the link training happens first
of all?

- Mani

> Fixes: 0c9651c21f2a ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET")
> Signed-off-by: Richard Zhu <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 99a60270b26cd..e43eda6b33ca7 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1568,7 +1568,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MM_EP] = {
> .variant = IMX8MM_EP,
> - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
> + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> + IMX6_PCIE_FLAG_HAS_PHYDRV,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> .clk_names = imx8mm_clks,
> @@ -1579,7 +1580,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MP_EP] = {
> .variant = IMX8MP_EP,
> - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
> + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> + IMX6_PCIE_FLAG_HAS_PHYDRV,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mp-iomuxc-gpr",
> .clk_names = imx8mm_clks,
>
> --
> 2.34.1
>

--
மணிவண்ணன் சதாசிவம்

2024-04-29 14:53:53

by Frank Li

Subject: Re: [PATCH v3 01/11] PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode

On Sat, Apr 27, 2024 at 02:30:57PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Apr 02, 2024 at 10:33:37AM -0400, Frank Li wrote:
> > From: Richard Zhu <[email protected]>
> >
> > Both IMX8MM_EP and IMX8MP_EP have the "IMX6_PCIE_FLAG_HAS_APP_RESET"
> > set indeed. Otherwise, the LTSSM_EN bit wouldn't be asserted anymore.
> > That's the root cause that PCIe link is down when i.MX8MM and i.MX8MP
> > PCIe are in the EP mode.
> >
>
> This commit message is difficult to understand. I think the issue you are fixing
> is that these 2 SoCs do not control the 'apps_reset', due to which the LTSSM
> state is not configured properly.
>
> Referring Link Down is confusing at its best. Is the link training happens first
> of all?

Commit message is not good enough, how about change to below one

PCI: imx6: Fix iMX8MM and iMX8MP's EP mode failing to establish link

Add IMX6_PCIE_FLAG_HAS_APP_RESET flag to IMX8MM_EP and IMX8MP_EP drvdata.
This was missed during code restructuring. The app-reset from System Reset
Controller needs to be released before starting LTSSM.

Frank

>
> - Mani
>
> > Fixes: 0c9651c21f2a ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET")
> > Signed-off-by: Richard Zhu <[email protected]>
> > Signed-off-by: Frank Li <[email protected]>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 99a60270b26cd..e43eda6b33ca7 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -1568,7 +1568,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > },
> > [IMX8MM_EP] = {
> > .variant = IMX8MM_EP,
> > - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
> > + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> > + IMX6_PCIE_FLAG_HAS_PHYDRV,
> > .mode = DW_PCIE_EP_TYPE,
> > .gpr = "fsl,imx8mm-iomuxc-gpr",
> > .clk_names = imx8mm_clks,
> > @@ -1579,7 +1580,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > },
> > [IMX8MP_EP] = {
> > .variant = IMX8MP_EP,
> > - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
> > + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> > + IMX6_PCIE_FLAG_HAS_PHYDRV,
> > .mode = DW_PCIE_EP_TYPE,
> > .gpr = "fsl,imx8mp-iomuxc-gpr",
> > .clk_names = imx8mm_clks,
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்