Hi,
Changes in v2:
- Addressing comments from Konrad and Dmitry.
- Rebased on top of 6.3-rc1.
This series adds the devicetree support for PCIe PHY and PCIe EP on SDX65.
The PCIe EP is enabled on SDX65 MTP board.
Thanks,
Rohit.
Rohit Agarwal (6):
dt-bindings: mfd: qcom,tcsr: Add compatible for sdx65
dt-bindings: PCI: qcom: Add SDX65 SoC
ARM: dts: qcom: sdx65: Add support for PCIe PHY
ARM: dts: qcom: sdx65: Add support for PCIe EP
ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
.../devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 50 ++++++++++--
arch/arm/boot/dts/qcom-sdx65.dtsi | 92 ++++++++++++++++++++++
4 files changed, 140 insertions(+), 5 deletions(-)
--
2.7.4
Add PCIe EP compatible string for SDX65 SoC.
Signed-off-by: Rohit Agarwal <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 89cfdee..096540b 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -13,6 +13,7 @@ properties:
compatible:
enum:
- qcom,sdx55-pcie-ep
+ - qcom,sdx65-pcie-ep
- qcom,sm8450-pcie-ep
reg:
@@ -109,6 +110,7 @@ allOf:
contains:
enum:
- qcom,sdx55-pcie-ep
+ - qcom,sdx65-pcie-ep
then:
properties:
clocks:
--
2.7.4
Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it,
updating status as last property for each node.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index ed98c83..facb8e2 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -245,13 +245,18 @@
status = "okay";
};
-&qpic_bam {
+&pcie_phy {
+ vdda-phy-supply = <&vreg_l1b_1p2>;
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+
status = "okay";
};
-&qpic_nand {
+&qpic_bam {
status = "okay";
+};
+&qpic_nand {
nand@0 {
reg = <0>;
@@ -262,11 +267,14 @@
secure-regions = /bits/ 64 <0x500000 0x500000
0xa00000 0xb00000>;
};
+
+ status = "okay";
};
&remoteproc_mpss {
- status = "okay";
memory-region = <&mpss_adsp_mem>;
+
+ status = "okay";
};
&usb {
@@ -278,14 +286,16 @@
};
&usb_hsphy {
- status = "okay";
vdda-pll-supply = <&vreg_l4b_0p88>;
vdda33-supply = <&vreg_l10b_3p08>;
vdda18-supply = <&vreg_l5b_1p8>;
+
+ status = "okay";
};
&usb_qmpphy {
- status = "okay";
vdda-phy-supply = <&vreg_l4b_0p88>;
vdda-pll-supply = <&vreg_l1b_1p2>;
+
+ status = "okay";
};
--
2.7.4
Enable PCIe Endpoint controller on the SDX65 MTP board based
on Qualcomm SDX65 platform.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index facb8e2..97459bb 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -245,6 +245,14 @@
status = "okay";
};
+&pcie_ep {
+ pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
+ &pcie_ep_wake_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l1b_1p2>;
vdda-pll-supply = <&vreg_l4b_0p88>;
@@ -277,6 +285,28 @@
status = "okay";
};
+&tlmm {
+ pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie_ep_perst_default: pcie-ep-perst-default-state {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pcie_ep_wake_default: pcie-ep-wake-default-state {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
&usb {
status = "okay";
};
--
2.7.4
Add support for PCIe Endpoint controller on the
Qualcomm SDX65 platform.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 59 +++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index df9d428..5ea6a5a 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
@@ -293,6 +294,59 @@
status = "disabled";
};
+ pcie_ep: pcie-ep@1c00000 {
+ compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
+ reg = <0x01c00000 0x3000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xa8>,
+ <0x40001000 0x1000>,
+ <0x40200000 0x100000>,
+ <0x01c03000 0x3000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "addr_space",
+ "mmio";
+
+ qcom,perst-regs = <&tcsr 0xb258 0xb270>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep",
+ "ref";
+
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global", "doorbell";
+
+ reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "core";
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+
+ max-link-speed = <3>;
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
pcie_phy: phy@1c06000 {
compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
reg = <0x01c06000 0x2000>;
@@ -332,6 +386,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fcb000 {
+ compatible = "qcom,sdx65-tcsr", "syscon";
+ reg = <0x01fc0000 0x1000>;
+ };
+
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sdx55-mpss-pas";
reg = <0x04080000 0x4040>;
--
2.7.4
Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
used by the PCIe EP controller.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 192f9f9..df9d428 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -293,6 +293,39 @@
status = "disabled";
};
+ pcie_phy: phy@1c06000 {
+ compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
+ reg = <0x01c06000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ <&gcc GCC_PCIE_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;
--
2.7.4
On 8.03.2023 13:19, Rohit Agarwal wrote:
> Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
> used by the PCIe EP controller.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 192f9f9..df9d428 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -293,6 +293,39 @@
> status = "disabled";
> };
>
> + pcie_phy: phy@1c06000 {
> + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> + reg = <0x01c06000 0x2000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
No child nodes, please drop this hunk.
Konrad
> + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_EN>,
> + <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> + <&gcc GCC_PCIE_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
> + "pipe";
> +
> + resets = <&gcc GCC_PCIE_PHY_BCR>;
> + reset-names = "phy";
> +
> + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x01f40000 0x40000>;
On 8.03.2023 13:19, Rohit Agarwal wrote:
> Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it,
> updating status as last property for each node.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 20 +++++++++++++++-----
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> index ed98c83..facb8e2 100644
> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> @@ -245,13 +245,18 @@
> status = "okay";
> };
>
> -&qpic_bam {
> +&pcie_phy {
> + vdda-phy-supply = <&vreg_l1b_1p2>;
> + vdda-pll-supply = <&vreg_l4b_0p88>;
> +
> status = "okay";
> };
>
> -&qpic_nand {
> +&qpic_bam {
> status = "okay";
> +};
>
> +&qpic_nand {
> nand@0 {
> reg = <0>;
>
> @@ -262,11 +267,14 @@
> secure-regions = /bits/ 64 <0x500000 0x500000
> 0xa00000 0xb00000>;
> };
> +
> + status = "okay";
Did you compiletest this?
Konrad
> };
>
> &remoteproc_mpss {
> - status = "okay";
> memory-region = <&mpss_adsp_mem>;
> +
> + status = "okay";
> };
>
> &usb {
> @@ -278,14 +286,16 @@
> };
>
> &usb_hsphy {
> - status = "okay";
> vdda-pll-supply = <&vreg_l4b_0p88>;
> vdda33-supply = <&vreg_l10b_3p08>;
> vdda18-supply = <&vreg_l5b_1p8>;
> +
> + status = "okay";
> };
>
> &usb_qmpphy {
> - status = "okay";
> vdda-phy-supply = <&vreg_l4b_0p88>;
> vdda-pll-supply = <&vreg_l1b_1p2>;
> +
> + status = "okay";
> };
On 3/8/2023 6:08 PM, Konrad Dybcio wrote:
>
> On 8.03.2023 13:19, Rohit Agarwal wrote:
>> Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it,
>> updating status as last property for each node.
>>
>> Signed-off-by: Rohit Agarwal <[email protected]>
>> ---
>> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 20 +++++++++++++++-----
>> 1 file changed, 15 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> index ed98c83..facb8e2 100644
>> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> @@ -245,13 +245,18 @@
>> status = "okay";
>> };
>>
>> -&qpic_bam {
>> +&pcie_phy {
>> + vdda-phy-supply = <&vreg_l1b_1p2>;
>> + vdda-pll-supply = <&vreg_l4b_0p88>;
>> +
>> status = "okay";
>> };
>>
>> -&qpic_nand {
>> +&qpic_bam {
>> status = "okay";
>> +};
>>
>> +&qpic_nand {
>> nand@0 {
>> reg = <0>;
>>
>> @@ -262,11 +267,14 @@
>> secure-regions = /bits/ 64 <0x500000 0x500000
>> 0xa00000 0xb00000>;
>> };
>> +
>> + status = "okay";
> Did you compiletest this?
So Sorry, Missed some of the patches for compiletest.
Will update immediately.
Thanks,
Rohit.
>
> Konrad
>> };
>>
>> &remoteproc_mpss {
>> - status = "okay";
>> memory-region = <&mpss_adsp_mem>;
>> +
>> + status = "okay";
>> };
>>
>> &usb {
>> @@ -278,14 +286,16 @@
>> };
>>
>> &usb_hsphy {
>> - status = "okay";
>> vdda-pll-supply = <&vreg_l4b_0p88>;
>> vdda33-supply = <&vreg_l10b_3p08>;
>> vdda18-supply = <&vreg_l5b_1p8>;
>> +
>> + status = "okay";
>> };
>>
>> &usb_qmpphy {
>> - status = "okay";
>> vdda-phy-supply = <&vreg_l4b_0p88>;
>> vdda-pll-supply = <&vreg_l1b_1p2>;
>> +
>> + status = "okay";
>> };
Hi Rohit,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on lee-mfd/for-mfd-next lee-mfd/for-mfd-fixes pci/next pci/for-linus linus/master v6.3-rc1 next-20230310]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Rohit-Agarwal/dt-bindings-mfd-qcom-tcsr-Add-compatible-for-sdx65/20230308-202140
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/1678277993-18836-4-git-send-email-quic_rohiagar%40quicinc.com
patch subject: [PATCH v2 3/6] ARM: dts: qcom: sdx65: Add support for PCIe PHY
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20230311/[email protected]/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ca67929d838c65d39536e65c284da94928f55786
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Rohit-Agarwal/dt-bindings-mfd-qcom-tcsr-Add-compatible-for-sdx65/20230308-202140
git checkout ca67929d838c65d39536e65c284da94928f55786
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/qcom-sdx65.dtsi:306.6-7 syntax error
FATAL ERROR: Unable to parse input tree
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
On 08/03/2023 14:19, Rohit Agarwal wrote:
> Add support for PCIe Endpoint controller on the
> Qualcomm SDX65 platform.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 59 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index df9d428..5ea6a5a 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> #address-cells = <1>;
> @@ -293,6 +294,59 @@
> status = "disabled";
> };
>
> + pcie_ep: pcie-ep@1c00000 {
> + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
> + reg = <0x01c00000 0x3000>,
> + <0x40000000 0xf1d>,
> + <0x40000f20 0xa8>,
> + <0x40001000 0x1000>,
> + <0x40200000 0x100000>,
> + <0x01c03000 0x3000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "addr_space",
> + "mmio";
> +
> + qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> +
> + clocks = <&gcc GCC_PCIE_AUX_CLK>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_PCIE_SLEEP_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "sleep",
> + "ref";
> +
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "global", "doorbell";
> +
> + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
-gpios should go to the board file too.
> +
> + resets = <&gcc GCC_PCIE_BCR>;
> + reset-names = "core";
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + phys = <&pcie_phy>;
> + phy-names = "pcie-phy";
> +
> + max-link-speed = <3>;
> + num-lanes = <2>;
> +
> + status = "disabled";
> + };
> +
> pcie_phy: phy@1c06000 {
> compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> reg = <0x01c06000 0x2000>;
> @@ -332,6 +386,11 @@
> #hwlock-cells = <1>;
> };
>
> + tcsr: syscon@1fcb000 {
> + compatible = "qcom,sdx65-tcsr", "syscon";
> + reg = <0x01fc0000 0x1000>;
> + };
> +
> remoteproc_mpss: remoteproc@4080000 {
> compatible = "qcom,sdx55-mpss-pas";
> reg = <0x04080000 0x4040>;
--
With best wishes
Dmitry