sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <[email protected]>
---
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
index 83bcf9fe0152..20caf40b4755 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -220,7 +220,8 @@ qspi1_flash: flash@0 {
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <80000000>;
+ spi-max-frequency = <104000000>;
+ spi-cs-setup-ns = /bits/ 16 <7>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
--
2.25.1
Hi Tudor,
On 17/11/2022 at 11:52, Tudor Ambarus wrote:
> sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
> operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
> at 3.3V, increase its maximum supported frequency to 104MHz. The
> increasing of the spi-max-frequency value requires the setting of the
> "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
>
> The sst26vf064b datasheet specifies just a minimum value for the
> "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
> maximum time specified. I determined experimentally that 5 ns for the
> spi-cs-setup-ns is not enough when the flash is operated close to its
> maximum frequency and tests showed that 7 ns is just fine, so set the
> spi-cs-setup-ns dt property to 7.
>
> With the increase of frequency the reads are now faster with ~37%.
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
> index 83bcf9fe0152..20caf40b4755 100644
> --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
> +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
> @@ -220,7 +220,8 @@ qspi1_flash: flash@0 {
> #size-cells = <1>;
> compatible = "jedec,spi-nor";
> reg = <0>;
> - spi-max-frequency = <80000000>;
> + spi-max-frequency = <104000000>;
> + spi-cs-setup-ns = /bits/ 16 <7>;
Following the different changes that happened to this property after
this post, am I right saying that this must now be changed to:
spi-cs-setup-delay-ns = <7>;
?
Thanks for your insight. Best regards,
Nicolas
> spi-rx-bus-width = <4>;
> spi-tx-bus-width = <4>;
> m25p,fast-read;
--
Nicolas Ferre
On 3/28/23 09:51, Nicolas Ferre wrote:
> Hi Tudor,
Hi!
>
> On 17/11/2022 at 11:52, Tudor Ambarus wrote:
>> sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
>> operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
>> at 3.3V, increase its maximum supported frequency to 104MHz. The
>> increasing of the spi-max-frequency value requires the setting of the
>> "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
>>
>> The sst26vf064b datasheet specifies just a minimum value for the
>> "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
>> maximum time specified. I determined experimentally that 5 ns for the
>> spi-cs-setup-ns is not enough when the flash is operated close to its
>> maximum frequency and tests showed that 7 ns is just fine, so set the
>> spi-cs-setup-ns dt property to 7.
>>
>> With the increase of frequency the reads are now faster with ~37%.
>>
>> Signed-off-by: Tudor Ambarus <[email protected]>
>> ---
>> arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
>> b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
>> index 83bcf9fe0152..20caf40b4755 100644
>> --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
>> +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
>> @@ -220,7 +220,8 @@ qspi1_flash: flash@0 {
>> #size-cells = <1>;
>> compatible = "jedec,spi-nor";
>> reg = <0>;
>> - spi-max-frequency = <80000000>;
>> + spi-max-frequency = <104000000>;
>> + spi-cs-setup-ns = /bits/ 16 <7>;
>
> Following the different changes that happened to this property after
> this post, am I right saying that this must now be changed to:
>
> spi-cs-setup-delay-ns = <7>;
>
> ?
>
Yes, that should do it. I'm amending the series right now. Can you do a
little test on your side so that we make sure everything is in place?
After the update, something like that should be run on any board (maybe
wlsom1-ek?):
#!/bin/sh
dd if=/dev/urandom of=./qspi_test bs=1M count=6
mtd_debug write /dev/mtd5 0 6291456 qspi_test
mtd_debug erase /dev/mtd5 0 6291456
mtd_debug read /dev/mtd5 0 6291456 qspi_read
hexdump qspi_read
mtd_debug write /dev/mtd5 0 6291456 qspi_test
mtd_debug read /dev/mtd5 0 6291456 qspi_read
sha1sum qspi_test qspi_read
brb,
ta