Patches [3], [4] and [5] depend on [1], [2] to be merged first. So, adding
the cleanup patches also to this series.
[v6]
* Add [1], [2] to handle the regmap overlap of lpasscc and lpass_aon
[v5]
* Fix the fail path and add pm_runtime_disable().
[v4]
* Fix the "fixes" tag.
[v3]
* Remove the maxItems from reg property.
[v2]
* Update/fix the YAML for reg property against each compatible.
[v1]
* Add support for clock gating resets for lpass audio clock
controller & MCLKs.
Satya Priya (2):
dt-bindings: clock: Add "qcom,adsp-pil-mode" property
clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon
Taniya Das (3):
dt-bindings: clock: Add resets for LPASS audio clock controller for
SC7280
dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280
clk: qcom: lpass: Add support for resets & external mclk for SC7280
.../bindings/clock/qcom,sc7280-lpasscc.yaml | 6 +-
.../bindings/clock/qcom,sc7280-lpasscorecc.yaml | 26 ++++++++-
drivers/clk/qcom/lpassaudiocc-sc7280.c | 66 +++++++++++++++++++++-
drivers/clk/qcom/lpasscc-sc7280.c | 44 ---------------
drivers/clk/qcom/lpasscorecc-sc7280.c | 33 +++++++++++
.../dt-bindings/clock/qcom,lpassaudiocc-sc7280.h | 5 ++
.../dt-bindings/clock/qcom,lpasscorecc-sc7280.h | 2 +
7 files changed, 130 insertions(+), 52 deletions(-)
--
2.7.4
Move registration of lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk to
lpass_aon_cc_sc7280_probe and register them only if "qcom,adsp-pil-mode"
is enabled in the lpass_aon DT node.
Signed-off-by: Satya Priya <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/lpassaudiocc-sc7280.c | 44 ++++++++++++++++++++++++++++++++++
drivers/clk/qcom/lpasscc-sc7280.c | 44 ----------------------------------
2 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 6ab6e5a3..6067328 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -12,6 +12,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <dt-bindings/clock/qcom,lpass-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include "clk-alpha-pll.h"
@@ -38,6 +39,32 @@ static const struct pll_vco zonda_vco[] = {
{ 595200000UL, 3600000000UL, 0 },
};
+static struct clk_branch lpass_q6ss_ahbm_clk = {
+ .halt_reg = 0x901c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x901c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "lpass_q6ss_ahbm_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch lpass_q6ss_ahbs_clk = {
+ .halt_reg = 0x9020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "lpass_q6ss_ahbs_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
/* 1128.96MHz configuration */
static const struct alpha_pll_config lpass_audio_cc_pll_config = {
.l = 0x3a,
@@ -614,6 +641,11 @@ static struct gdsc lpass_aon_cc_lpass_audio_hm_gdsc = {
.flags = RETAIN_FF_ENABLE,
};
+static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
+ [LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
+ [LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
+};
+
static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] = {
[LPASS_AON_CC_AUDIO_HM_H_CLK] = &lpass_aon_cc_audio_hm_h_clk.clkr,
[LPASS_AON_CC_VA_MEM0_CLK] = &lpass_aon_cc_va_mem0_clk.clkr,
@@ -659,6 +691,12 @@ static struct regmap_config lpass_audio_cc_sc7280_regmap_config = {
.fast_io = true,
};
+static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
+ .config = &lpass_audio_cc_sc7280_regmap_config,
+ .clks = lpass_cc_sc7280_clocks,
+ .num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
+};
+
static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.clks = lpass_audio_cc_sc7280_clocks,
@@ -785,6 +823,12 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
if (ret)
return ret;
+ if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
+ lpass_audio_cc_sc7280_regmap_config.name = "cc";
+ desc = &lpass_cc_sc7280_desc;
+ return qcom_cc_probe(pdev, desc);
+ }
+
lpass_audio_cc_sc7280_regmap_config.name = "lpasscc_aon";
lpass_audio_cc_sc7280_regmap_config.max_register = 0xa0008;
desc = &lpass_aon_cc_sc7280_desc;
diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index b39ee1c..5c1e17b 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -17,32 +17,6 @@
#include "clk-branch.h"
#include "common.h"
-static struct clk_branch lpass_q6ss_ahbm_clk = {
- .halt_reg = 0x1c,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x1c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "lpass_q6ss_ahbm_clk",
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch lpass_q6ss_ahbs_clk = {
- .halt_reg = 0x20,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x20,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "lpass_q6ss_ahbs_clk",
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
.halt_reg = 0x0,
.halt_check = BRANCH_HALT,
@@ -105,17 +79,6 @@ static struct regmap_config lpass_regmap_config = {
.fast_io = true,
};
-static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
- [LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
- [LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
-};
-
-static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
- .config = &lpass_regmap_config,
- .clks = lpass_cc_sc7280_clocks,
- .num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
-};
-
static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
[LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
&lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
@@ -169,13 +132,6 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
if (ret)
goto destroy_pm_clk;
- lpass_regmap_config.name = "cc";
- desc = &lpass_cc_sc7280_desc;
-
- ret = qcom_cc_probe_by_index(pdev, 2, desc);
- if (ret)
- goto destroy_pm_clk;
-
return 0;
destroy_pm_clk:
--
2.7.4
From: Taniya Das <[email protected]>
The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks.
Also add the external mclk to interface external MI2S.
Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280").
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/lpassaudiocc-sc7280.c | 22 +++++++++++++++++++++-
drivers/clk/qcom/lpasscorecc-sc7280.c | 33 +++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 6067328..063e036 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -23,6 +23,7 @@
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
+#include "reset.h"
enum {
P_BI_TCXO,
@@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
.parent_data = lpass_aon_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -703,6 +704,18 @@ static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
.num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
};
+static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
+ [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
+ [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
+ [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
+};
+
+static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
+ .config = &lpass_audio_cc_sc7280_regmap_config,
+ .resets = lpass_audio_cc_sc7280_resets,
+ .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
+};
+
static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpassaudiocc" },
{ }
@@ -779,6 +792,13 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
return ret;
}
+ ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n");
+ pm_runtime_disable(&pdev->dev);
+ return ret;
+ }
+
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
index 1f1f1bd..6ad19b0 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7280.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
@@ -190,6 +190,19 @@ static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
},
};
+static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = {
+ .cmd_rcgr = 0x20000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = lpass_core_cc_parent_map_0,
+ .freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "lpass_core_cc_ext_mclk0_clk_src",
+ .parent_data = lpass_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
static struct clk_branch lpass_core_cc_core_clk = {
.halt_reg = 0x1f000,
@@ -283,6 +296,24 @@ static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
},
};
+static struct clk_branch lpass_core_cc_ext_mclk0_clk = {
+ .halt_reg = 0x20014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x20014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "lpass_core_cc_ext_mclk0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &lpass_core_cc_ext_mclk0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
@@ -326,6 +357,8 @@ static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
[LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
[LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
[LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
+ [LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr,
+ [LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr,
};
static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
--
2.7.4
From: Taniya Das <[email protected]>
Support external mclk to interface external MI2S clocks for SC7280.
Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280").
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
index 28ed2a0..0324c69 100644
--- a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
@@ -19,6 +19,8 @@
#define LPASS_CORE_CC_LPM_CORE_CLK 9
#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10
#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11
+#define LPASS_CORE_CC_EXT_MCLK0_CLK 12
+#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 13
/* LPASS_CORE_CC power domains */
#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0
--
2.7.4
From: Taniya Das <[email protected]>
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for SC7280. Update reg property min/max items in YAML schema.
Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280").
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
---
.../bindings/clock/qcom,sc7280-lpasscorecc.yaml | 19 ++++++++++++++++---
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h | 5 +++++
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
index 5ccfb24..f50e284 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -22,6 +22,8 @@ properties:
clock-names: true
+ reg: true
+
compatible:
enum:
- qcom,sc7280-lpassaoncc
@@ -38,8 +40,8 @@ properties:
'#power-domain-cells':
const: 1
- reg:
- maxItems: 1
+ '#reset-cells':
+ const: 1
qcom,adsp-pil-mode:
description:
@@ -75,6 +77,11 @@ allOf:
items:
- const: bi_tcxo
- const: lpass_aon_cc_main_rcg_clk_src
+
+ reg:
+ items:
+ - description: lpass core cc register
+ - description: lpass audio csr register
- if:
properties:
compatible:
@@ -96,6 +103,8 @@ allOf:
- const: bi_tcxo_ao
- const: iface
+ reg:
+ maxItems: 1
- if:
properties:
compatible:
@@ -114,6 +123,8 @@ allOf:
items:
- const: bi_tcxo
+ reg:
+ maxItems: 1
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -122,13 +133,15 @@ examples:
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
- reg = <0x3300000 0x30000>;
+ reg = <0x3300000 0x30000>,
+ <0x32a9000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+ #reset-cells = <1>;
};
- |
diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
index 20ef2ea..22dcd47 100644
--- a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
@@ -24,6 +24,11 @@
#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
+/* LPASS AUDIO CC CSR */
+#define LPASS_AUDIO_SWR_RX_CGCR 0
+#define LPASS_AUDIO_SWR_TX_CGCR 1
+#define LPASS_AUDIO_SWR_WSA_CGCR 2
+
/* LPASS_AON_CC clocks */
#define LPASS_AON_CC_PLL 0
#define LPASS_AON_CC_PLL_OUT_EVEN 1
--
2.7.4
The LPASS Peripheral loader clocks would be used to bring
LPASS out of reset, when this property is present.
This is a cleanup done to handle overlap of regmap of
lpasscc and lpass_aon blocks. As a part of this, remove
the "cc" regmap from lpasscc node.
Signed-off-by: Satya Priya <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++----
.../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++++++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 47028d7..633887d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -36,13 +36,11 @@ properties:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
- - description: LPASS cc register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
- - const: cc
required:
- compatible
@@ -59,8 +57,8 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
- reg-names = "qdsp6ss", "top_cc", "cc";
+ reg = <0x03000000 0x40>, <0x03c04000 0x4>;
+ reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
index bad9135..5ccfb24 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -41,6 +41,12 @@ properties:
reg:
maxItems: 1
+ qcom,adsp-pil-mode:
+ description:
+ Indicates if the LPASS would be brought out of reset using
+ peripheral loader.
+ type: boolean
+
required:
- compatible
- reg
@@ -165,6 +171,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
+ qcom,adsp-pil-mode;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
--
2.7.4
On Wed, 20 Jul 2022 16:33:39 +0530, Satya Priya wrote:
> The LPASS Peripheral loader clocks would be used to bring
> LPASS out of reset, when this property is present.
>
> This is a cleanup done to handle overlap of regmap of
> lpasscc and lpass_aon blocks. As a part of this, remove
> the "cc" regmap from lpasscc node.
>
> Signed-off-by: Satya Priya <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++----
> .../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++++++
> 2 files changed, 9 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
Quoting Satya Priya (2022-07-20 04:03:39)
> The LPASS Peripheral loader clocks would be used to bring
> LPASS out of reset, when this property is present.
>
> This is a cleanup done to handle overlap of regmap of
> lpasscc and lpass_aon blocks. As a part of this, remove
> the "cc" regmap from lpasscc node.
>
> Signed-off-by: Satya Priya <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> ---
Found it! Can you mention dependencies between patch series?
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Satya Priya (2022-07-20 04:03:40)
> Move registration of lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk to
> lpass_aon_cc_sc7280_probe and register them only if "qcom,adsp-pil-mode"
> is enabled in the lpass_aon DT node.
>
> Signed-off-by: Satya Priya <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Satya Priya (2022-07-20 04:03:43)
> From: Taniya Das <[email protected]>
>
> The clock gating control for TX/RX/WSA core bus clocks would be required
> to be reset(moved from hardware control) from audio core driver. Thus
> add the support for the reset clocks.
>
> Also add the external mclk to interface external MI2S.
>
> Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280").
> Signed-off-by: Taniya Das <[email protected]>
> ---
> drivers/clk/qcom/lpassaudiocc-sc7280.c | 22 +++++++++++++++++++++-
> drivers/clk/qcom/lpasscorecc-sc7280.c | 33 +++++++++++++++++++++++++++++++++
> 2 files changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
> index 6067328..063e036 100644
> --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
> +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
> @@ -23,6 +23,7 @@
> #include "clk-regmap-mux.h"
> #include "common.h"
> #include "gdsc.h"
> +#include "reset.h"
>
> enum {
> P_BI_TCXO,
> @@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
> .parent_data = lpass_aon_cc_parent_data_0,
> .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
> .flags = CLK_OPS_PARENT_ENABLE,
> - .ops = &clk_rcg2_ops,
> + .ops = &clk_rcg2_shared_ops,
This diff isn't mentioned in the commit text at all. Is it intentional?
If so, please mention why it needs to change.
Quoting Satya Priya (2022-07-20 04:03:41)
> From: Taniya Das <[email protected]>
>
> Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
> for SC7280. Update reg property min/max items in YAML schema.
>
> Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280").
> Acked-by: Rob Herring <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Satya Priya (2022-07-20 04:03:41)
> From: Taniya Das <[email protected]>
>
> Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
> for SC7280. Update reg property min/max items in YAML schema.
>
> Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280").
BTW, that period at the end of the fixes line should be removed.
On 7/27/2022 7:01 AM, Stephen Boyd wrote:
> Quoting Satya Priya (2022-07-20 04:03:43)
>> From: Taniya Das <[email protected]>
>>
>> The clock gating control for TX/RX/WSA core bus clocks would be required
>> to be reset(moved from hardware control) from audio core driver. Thus
>> add the support for the reset clocks.
>>
>> Also add the external mclk to interface external MI2S.
>>
>> Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280").
>> Signed-off-by: Taniya Das <[email protected]>
>> ---
>> drivers/clk/qcom/lpassaudiocc-sc7280.c | 22 +++++++++++++++++++++-
>> drivers/clk/qcom/lpasscorecc-sc7280.c | 33 +++++++++++++++++++++++++++++++++
>> 2 files changed, 54 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
>> index 6067328..063e036 100644
>> --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
>> +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
>> @@ -23,6 +23,7 @@
>> #include "clk-regmap-mux.h"
>> #include "common.h"
>> #include "gdsc.h"
>> +#include "reset.h"
>>
>> enum {
>> P_BI_TCXO,
>> @@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
>> .parent_data = lpass_aon_cc_parent_data_0,
>> .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
>> .flags = CLK_OPS_PARENT_ENABLE,
>> - .ops = &clk_rcg2_ops,
>> + .ops = &clk_rcg2_shared_ops,
> This diff isn't mentioned in the commit text at all. Is it intentional?
> If so, please mention why it needs to change.
It is updated to park the RCG at XO after disable as this clock signal
is used by hardware to turn ON memories in LPASS. I'll mention this in
the commit text.
On 7/27/2022 7:00 AM, Stephen Boyd wrote:
> Quoting Satya Priya (2022-07-20 04:03:41)
>> From: Taniya Das <[email protected]>
>>
>> Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
>> for SC7280. Update reg property min/max items in YAML schema.
>>
>> Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280").
> BTW, that period at the end of the fixes line should be removed.
Okay.