2015-05-19 00:00:54

by Thomas Gleixner

Subject: [patch 2/6] x86, perf, cqm: Use proper data type

int is really not a proper data type for a MSR. Use u32 to make it
clear that we are dealing with a 32bit unsigned hardware value.

Signed-off-by: Thomas Gleixner <[email protected]>
---
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 4 ++--
include/linux/perf_event.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)

Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -18,7 +18,7 @@ static unsigned int cqm_l3_scale; /* sup

struct intel_cqm_state {
raw_spinlock_t lock;
- int rmid;
+ u32 rmid;
int cnt;
};

@@ -962,7 +962,7 @@ out:
static void intel_cqm_event_start(struct perf_event *event, int mode)
{
struct intel_cqm_state *state = this_cpu_ptr(&cqm_state);
- unsigned int rmid = event->hw.cqm_rmid;
+ u32 rmid = event->hw.cqm_rmid;
unsigned long flags;

if (!(event->hw.cqm_state & PERF_HES_STOPPED))
Index: linux/include/linux/perf_event.h
===================================================================
--- linux.orig/include/linux/perf_event.h
+++ linux/include/linux/perf_event.h
@@ -124,7 +124,7 @@ struct hw_perf_event {
};
struct { /* intel_cqm */
int cqm_state;
- int cqm_rmid;
+ u32 cqm_rmid;
struct list_head cqm_events_entry;
struct list_head cqm_groups_entry;
struct list_head cqm_group_entry;

2015-05-19 08:58:15

by Matt Fleming

Subject: Re: [patch 2/6] x86, perf, cqm: Use proper data type

On Tue, 19 May, at 12:00:51AM, Thomas Gleixner wrote:
> int is really not a proper data type for a MSR. Use u32 to make it
> clear that we are dealing with a 32bit unsigned hardware value.
>
> Signed-off-by: Thomas Gleixner <[email protected]>
> ---
> arch/x86/kernel/cpu/perf_event_intel_cqm.c | 4 ++--
> include/linux/perf_event.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)

Yeah, makes sense, but this is missing a bunch of changes to other
functions that pass rmids around.

Lemme take a swing at that.

--
Matt Fleming, Intel Open Source Technology Center

2015-05-19 13:03:32

by Thomas Gleixner

Subject: Re: [patch 2/6] x86, perf, cqm: Use proper data type

On Tue, 19 May 2015, Matt Fleming wrote:

> On Tue, 19 May, at 12:00:51AM, Thomas Gleixner wrote:
> > int is really not a proper data type for a MSR. Use u32 to make it
> > clear that we are dealing with a 32bit unsigned hardware value.
> >
> > Signed-off-by: Thomas Gleixner <[email protected]>
> > ---
> > arch/x86/kernel/cpu/perf_event_intel_cqm.c | 4 ++--
> > include/linux/perf_event.h | 2 +-
> > 2 files changed, 3 insertions(+), 3 deletions(-)
>
> Yeah, makes sense, but this is missing a bunch of changes to other
> functions that pass rmids around.

Right. I cared about the stuff which handles the cached state.

> Lemme take a swing at that.

Yes, please.

Thanks,

tglx