Hi,
This patchset introduces a couple of xdma driver enhancements. The most
important change is the introduction of interleaved DMA transfers
feature, which is a big deal, as it allows DMAEngine clients to express
DMA transfers in an arbitrary way. This is extremely useful in FPGA
environments, where in one FPGA system there may be a need to do DMA both
to/from FIFO at a fixed address and to/from a (non)contiguous RAM.
It is a another reroll of my previous patch series [1], but it is heavily
modified one as it is based on Miquel's patchset [2]. We agreed on doing
it that way, as both our patchsets touched the very same piece of code.
The discussion took place under [2] thread.
I tested it with XDMA v4.1 (Rev.20) IP core, with both sg and
interleaved DMA transfers.
Jan
Changes since v1:
[PATCH 1/5]:
Complete a terminated descriptor with dma_cookie_complete()
Don't reinitialize temporary list head in xdma_terminate_all()
[PATCH 4/5]:
Fix incorrect text wrapping
Changes since v2:
[PATCH 1/5]:
DO NOT schedule callback from within xdma_terminate_all()
Changes since v3:
Base patchset on Miquel's [2] series
Reorganize commits` structure
Introduce interleaved DMA transfers feature
Implement transfer error reporting
Changes since v4:
Get rid of duplicated line of code
Fix various coding style issues
[1]:
https://lore.kernel.org/dmaengine/[email protected]/T/#t
[2]:
https://lore.kernel.org/dmaengine/[email protected]/T/#t
---
Jan Kuliga (8):
dmaengine: xilinx: xdma: Get rid of unused code
dmaengine: xilinx: xdma: Add necessary macro definitions
dmaengine: xilinx: xdma: Ease dma_pool alignment requirements
dmaengine: xilinx: xdma: Rework xdma_terminate_all()
dmaengine: xilinx: xdma: Add error checking in xdma_channel_isr()
dmaengine: xilinx: xdma: Add transfer error reporting
dmaengine: xilinx: xdma: Prepare the introduction of interleaved DMA
transfers
dmaengine: xilinx: xdma: Implement interleaved DMA transfers
drivers/dma/xilinx/xdma-regs.h | 30 ++--
drivers/dma/xilinx/xdma.c | 283 +++++++++++++++++++++++----------
2 files changed, 210 insertions(+), 103 deletions(-)
--
2.34.1
Verified this patch series with our device (sg interface)
Thanks,
Lizhi
On 12/18/23 03:39, Jan Kuliga wrote:
> Hi,
>
> This patchset introduces a couple of xdma driver enhancements. The most
> important change is the introduction of interleaved DMA transfers
> feature, which is a big deal, as it allows DMAEngine clients to express
> DMA transfers in an arbitrary way. This is extremely useful in FPGA
> environments, where in one FPGA system there may be a need to do DMA both
> to/from FIFO at a fixed address and to/from a (non)contiguous RAM.
>
> It is a another reroll of my previous patch series [1], but it is heavily
> modified one as it is based on Miquel's patchset [2]. We agreed on doing
> it that way, as both our patchsets touched the very same piece of code.
> The discussion took place under [2] thread.
>
> I tested it with XDMA v4.1 (Rev.20) IP core, with both sg and
> interleaved DMA transfers.
>
> Jan
>
> Changes since v1:
> [PATCH 1/5]:
> Complete a terminated descriptor with dma_cookie_complete()
> Don't reinitialize temporary list head in xdma_terminate_all()
> [PATCH 4/5]:
> Fix incorrect text wrapping
>
> Changes since v2:
> [PATCH 1/5]:
> DO NOT schedule callback from within xdma_terminate_all()
>
> Changes since v3:
> Base patchset on Miquel's [2] series
> Reorganize commits` structure
> Introduce interleaved DMA transfers feature
> Implement transfer error reporting
>
> Changes since v4:
> Get rid of duplicated line of code
> Fix various coding style issues
>
> [1]:
> https://lore.kernel.org/dmaengine/[email protected]/T/#t
>
> [2]:
> https://lore.kernel.org/dmaengine/[email protected]/T/#t
>
> ---
> Jan Kuliga (8):
> dmaengine: xilinx: xdma: Get rid of unused code
> dmaengine: xilinx: xdma: Add necessary macro definitions
> dmaengine: xilinx: xdma: Ease dma_pool alignment requirements
> dmaengine: xilinx: xdma: Rework xdma_terminate_all()
> dmaengine: xilinx: xdma: Add error checking in xdma_channel_isr()
> dmaengine: xilinx: xdma: Add transfer error reporting
> dmaengine: xilinx: xdma: Prepare the introduction of interleaved DMA
> transfers
> dmaengine: xilinx: xdma: Implement interleaved DMA transfers
>
> drivers/dma/xilinx/xdma-regs.h | 30 ++--
> drivers/dma/xilinx/xdma.c | 283 +++++++++++++++++++++++----------
> 2 files changed, 210 insertions(+), 103 deletions(-)
>
On Mon, 18 Dec 2023 12:39:04 +0100, Jan Kuliga wrote:
> This patchset introduces a couple of xdma driver enhancements. The most
> important change is the introduction of interleaved DMA transfers
> feature, which is a big deal, as it allows DMAEngine clients to express
> DMA transfers in an arbitrary way. This is extremely useful in FPGA
> environments, where in one FPGA system there may be a need to do DMA both
> to/from FIFO at a fixed address and to/from a (non)contiguous RAM.
>
> [...]
Applied, thanks!
[1/8] dmaengine: xilinx: xdma: Get rid of unused code
commit: 6e2387183312cdfce6326b2626c0b801c2ffe686
[2/8] dmaengine: xilinx: xdma: Add necessary macro definitions
commit: 7a9c7f46bd0abea214d96f00f78622f24c798ad8
[3/8] dmaengine: xilinx: xdma: Ease dma_pool alignment requirements
commit: e5bc76b0e1c54906ca744ed1a7872f4f407d5d2e
[4/8] dmaengine: xilinx: xdma: Rework xdma_terminate_all()
commit: 2e142cebb1645ac18db1e66f0c30a8d720d00c0b
[5/8] dmaengine: xilinx: xdma: Add error checking in xdma_channel_isr()
commit: c38d055a7c021145ab3a07cf69992d287440c4cb
[6/8] dmaengine: xilinx: xdma: Add transfer error reporting
commit: c3fcb6f5575fcfd240baa339319d2a42d137cd8e
[7/8] dmaengine: xilinx: xdma: Prepare the introduction of interleaved DMA transfers
commit: fa88abfd0d03fea8b800ff1df4f161c804d24c8a
[8/8] dmaengine: xilinx: xdma: Implement interleaved DMA transfers
commit: 01e6d907656134949c4126e7fd64984d4daa4c1e
Best regards,
--
~Vinod