This series adds support for OSPI version of Cadence QSPI controller IP.
Tested with AM654 EVM with MT35x512 Octal flash
Changes:
v4:
Fix comments on v3 by Tudor.
Rebase on top latest linux-next(all dependencies are now part of -next)
v3:
Rebase on top of v7 of Yogesh's series[1]
v2:
spi-nor core patches dropped, are now part of Yogesh's series [1]
Declare Octal mode capability based on compatible.
Vignesh R (2):
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
.../bindings/mtd/cadence-quadspi.txt | 1 +
drivers/mtd/spi-nor/cadence-quadspi.c | 53 ++++++++++++++-----
2 files changed, 42 insertions(+), 12 deletions(-)
--
2.20.1
Cadence OSPI controller IP supports Octal IO (x8 IO lines),
It also has an integrated PHY. IP register layout is very
similar to existing QSPI IP except for additional bits to support Octal
and Octal DDR mode. Therefore, extend current driver to support Octal
mode. Only Octal SDR read (1-1-8)mode is supported for now.
Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
Signed-off-by: Vignesh R <[email protected]>
---
v4: Fix comments by Tudor on v3
v3: No changes
v2: Declare Octal mode capability based on compatible.
drivers/mtd/spi-nor/cadence-quadspi.c | 53 +++++++++++++++++++++------
1 file changed, 41 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 04cedd3a2bf6..2091addc45a3 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -44,6 +44,12 @@
/* Quirks */
#define CQSPI_NEEDS_WR_DELAY BIT(0)
+/* Capabilities mask */
+#define cqspi_base_hwcaps_mask \
+ (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \
+ SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \
+ SNOR_HWCAPS_PP)
+
struct cqspi_st;
struct cqspi_flash_pdata {
@@ -93,6 +99,11 @@ struct cqspi_st {
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
};
+struct cqspi_driver_platdata {
+ u32 hwcaps_mask;
+ u8 quirks;
+};
+
/* Operation timeout value */
#define CQSPI_TIMEOUT_MS 500
#define CQSPI_READ_TIMEOUT_MS 10
@@ -101,6 +112,7 @@ struct cqspi_st {
#define CQSPI_INST_TYPE_SINGLE 0
#define CQSPI_INST_TYPE_DUAL 1
#define CQSPI_INST_TYPE_QUAD 2
+#define CQSPI_INST_TYPE_OCTAL 3
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
@@ -911,6 +923,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
case SNOR_PROTO_1_1_4:
f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
break;
+ case SNOR_PROTO_1_1_8:
+ f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
+ break;
default:
return -EINVAL;
}
@@ -1213,21 +1228,22 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
{
- const struct spi_nor_hwcaps hwcaps = {
- .mask = SNOR_HWCAPS_READ |
- SNOR_HWCAPS_READ_FAST |
- SNOR_HWCAPS_READ_1_1_2 |
- SNOR_HWCAPS_READ_1_1_4 |
- SNOR_HWCAPS_PP,
- };
struct platform_device *pdev = cqspi->pdev;
struct device *dev = &pdev->dev;
+ const struct cqspi_driver_platdata *ddata;
+ struct spi_nor_hwcaps hwcaps;
struct cqspi_flash_pdata *f_pdata;
struct spi_nor *nor;
struct mtd_info *mtd;
unsigned int cs;
int i, ret;
+ ddata = of_device_get_match_data(dev);
+ if (!ddata)
+ hwcaps.mask = cqspi_base_hwcaps_mask;
+ else
+ hwcaps.mask = ddata->hwcaps_mask;
+
/* Get flash device data */
for_each_available_child_of_node(dev->of_node, np) {
ret = of_property_read_u32(np, "reg", &cs);
@@ -1310,7 +1326,7 @@ static int cqspi_probe(struct platform_device *pdev)
struct cqspi_st *cqspi;
struct resource *res;
struct resource *res_ahb;
- unsigned long data;
+ const struct cqspi_driver_platdata *ddata;
int ret;
int irq;
@@ -1377,8 +1393,8 @@ static int cqspi_probe(struct platform_device *pdev)
}
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
- data = (unsigned long)of_device_get_match_data(dev);
- if (data & CQSPI_NEEDS_WR_DELAY)
+ ddata = of_device_get_match_data(dev);
+ if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
cqspi->master_ref_clk_hz);
@@ -1460,14 +1476,27 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
#define CQSPI_DEV_PM_OPS NULL
#endif
+static const struct cqspi_driver_platdata k2g_qspi = {
+ .hwcaps_mask = cqspi_base_hwcaps_mask,
+ .quirks = CQSPI_NEEDS_WR_DELAY,
+};
+
+static const struct cqspi_driver_platdata am654_ospi = {
+ .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8,
+ .quirks = CQSPI_NEEDS_WR_DELAY,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
- .data = (void *)0,
},
{
.compatible = "ti,k2g-qspi",
- .data = (void *)CQSPI_NEEDS_WR_DELAY,
+ .data = &k2g_qspi,
+ },
+ {
+ .compatible = "ti,am654-ospi",
+ .data = &am654_ospi,
},
{ /* end of table */ }
};
--
2.20.1
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
QSPI controller but supports Octal IO(x8 data lines) and Double Data
Rate(DDR) mode. Add new compatible to support OSPI controller on TI's
AM654 SoCs.
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
v4: No changes
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index bb2075df9b38..4345c3a6f530 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible : should be one of the following:
Generic default - "cdns,qspi-nor".
For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
+ For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
--
2.20.1
On 01/22/2019 08:41 AM, Vignesh R wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current driver to support Octal
> mode. Only Octal SDR read (1-1-8)mode is supported for now.
>
> Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
>
> Signed-off-by: Vignesh R <[email protected]>
> ---
>
> v4: Fix comments by Tudor on v3
> v3: No changes
> v2: Declare Octal mode capability based on compatible.
>
> drivers/mtd/spi-nor/cadence-quadspi.c | 53 +++++++++++++++++++++------
> 1 file changed, 41 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 04cedd3a2bf6..2091addc45a3 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -44,6 +44,12 @@
> /* Quirks */
> #define CQSPI_NEEDS_WR_DELAY BIT(0)
>
> +/* Capabilities mask */
> +#define cqspi_base_hwcaps_mask \
> + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \
> + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \
> + SNOR_HWCAPS_PP)
> +
> struct cqspi_st;
>
> struct cqspi_flash_pdata {
> @@ -93,6 +99,11 @@ struct cqspi_st {
> struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
> };
>
> +struct cqspi_driver_platdata {
> + u32 hwcaps_mask;
> + u8 quirks;
> +};
> +
> /* Operation timeout value */
> #define CQSPI_TIMEOUT_MS 500
> #define CQSPI_READ_TIMEOUT_MS 10
> @@ -101,6 +112,7 @@ struct cqspi_st {
> #define CQSPI_INST_TYPE_SINGLE 0
> #define CQSPI_INST_TYPE_DUAL 1
> #define CQSPI_INST_TYPE_QUAD 2
> +#define CQSPI_INST_TYPE_OCTAL 3
>
> #define CQSPI_DUMMY_CLKS_PER_BYTE 8
> #define CQSPI_DUMMY_BYTES_MAX 4
> @@ -911,6 +923,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
> case SNOR_PROTO_1_1_4:
> f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
> break;
> + case SNOR_PROTO_1_1_8:
> + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
> + break;
> default:
> return -EINVAL;
> }
> @@ -1213,21 +1228,22 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
>
> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
> {
> - const struct spi_nor_hwcaps hwcaps = {
> - .mask = SNOR_HWCAPS_READ |
> - SNOR_HWCAPS_READ_FAST |
> - SNOR_HWCAPS_READ_1_1_2 |
> - SNOR_HWCAPS_READ_1_1_4 |
> - SNOR_HWCAPS_PP,
> - };
> struct platform_device *pdev = cqspi->pdev;
> struct device *dev = &pdev->dev;
> + const struct cqspi_driver_platdata *ddata;
> + struct spi_nor_hwcaps hwcaps;
> struct cqspi_flash_pdata *f_pdata;
> struct spi_nor *nor;
> struct mtd_info *mtd;
> unsigned int cs;
> int i, ret;
>
> + ddata = of_device_get_match_data(dev);
> + if (!ddata)
> + hwcaps.mask = cqspi_base_hwcaps_mask;
Nice!
Reviewed-by: Tudor Ambarus <[email protected]>
> + else
> + hwcaps.mask = ddata->hwcaps_mask;
> +
> /* Get flash device data */
> for_each_available_child_of_node(dev->of_node, np) {
> ret = of_property_read_u32(np, "reg", &cs);
> @@ -1310,7 +1326,7 @@ static int cqspi_probe(struct platform_device *pdev)
> struct cqspi_st *cqspi;
> struct resource *res;
> struct resource *res_ahb;
> - unsigned long data;
> + const struct cqspi_driver_platdata *ddata;
> int ret;
> int irq;
>
> @@ -1377,8 +1393,8 @@ static int cqspi_probe(struct platform_device *pdev)
> }
>
> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> - data = (unsigned long)of_device_get_match_data(dev);
> - if (data & CQSPI_NEEDS_WR_DELAY)
> + ddata = of_device_get_match_data(dev);
> + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
> cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> cqspi->master_ref_clk_hz);
>
> @@ -1460,14 +1476,27 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
> #define CQSPI_DEV_PM_OPS NULL
> #endif
>
> +static const struct cqspi_driver_platdata k2g_qspi = {
> + .hwcaps_mask = cqspi_base_hwcaps_mask,
> + .quirks = CQSPI_NEEDS_WR_DELAY,
> +};
> +
> +static const struct cqspi_driver_platdata am654_ospi = {
> + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8,
> + .quirks = CQSPI_NEEDS_WR_DELAY,
> +};
> +
> static const struct of_device_id cqspi_dt_ids[] = {
> {
> .compatible = "cdns,qspi-nor",
> - .data = (void *)0,
> },
> {
> .compatible = "ti,k2g-qspi",
> - .data = (void *)CQSPI_NEEDS_WR_DELAY,
> + .data = &k2g_qspi,
> + },
> + {
> + .compatible = "ti,am654-ospi",
> + .data = &am654_ospi,
> },
> { /* end of table */ }
> };
>
On Tue, 22 Jan 2019 12:11:37 +0530
Vignesh R <[email protected]> wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current driver to support Octal
> mode. Only Octal SDR read (1-1-8)mode is supported for now.
>
> Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
>
> Signed-off-by: Vignesh R <[email protected]>
> ---
>
> v4: Fix comments by Tudor on v3
> v3: No changes
> v2: Declare Octal mode capability based on compatible.
>
> drivers/mtd/spi-nor/cadence-quadspi.c | 53 +++++++++++++++++++++------
> 1 file changed, 41 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 04cedd3a2bf6..2091addc45a3 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -44,6 +44,12 @@
> /* Quirks */
> #define CQSPI_NEEDS_WR_DELAY BIT(0)
>
> +/* Capabilities mask */
> +#define cqspi_base_hwcaps_mask \
Nit: we usually use upper cases for such definitions.
> + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \
> + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \
> + SNOR_HWCAPS_PP)
> +
> struct cqspi_st;
>
> struct cqspi_flash_pdata {
> @@ -93,6 +99,11 @@ struct cqspi_st {
> struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
> };
>
> +struct cqspi_driver_platdata {
> + u32 hwcaps_mask;
> + u8 quirks;
> +};
> +
> /* Operation timeout value */
> #define CQSPI_TIMEOUT_MS 500
> #define CQSPI_READ_TIMEOUT_MS 10
> @@ -101,6 +112,7 @@ struct cqspi_st {
> #define CQSPI_INST_TYPE_SINGLE 0
> #define CQSPI_INST_TYPE_DUAL 1
> #define CQSPI_INST_TYPE_QUAD 2
> +#define CQSPI_INST_TYPE_OCTAL 3
>
> #define CQSPI_DUMMY_CLKS_PER_BYTE 8
> #define CQSPI_DUMMY_BYTES_MAX 4
> @@ -911,6 +923,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
> case SNOR_PROTO_1_1_4:
> f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
> break;
> + case SNOR_PROTO_1_1_8:
> + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
> + break;
> default:
> return -EINVAL;
> }
> @@ -1213,21 +1228,22 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
>
> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
> {
> - const struct spi_nor_hwcaps hwcaps = {
> - .mask = SNOR_HWCAPS_READ |
> - SNOR_HWCAPS_READ_FAST |
> - SNOR_HWCAPS_READ_1_1_2 |
> - SNOR_HWCAPS_READ_1_1_4 |
> - SNOR_HWCAPS_PP,
> - };
> struct platform_device *pdev = cqspi->pdev;
> struct device *dev = &pdev->dev;
> + const struct cqspi_driver_platdata *ddata;
> + struct spi_nor_hwcaps hwcaps;
> struct cqspi_flash_pdata *f_pdata;
> struct spi_nor *nor;
> struct mtd_info *mtd;
> unsigned int cs;
> int i, ret;
>
> + ddata = of_device_get_match_data(dev);
> + if (!ddata)
> + hwcaps.mask = cqspi_base_hwcaps_mask;
> + else
> + hwcaps.mask = ddata->hwcaps_mask;
> +
> /* Get flash device data */
> for_each_available_child_of_node(dev->of_node, np) {
> ret = of_property_read_u32(np, "reg", &cs);
> @@ -1310,7 +1326,7 @@ static int cqspi_probe(struct platform_device *pdev)
> struct cqspi_st *cqspi;
> struct resource *res;
> struct resource *res_ahb;
> - unsigned long data;
> + const struct cqspi_driver_platdata *ddata;
> int ret;
> int irq;
>
> @@ -1377,8 +1393,8 @@ static int cqspi_probe(struct platform_device *pdev)
> }
>
> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> - data = (unsigned long)of_device_get_match_data(dev);
> - if (data & CQSPI_NEEDS_WR_DELAY)
> + ddata = of_device_get_match_data(dev);
> + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
> cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> cqspi->master_ref_clk_hz);
>
> @@ -1460,14 +1476,27 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
> #define CQSPI_DEV_PM_OPS NULL
> #endif
>
> +static const struct cqspi_driver_platdata k2g_qspi = {
> + .hwcaps_mask = cqspi_base_hwcaps_mask,
> + .quirks = CQSPI_NEEDS_WR_DELAY,
> +};
> +
> +static const struct cqspi_driver_platdata am654_ospi = {
> + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8,
> + .quirks = CQSPI_NEEDS_WR_DELAY,
> +};
> +
> static const struct of_device_id cqspi_dt_ids[] = {
> {
> .compatible = "cdns,qspi-nor",
> - .data = (void *)0,
Can't we have a cqspi_driver_platdata instance for that one too?
> },
> {
> .compatible = "ti,k2g-qspi",
> - .data = (void *)CQSPI_NEEDS_WR_DELAY,
> + .data = &k2g_qspi,
> + },
> + {
> + .compatible = "ti,am654-ospi",
> + .data = &am654_ospi,
> },
> { /* end of table */ }
> };
On 23-Jan-19 2:15 PM, Boris Brezillon wrote:
> On Tue, 22 Jan 2019 12:11:37 +0530
> Vignesh R <[email protected]> wrote:
>
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
>> It also has an integrated PHY. IP register layout is very
>> similar to existing QSPI IP except for additional bits to support Octal
>> and Octal DDR mode. Therefore, extend current driver to support Octal
>> mode. Only Octal SDR read (1-1-8)mode is supported for now.
>>
>> Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
>>
>> Signed-off-by: Vignesh R <[email protected]>
>> ---
>>
>> v4: Fix comments by Tudor on v3
>> v3: No changes
>> v2: Declare Octal mode capability based on compatible.
>>
>> drivers/mtd/spi-nor/cadence-quadspi.c | 53 +++++++++++++++++++++------
>> 1 file changed, 41 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index 04cedd3a2bf6..2091addc45a3 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -44,6 +44,12 @@
>> /* Quirks */
>> #define CQSPI_NEEDS_WR_DELAY BIT(0)
>>
>> +/* Capabilities mask */
>> +#define cqspi_base_hwcaps_mask \
>
> Nit: we usually use upper cases for such definitions.
>
Will fix.
>> + (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \
>> + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \
>> + SNOR_HWCAPS_PP)
>> +
>> struct cqspi_st;
>>
>> struct cqspi_flash_pdata {
>> @@ -93,6 +99,11 @@ struct cqspi_st {
>> struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>> };
>>
>> +struct cqspi_driver_platdata {
>> + u32 hwcaps_mask;
>> + u8 quirks;
>> +};
>> +
>> /* Operation timeout value */
>> #define CQSPI_TIMEOUT_MS 500
>> #define CQSPI_READ_TIMEOUT_MS 10
>> @@ -101,6 +112,7 @@ struct cqspi_st {
>> #define CQSPI_INST_TYPE_SINGLE 0
>> #define CQSPI_INST_TYPE_DUAL 1
>> #define CQSPI_INST_TYPE_QUAD 2
>> +#define CQSPI_INST_TYPE_OCTAL 3
>>
>> #define CQSPI_DUMMY_CLKS_PER_BYTE 8
>> #define CQSPI_DUMMY_BYTES_MAX 4
>> @@ -911,6 +923,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
>> case SNOR_PROTO_1_1_4:
>> f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
>> break;
>> + case SNOR_PROTO_1_1_8:
>> + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
>> + break;
>> default:
>> return -EINVAL;
>> }
>> @@ -1213,21 +1228,22 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
>>
>> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
>> {
>> - const struct spi_nor_hwcaps hwcaps = {
>> - .mask = SNOR_HWCAPS_READ |
>> - SNOR_HWCAPS_READ_FAST |
>> - SNOR_HWCAPS_READ_1_1_2 |
>> - SNOR_HWCAPS_READ_1_1_4 |
>> - SNOR_HWCAPS_PP,
>> - };
>> struct platform_device *pdev = cqspi->pdev;
>> struct device *dev = &pdev->dev;
>> + const struct cqspi_driver_platdata *ddata;
>> + struct spi_nor_hwcaps hwcaps;
>> struct cqspi_flash_pdata *f_pdata;
>> struct spi_nor *nor;
>> struct mtd_info *mtd;
>> unsigned int cs;
>> int i, ret;
>>
>> + ddata = of_device_get_match_data(dev);
>> + if (!ddata)
>> + hwcaps.mask = cqspi_base_hwcaps_mask;
>> + else
>> + hwcaps.mask = ddata->hwcaps_mask;
>> +
>> /* Get flash device data */
>> for_each_available_child_of_node(dev->of_node, np) {
>> ret = of_property_read_u32(np, "reg", &cs);
>> @@ -1310,7 +1326,7 @@ static int cqspi_probe(struct platform_device *pdev)
>> struct cqspi_st *cqspi;
>> struct resource *res;
>> struct resource *res_ahb;
>> - unsigned long data;
>> + const struct cqspi_driver_platdata *ddata;
>> int ret;
>> int irq;
>>
>> @@ -1377,8 +1393,8 @@ static int cqspi_probe(struct platform_device *pdev)
>> }
>>
>> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
>> - data = (unsigned long)of_device_get_match_data(dev);
>> - if (data & CQSPI_NEEDS_WR_DELAY)
>> + ddata = of_device_get_match_data(dev);
>> + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
>> cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
>> cqspi->master_ref_clk_hz);
>>
>> @@ -1460,14 +1476,27 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>> #define CQSPI_DEV_PM_OPS NULL
>> #endif
>>
>> +static const struct cqspi_driver_platdata k2g_qspi = {
>> + .hwcaps_mask = cqspi_base_hwcaps_mask,
>> + .quirks = CQSPI_NEEDS_WR_DELAY,
>> +};
>> +
>> +static const struct cqspi_driver_platdata am654_ospi = {
>> + .hwcaps_mask = cqspi_base_hwcaps_mask | SNOR_HWCAPS_READ_1_1_8,
>> + .quirks = CQSPI_NEEDS_WR_DELAY,
>> +};
>> +
>> static const struct of_device_id cqspi_dt_ids[] = {
>> {
>> .compatible = "cdns,qspi-nor",
>> - .data = (void *)0,
>
> Can't we have a cqspi_driver_platdata instance for that one too?
I had that in v3, will add it back. Thanks for the review!
>
>> },
>> {
>> .compatible = "ti,k2g-qspi",
>> - .data = (void *)CQSPI_NEEDS_WR_DELAY,
>> + .data = &k2g_qspi,
>> + },
>> + {
>> + .compatible = "ti,am654-ospi",
>> + .data = &am654_ospi,
>> },
>> { /* end of table */ }
>> };
>
Regards
Vignesh