Add bindings for Mixel LVDS PHY found on Freescale i.MX8qm SoC.
Signed-off-by: Liu Ying <[email protected]>
---
v1->v2:
* Set fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum. (Krzysztof)
* Skip 'clock-names' property. (Krzysztof)
* Drop 'This patch' from commit message. (Krzysztof)
.../bindings/phy/mixel,lvds-phy.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
new file mode 100644
index 000000000000..4bfcc0dd987f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mixel,lvds-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mixel LVDS PHY for Freescale i.MX8qm SoC
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
+ It converts two groups of four 7/10 bits of CMOS data into two
+ groups of four data lanes of LVDS data streams. A phase-locked
+ transmit clock is transmitted in parallel with each group of
+ data streams over a fifth LVDS link. Every cycle of the transmit
+ clock, 56/80 bits of input data are sampled and transmitted
+ through the two groups of LVDS data streams. Together with the
+ transmit clocks, the two groups of LVDS data streams form two
+ LVDS channels.
+
+ The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
+ by Control and Status Registers(CSR) module in the SoC. The CSR
+ module, as a system controller, contains the PHY's registers.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-lvds-phy
+ - mixel,lvds-phy
+
+ "#phy-cells":
+ const: 1
+ description: |
+ Cell allows setting the LVDS channel index of the PHY.
+ Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#phy-cells"
+ - clocks
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ phy {
+ compatible = "fsl,imx8qm-lvds-phy";
+ #phy-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ };
--
2.25.1
On 20/06/2022 05:45, Liu Ying wrote:
> Add bindings for Mixel LVDS PHY found on Freescale i.MX8qm SoC.
>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v1->v2:
> * Set fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum. (Krzysztof)
> * Skip 'clock-names' property. (Krzysztof)
> * Drop 'This patch' from commit message. (Krzysztof)
>
> .../bindings/phy/mixel,lvds-phy.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> new file mode 100644
> index 000000000000..4bfcc0dd987f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
Name the file fsl,imx8qm-lvds-phy.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mixel,lvds-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mixel LVDS PHY for Freescale i.MX8qm SoC
> +
> +maintainers:
> + - Liu Ying <[email protected]>
> +
> +description: |
> + The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
> + It converts two groups of four 7/10 bits of CMOS data into two
> + groups of four data lanes of LVDS data streams. A phase-locked
> + transmit clock is transmitted in parallel with each group of
> + data streams over a fifth LVDS link. Every cycle of the transmit
> + clock, 56/80 bits of input data are sampled and transmitted
> + through the two groups of LVDS data streams. Together with the
> + transmit clocks, the two groups of LVDS data streams form two
> + LVDS channels.
> +
> + The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
> + by Control and Status Registers(CSR) module in the SoC. The CSR
> + module, as a system controller, contains the PHY's registers.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8qm-lvds-phy
> + - mixel,lvds-phy
This is not specific enough compatible.
> +
> + "#phy-cells":
> + const: 1
> + description: |
> + Cell allows setting the LVDS channel index of the PHY.
> + Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - "#phy-cells"
> + - clocks
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + phy {
> + compatible = "fsl,imx8qm-lvds-phy";
> + #phy-cells = <1>;
> + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
> + power-domains = <&pd IMX_SC_R_LVDS_0>;
> + };
Best regards,
Krzysztof
On Mon, 2022-06-20 at 12:32 +0200, Krzysztof Kozlowski wrote:
> On 20/06/2022 05:45, Liu Ying wrote:
> > Add bindings for Mixel LVDS PHY found on Freescale i.MX8qm SoC.
> >
> > Signed-off-by: Liu Ying <[email protected]>
> > ---
> > v1->v2:
> > * Set fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's
> > enum. (Krzysztof)
> > * Skip 'clock-names' property. (Krzysztof)
> > * Drop 'This patch' from commit message. (Krzysztof)
> >
> > .../bindings/phy/mixel,lvds-phy.yaml | 61
> > +++++++++++++++++++
> > 1 file changed, 61 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-
> > phy.yaml b/Documentation/devicetree/bindings/phy/mixel,lvds-
> > phy.yaml
> > new file mode 100644
> > index 000000000000..4bfcc0dd987f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.yaml
>
> Name the file fsl,imx8qm-lvds-phy.yaml
Will do.
>
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fphy%2Fmixel%2Clvds-phy.yaml%23&data=05%7C01%7Cvictor.liu%40nxp.com%7C8141f62511ab4e19e50708da52a835dc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637913179660099686%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=467HslkQFKI%2FQxOyEpP2io%2BMeogqOTeArcq%2B2hS8W6Q%3D&reserved=0
> > +$schema:
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Cvictor.liu%40nxp.com%7C8141f62511ab4e19e50708da52a835dc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637913179660099686%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=v9tffg9QmyP150hLYv%2FLikQJNY%2FW51ViZsUKku2yTMs%3D&reserved=0
> > +
> > +title: Mixel LVDS PHY for Freescale i.MX8qm SoC
> > +
> > +maintainers:
> > + - Liu Ying <[email protected]>
> > +
> > +description: |
> > + The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
> > + It converts two groups of four 7/10 bits of CMOS data into two
> > + groups of four data lanes of LVDS data streams. A phase-locked
> > + transmit clock is transmitted in parallel with each group of
> > + data streams over a fifth LVDS link. Every cycle of the transmit
> > + clock, 56/80 bits of input data are sampled and transmitted
> > + through the two groups of LVDS data streams. Together with the
> > + transmit clocks, the two groups of LVDS data streams form two
> > + LVDS channels.
> > +
> > + The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
> > + by Control and Status Registers(CSR) module in the SoC. The CSR
> > + module, as a system controller, contains the PHY's registers.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8qm-lvds-phy
> > + - mixel,lvds-phy
>
> This is not specific enough compatible.
Will use mixel,28fdsoi-lvds-1250-8ch-tx-pll.
Thanks,
Liu Ying